200401603 (1) 玖、發明說明 【發明所屬之技術領域】 ' 本發明是有關一種屏蔽線，更詳細是有關形成在多層 基板內的屏蔽線，以及積層該多層基板的電子電路元件及 半導體晶片。 【先前技術】 近年廣泛使用個人電腦、攜帶型電話等利用高頻的電 φ 氣機器。而該些機器正促進輕薄短小化，包括使用半導體 封裝基板的印刷基板、1C、電子零件正急速進行小型化。 隨著該傾向，該些基板、1C、電子零件也成爲一種導體彼 此非常接近的構造。而且各元件配置得非常接近。 ~ 因此，例如會有在信號線近傍產生電磁波的機器或是 、 元件的情形，達到某一定以上的雜訊位準，信號就會混亂 發產誤動作。近年該問題發生很多，急於對應。現狀是以 元件配置最適化、全體屏蔽等來對應。 Φ 但是元件配置的最適化，基本上不但會重複試行錯誤 ，效率還非常差。有關屏蔽也是以機器或是元件全體以銅 板或是銅爲主成份的電糊硬化物覆蓋。但是種此覆蓋機器 全體的方法，對於在機器內部發生雜訊得不到效，用覆蓋 元件的方法會有高密度實裝變困難等，問題較多。進而近 年一般多層基板’在基板內部也有電磁波的發生源，無法 應用上述的外部屏蔽。 高頻電路在此是爲了避免產生雜訊，將後述同軸電纜 -5- (2) (2)200401603 狀的構造亦即應用於基板內層之信號傳送的條線之上下， 以寬大面積’理想上是能廣泛應用以具有無限大面積的 GND面隔開的構造。但是該構造應用於近年小型化的機 器上，需要寬大的面積，不適當的點較多。 在與基板平面垂直的方向具有電路面的多層線圈及其 製造方法，例如很適合晶片感應器，於日本特開平第11-251146號公報等揭示複數個。但是有該些方法中完全沒 有記載有關爲了減少配線在與基板平行的平面的信號線和 對該信號線受外部電磁雜訊的影響，在與基板平面垂直的 方向形成線圈的方法。亦即有關像是線圈內部貫通別的電 路的構造完全未提及。 而用於1C的，於曰本特開平第11-2〗4622號公報中 則揭示著將多重圓筒形線圈形成在半導體基板周圍的方法 。該方法是屬於欲得到更大感應器的發明，但同時對於迴 避其內部元件的雜訊也很有效。但是此方法不得於線圏部 分使用非常多的體積，由小型化的觀點來看非常有問題。 而與前述晶片感應器情形同樣的，針對線圈內部貫通別的 電路的構造並未提及。 對於像是信號線爲了由雜訊來保護傳遞重要資訊的電 路，其周圍以導體覆蓋是最有效。像這樣除了前述條線以 外，還有同軸電纜。例如從電視天線連接至接收器的信號 線，其周圍是用鋼被覆，來自於外部雜訊的影響少。同軸 電纜與條線不同，不需要寬大面積的GND面。因而認爲 只要能將由類似此種同軸電纜的構造形成的屏蔽線’形成 (3) (3)200401603 在多層基板（印刷基板）內，有效遮蔽雜訊和小型化就能併 存。並認爲藉由將此種多層基板積層在半導體晶片UC) ' 電子電路元件，就能在信號線上製造使用此種小型屏蔽線 的半導體晶片（1C)、電子電路元件。在此考慮在屏蔽線的 外部導體使用線圈狀導體、編織狀導體、條狀導體等的小 型屏蔽線，但此種構造的屏蔽線習知並不存在。 本發明課題在於提供一種省空間並且能於高頻領域中 由電磁波遮蔽重要信號線的多層基板內屏蔽線、及其製造 方法。 [發明內容】 若按照本發明，上述課題可經以下手段達成。於申請 專利範圍第1項記載的發明乃屬於其特徵爲具有：與多層 基板一體形成的線圏中’包括平行於該多層基板的捲線部 分以及垂直於該多層基板的捲線部分的線圈、和屬於與前 述多層基板一體形成的導線’而形成在前述線圈內部的導 線。 如申請專利範圍第2項所記載的發明，前述線圈的單 位捲線從與鄰接的其他單位捲線同方向觀看時，分別具有· 互相反向旋轉的螺旋狀圖案’以及互相鄰接的單位捲線彼 此乃於該螺旋狀圖案的削端彼此或末端彼此交互連接。 如申請專利範圍第3項所記載的發明，乃加上申請專 利範圍第1或2項所記載的發明特徵，前述線圈乃爲積層 平行於則述多層基板的捲線部分，形成作爲導電層的一部 (4) (4)200401603 分’重直於前述多層基板的捲線部分，形成作爲透過前述 絕緣層而連接鄰接的前述導電層間的突起電極爲其特徵。 如申請專利範圍第4項所記載的發明，乃加上申請專 利範圍第1或2項所記載的發明特徵，前述線圈乃爲利用 積層法平行於前述多層基板的捲線部分，形成作爲積層的 導電層的一部分，垂直於前述多層基板的捲線部分，形成 作爲通過則述絕緣層而連接鄰接的前述導電層間的導孔或 是通孔爲其特徵。 如申請專利範圍第5項所記載的發明，乃具有：屬於 與多層基板一體形成的外部導體’而包括平行於該多層基 板的導體部分以及垂直於該多層基板的導體部分的外部導 體、和屬於與前述多層基板一體形成的導線，而形成在前 述外部導體內部的導線爲其特徵。 如申請專利範圍第6項所記載的發明，乃加上申請專 利範圍第5項所記載的發明特徵’前述外部導體乃爲平行 於前述多層基板的導體部分是屬於條狀導體爲其特徵。 如申i靑專利範圍第7項所記載的發明，乃加上申請專 利範圍第5項或第6項所記載的發明特徵，前述外部導體 乃爲平行於前述多層基板的導體部分，形成作爲積層的導 電層的一部分’垂直於前述多層基板的導體部分，形成作 爲透過前述絕緣層而連接鄰接的前述導電層間的突起電極 爲其特徵。 如申請專利範圍第8項所記載的發明，乃加上申請專 利範圍第5項或第6項所記載的發明特徵，前述外部導體200401603 (1) 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to a shielded wire, and more specifically to a shielded wire formed in a multilayer substrate, and an electronic circuit element and a semiconductor wafer laminated with the multilayer substrate. [Prior technology] In recent years, personal computers, portable telephones, and other high-frequency electric appliances have been widely used. These devices are promoting thinning, miniaturization, and miniaturization of printed circuit boards, 1C, and electronic components that use semiconductor package substrates. With this tendency, the substrates, 1C, and electronic components also have a structure in which the conductors are very close to each other. And the components are arranged very close together. Therefore, for example, there may be a case where a device or a component that generates electromagnetic waves near a signal line reaches a certain noise level or more, and the signal may malfunction and malfunction. This problem has occurred a lot in recent years, and we are eager to respond. The current situation is to respond to the optimization of component layout and overall shielding. Φ However, the optimization of component configuration will basically not only make repeated trial and error, but also the efficiency is very poor. The shield is also covered with a hardened electrical paste made of copper or copper as the main component of the machine or components. However, this method of covering the entire machine is not effective for the occurrence of noise inside the machine, and the method of covering the components will make high-density mounting difficult, etc., and there are many problems. Furthermore, in recent years, a general multilayer substrate 'has an electromagnetic wave generation source inside the substrate, and the above-mentioned external shielding cannot be applied. The high-frequency circuit is here to avoid noise, and the coaxial cable described below-5- (2) (2) 200401603-like structure, that is, applied to the signal transmission lines on the inner layer of the substrate, with a large area 'ideal The above structure can be widely applied with a GND plane separated by an infinite area. However, this structure is applied to machines that have been miniaturized in recent years, requiring a large area, and there are many inappropriate points. A multilayer coil having a circuit surface in a direction perpendicular to the plane of the substrate and a method for manufacturing the same are suitable for a wafer inductor, for example, and disclosed in Japanese Patent Application Laid-Open No. 11-251146. However, none of these methods describes a method of forming a coil in a direction perpendicular to the plane of the substrate in order to reduce the signal line of the wiring in a plane parallel to the substrate and to prevent the signal line from being affected by external electromagnetic noise. In other words, there is no mention about the structure of other circuits passing through the coil. For 1C, Japanese Patent Application Laid-Open No. 11-2〗 4622 discloses a method of forming a multi-cylindrical coil around a semiconductor substrate. This method belongs to the invention of getting larger sensors, but it is also effective to avoid noise from its internal components. However, this method must not use a very large volume in the coil section, which is very problematic from the viewpoint of miniaturization. As in the case of the aforementioned chip inductor, the structure for penetrating other circuits inside the coil is not mentioned. For a circuit such as a signal line to protect important information from noise, it is most effective to cover it with a conductor. In addition to the aforementioned wires, there are coaxial cables like this. For example, the signal line connected from the TV antenna to the receiver is covered with steel around it, and has little influence from external noise. Coaxial cables are not the same as strip cables, and do not require a large GND plane. Therefore, it is considered that as long as a shielded wire formed by a structure similar to this type of coaxial cable can be formed (3) (3) 200401603 in a multilayer substrate (printed substrate), it is possible to coexist effectively shielding noise and miniaturization. It is thought that by stacking such a multi-layer substrate on a semiconductor wafer (UC) 'electronic circuit element, a semiconductor chip (1C) or an electronic circuit element using such a small shielded wire can be manufactured on a signal line. Here, it is considered that a small-sized shielded wire such as a coiled conductor, a braided conductor, or a strip-shaped conductor is used as the outer conductor of the shielded wire, but a shielded wire of this structure is not known. An object of the present invention is to provide a shielded wire in a multilayer substrate which saves space and shields important signal lines by electromagnetic waves in a high-frequency field, and a method for manufacturing the same. [Summary of the Invention] According to the present invention, the above-mentioned problems can be achieved by the following means. The invention described in item 1 of the scope of the patent application is characterized by having a coil including a winding portion parallel to the multilayer substrate and a coil perpendicular to the winding portion of the multilayer substrate in a line formed integrally with the multilayer substrate, and belonging to The lead wire formed integrally with the multilayer substrate is a lead wire formed inside the coil. According to the invention described in claim 2 of the scope of patent application, when the unit windings of the aforementioned coils are viewed from the same direction as the adjacent unit windings, they each have a spiral pattern that rotates in opposite directions to each other and the unit windings adjacent to each other The cut ends of the spiral pattern are alternately connected to each other or to each other. For example, the invention described in item 3 of the scope of patent application is added with the features of invention in item 1 or 2 of scope of patent application. The aforementioned coil is a layer that is parallel to the winding part of the multilayer substrate and forms a conductive layer. Part (4) (4) 200401603 is characterized in that it is straight to the winding portion of the multilayer substrate and forms a protruding electrode that connects the adjacent conductive layers through the insulating layer. If the invention described in item 4 of the patent application scope is added to the invention feature described in item 1 or 2 of the patent application scope, the coil is formed by using a lamination method in parallel with the winding portion of the multilayer substrate to form a conductive layer. A part of the layer is perpendicular to the winding portion of the multilayer substrate, and is characterized by forming a via hole or a through hole connected between the conductive layers adjacent to each other through the insulating layer. The invention described in claim 5 of the scope of patent application has an external conductor that belongs to an external conductor integrally formed with the multilayer substrate, and includes a conductor portion parallel to the multilayer substrate and a conductor portion perpendicular to the conductor portion of the multilayer substrate, and A conductive wire formed integrally with the multilayer substrate, and a conductive wire formed inside the external conductor is a feature of the conductive wire. If the invention described in claim 6 of the patent application scope is added with the invention feature described in claim 5 of the patent application scope ', the feature that the outer conductor is a strip conductor that is parallel to the conductor portion of the multilayer substrate is characteristic. If the invention described in item 7 of the patent application is added to the features of the invention described in item 5 or 6 of the patent application scope, the external conductor is a conductor portion parallel to the multilayer substrate, and is formed as a laminate. A part of the conductive layer ′ is perpendicular to the conductive portion of the multilayer substrate, and it is characterized in that a protruding electrode is formed to connect the adjacent conductive layers through the insulating layer. If the invention described in item 8 of the patent application is added to the features of the invention described in item 5 or 6 of the patent application, the aforementioned external conductor
-8- (5) (5)200401603 乃爲利用積層法平行於前述多層基板的導體部分，形成作 爲積層的導電層的一部分，垂直於前述多層基板的導體部 分，形成作爲通過前述絕緣層而連接鄰接的前述導電層間 的導孔或是通孔。 如申請專利範圍第9項所記載的發明，乃於外面積層 包括如申請專利範圍第1項至第8項的任一項所記載的多 層基板內屏蔽線的多層基板爲其特徵。 如申請專利範圍第1 〇項所記載的發明，乃搭載於包 括如申請專利範圍第1項至第8項的任一項所記載的多層 基板內屏蔽線的多層基板上爲其特徵。 如申請專利範圍第1 1項所記載的發明，乃具備有： 形成構成多層基板的一層絕緣層的步驟；和將平行於 前述多層基板的線圈的捲線部分的至少一部分形成在前述 多層基板內的絕緣層上的步驟；和將導線介著該線圈與前 述絕緣層形成在前述線圈內側的步驟；和形成平行於前述 多層基板的線圈的前述捲線部分的至少一部分彼此在絕緣 層間電氣連接的垂直連接部，且藉此形成垂直於前述多層 基板的線圈的捲線部分的至少一部分的步驟；和直至形成 絕緣層的前述步驟、形成平行於前述多層基板的線圏的捲 線部分的至少一部分的前述步驟、以及形成垂直於前述多 層基板的線圈的捲線部分的至少一部分的前述步驟的至少 任一步驟，在行平於前述多層基板的線圈的捲線部分與垂 直於前述多層基板的線圈的捲線部分形成支撐前述多層基 板內的所定線圈爲止，針對目前所形成的多層基板的部分 (6) (6)200401603 加以適當反覆的步驟爲其特徵。 如申請專利範圍第1 2項所記載的發明’乃加上申請 專利軺圍桌11項所記載的發明特徵，前述所定線圈的單 位捲線從與鄰接的其他單位捲線同方向觀看的時候，分別 具有互相反向旋轉的螺旋狀圖案，以及前述所定線圈互相 鄰接的單位捲線的組合乃於前述螺旋狀圖案的前端彼此或 末端彼此交互連接爲其特徵。 如申請專利範圍第1 3項所記載的發明，乃具備有： 形成構成多層基板的一層絕緣層的步驟；和將平行於 前述多層基板的外部導體的導體部分的至少一部分形成在 前述多層基板內的絕緣層上的步驟；和將導線介著該外部 導體與前述絕緣層形成在前述外部導體內側的步驟；和形 成平行於前述多層基板的外部導體的前述導體部分的至少 一部分彼此在絕緣層間電氣連接的垂直連接部，且藉此形 成垂直於前述多層基板的外部導體的導體部分的至少一部 分的步驟；和直至形成絕緣層的前述步驟、形成平行於前 述多層基板的外部導體的導 體部分的至少一部分的前述步驟、以及形成垂直於前 述多層基板的外部導體的導體部分的至少一部分的前述步 驟的至少任一步驟，在行平於前述多層基板的外部導體的 導體部分與垂直於前述多層基板的外部導體的導體部分形 成支撐前述多層基板內的所定外部導體爲止，針對目前所 形成的多層基板的部分加以適當反覆的步驟爲其特徵。 如申請專利範圍第1 4項所記載的發明，乃加上申請 -10- (7) (7)200401603 專利範圍第1 3項所記載的發明特徵，平行於前述外部導 體的多層基板的導體部分乃屬於條狀導體爲其特徵。 如申請專利範圍第1 5項所記載的發明，乃加上申請 專利範圍第1 1項至第1 4項的任一項所記載的發明特徵， 前述多層基板內屏蔽線乃爲積層在半導體晶圓的外面，更 具有將積層前述多層遮板內屏蔽線的前述半導體晶圓切割 成半導體晶片單位的步驟爲其特徵。 如申請專利範圍第1 6項所記載的發明，乃加上申請 專利範圍第1 1項至第1 4項的任一項所記載的發明特徵， 前述多層基板內屏蔽線乃爲積層在半導體晶片的外面爲其 特徵。 如申請專利範圍第1 7項所記載的發明，乃加上申請 專利範圍第1 1項至第1 4項的任一項所記載的發明特徵， 於' 包括前述多層基板內屏蔽線的多層製板上搭載電子電路 元件爲其特徵。 【實施方式】 以下針對本發明實施形態邊參照圖面邊說明。由此針 对有關本發明第一實施形態的多層基板內屏蔽線1的構成 做說明。第1圖是表示多層基板內屏蔽線1的槪略構 成立體圖。多層基板內屏蔽線1是由線圈la、導線lb以 及多層基板lc所構成。線圏la是於多層基板的複數個絕 緣層及導電層的各個形成步驟中’形成作爲導電層的一部 ^ 屬作爲屏敝線之外部導體功能的構成要素。線圈 -11 - 200401603 (δ) 1 a乃屬於中心軸平行於多層基板，包括平行於多層基板 的捲線部分以及垂直於該多層基板的捲線部分。線圈1 a 最適合斷面形狀爲重複四角形、圓形等導線圖案的單位捲 線以電氣式串接而連接的形態所構成。本詳細說明書中的 線圈1 a以及該單位捲線的形態乃廣泛包括欲作爲屏蔽線 之外部導體功能的任何形態。最適合是平行於線圈1 a的 多層基板的捲線部分是形成積層的導電層的一部分，垂直 於多層基板的捲線部分是形成作爲透過絕緣層而連接鄰接 的導電層間的突起電極、導孔或是通孔等。像這樣藉由形 成線圈1 a ’利用積層法等公知的多層基板（印刷基板）製造 技術’可在多層基板之製造工程中，將線圈1 a同時形成 在多層基板內。導線lb可在多層基板之製造工程中，介 著線圈1 a與絕緣層形成在線圈1 a的內部。多層基板1c 是屬於積層絕緣層而構成的基板。再者，實際的多層基板 lc之形成步驟是交互積層絕緣層與導電層。然後導電層 的部分是屬於前述線圈1 a的一部分，其他絕緣層的部分 屬於多層基板1C。 其次，針對有關本發明第二實施形態的多層基板內屏 蔽線2之構成做說明。第1圖（b)是表示多層基板內屏蔽 線2的槪略構成立體圖。多層基板內屏蔽線2是由線圈 2a '導線2b以及多層基板2c所構成。線圈2a的單位捲 線在從與鄰接的其他單位捲線同方向觀看時，分別具有反 向旋轉的螺旋狀圖案，以及互相鄰接的單位捲線彼此乃於 該螺旋狀圖案的前端彼此或末端彼此互相連接。藉由像這 酿 -12 - 200401603 Ο) 樣構成線圈2 a ’就能令單位捲線內的圏數變得更大，得 到更大的屏蔽效果。導線2b及多層基板2c乃爲與第一實 施形態同樣的構成要素。 其次，針對有關本發明第三實施形態的多層基板內屏 蔽線3的構成做說明。第1圖（c)是表示多層基板內屏蔽 線3的槪略構成立體圖。多層基板內屏蔽線3是由外部導 體3 a、導線3 b以及多層基板3 c所構成。外部導體3 a是 包括平行於多層基板3 c的導體部分以及垂直於該多層基 板的導體部分。該導體部分可爲條帶狀也可爲線狀。第i 圖（Ο是表示由線狀導體部分形成的編織形外部導體實例 。導線3 b及多層基板3 c是屬於與第一實施形態同樣的構 成要素。 其次，針對有關本發明第四實施形態的多層基板內屏 蔽線4的構成做說明。第1圖（d)是表示多層基板內屏蔽 線4的槪略構成立體圖。多層基板內屏蔽線4是由外部導 體（平行於多層基板4d的平行外部導體4a以及垂直於多 層基板4d的垂直外部導體4b)、導線4以及多層基板4d 所構成。平行外部導體4 a是屬於條狀導體。藉由此種構 成，於多層基板的積層工程中，就不需要對平行多層基板 4c的導體部分進行微細形狀蝕刻的處理，同時沒有線以 面遮蔽的緣故，具有屏蔽效果高的優點。垂直外部導體 4b最適合線狀的導體。導線4c以及多層基板4d乃屬於 與第一實施形態同樣的構成要素。第1圖（e)及（f)是其他 線圏的構造例。該些例子中，只在平行或正交線圈中心軸 齡| -13- (10) (10)200401603 方向的捲線部分構成線圈。 由此針對多層基板內屏蔽線1〜4的動作做說明。多 層基板內屏蔽線1〜4也很適合使用作爲將構成單片I c等 的半導體晶片安裝在其上的插入件。而多層基板內屏蔽線 1〜4可將其他電路元件形成在其內部或安裝在外部，可 像這樣構成將以其他電路元件與多層基板內屏蔽線1〜4 所構成的電路功能附加在半導體晶片本身功能的半導體封 裝。多層基板內屏蔽線1〜4可藉由調整線圈或外部導體 伸長方向’簡便且任意地設定屏蔽線的長度。多層基板內 屏蔽線1〜4很適合對內部導線流入受到雜訊影響信號不 佳等等的電流。此時，遮蔽静電感應式的雜訊的時候，能 以線圏或外部導體的任一點接地。藉此達成静電遮蔽。而 遮蔽電磁感應式的雜訊的時候，藉由流入導線的電流回路 作爲線圈或外部導體，就可同樣作爲同軸電纜使用。藉此 達成電磁遮蔽。而且導線不但不會受到來自外部雜訊的影 響’導入導線導線的電流也不會受到周邊其他配線、元件 等的影響。 本發明乃屬於將該同軸電纜類似的構造應用於印刷基 板、1C、電子機器的信號線。亦即，藉由依序進行形成與 基板平面平行的絕緣層、開孔以及形成導體圖案，在與基 板平面平行地形成線圈的一部分，且藉由重複該順序而形 成電氣連接，就能在與基板平面垂直的方向螺旋狀地形成 具有電路面的線圈狀電路。製作該些線圈時，藉由事先在 與基板平面平行的方向形成信號線，就能一併在與基板平 (11) (11)200401603 面垂直的方向以及平面方向的兩個方向形成電路。 同樣的構造是在與基板平面平行的平面形成線圈，也 可利用導孔形成貫通其中的信號線。但是信號線非常纖細 ’很難在與基板垂直的方向形成非常均勻的電路。事實上 更不可只在與基板平面垂直的方向形成信號線，必定會產 生需要形成在與基板平面平行的平面。用此方法就不可能 形成屏蔽形成在與基板平面平行之平面的信號線。 而若利用本發明的方法，就能簡便地只在所希望的部 分得到線圈。也能成爲目前完全沒有方法解決在基板內部 的電磁波對策。進而需要的話，在可能產生電磁波的某部 位應用此方法’也能成爲電磁波不會洩漏至該部位外部的 構造。 此時’本發明的方法乃如一般的同軸電纜，不能完全 覆蓋信號線的周圍，但是近年來以電子、電氣機器爲主流 的高頻領域’據知就連本發明的方法亦即「覆蓋」有間隙 的構造’在屏蔽效果上也沒問題。更因爲本發明的方法能 在基板平面的任意方向設定線圈的伸長方向，配合需要也 能在任一方向以同一製程形成線圈。 其次，針對本發明的多層基板內屏蔽線1〜4之製造 方法’一同說明與習知技術比較的優點。第1圖（a)所示 是針對使用單層線圈的屏蔽以有機材料作爲絕緣體使用的 多層基板內屏蔽線1的情形做說明。首先如第2圖所示， 準備一形成有屬於線圈一部分的通孔和屬於信號線的導體 1 b的核心基板1 d。材料可使用公知慣用的銅張積層板例 -15- (12) (12)200401603 如玻璃環氧樹脂、雙馬來酸酐縮亞胺三氮雜苯基板，或是 使用誘電特性優的聚苯醚樹脂、聚醚醚銅樹脂、苯環丁烯 苯環丙稀樹脂等的基板。開孔可利用鑽孔器或碳酸氣體雷 射' YAG雷射等廣泛使用的方法進行。導體的圖案化可 利用減成法、加成法等公知慣用的方法進行。 接著在核心基板丨d的兩面，如第8圖積層形成最外 層1 e °絕緣層的材料、開孔方法、圖案化方法可使用與 核心材料同樣的材料、方法。 最外層的積層、形成是針對內層材料，於兩面製作絕 緣層’進而製作導電層，就能進行圖案化以及電氣連接。 針對幾種方法具體舉例說明。 針對所謂增層法的情形做說明。在由上述內層材料製 成的基板上形成絕緣層。絕緣層可使用玻璃環氧系或是醯 胺樹脂系等等的黏合膠片、液狀或是薄膜狀的熱可塑或是 熱硬化性的樹脂組成物，或是一般稱爲具樹脂的銅箔、銅 箔與絕緣樹脂層一體化的等等。 絕緣層的形成乃例如如以下施行。如第4圖（a)所示 ’在上述核心基板Id的兩面配置黏合膠片類5、未圖案 化的銅箱6，或是如第4圖（b)所示具樹脂的銅范7，如第 5圖所示利用積層加壓法將該些一併積層、硬化，製成— 體化的絕緣層和導電層。或是如第6圖所示，形成上述基 板1 d上利用網版印刷、簾幕式塗佈、噴塗法等等公知慣 用的方法塗佈液狀組成物，且用UV、電子線、加熱等等 使之硬化。或是在上述基板上利用滾壓、層壓等等的方法 -16- (13) (13)200401603 貼合薄膜狀組成物，並利用所定的方法使之硬化，得到絕 緣層8。 接著形成導孔。在以上述方法得到的基板的所定位置 利用鑽孔器、雷射等形成導孔9。第7圖（a)是用黏合膠片 5與銅箔6當作絕緣層及導電層時，同樣地第7圖（b)是針 對使用具樹脂的銅箔7、第7圖（c)是針對使用液狀或薄膜 狀的熱可塑性或是熱硬化性的樹脂組成物8的情形而記載 。使用黏合膠片類或是具樹脂的銅箔並與絕緣層一同形成 導電層時’使用廣泛用於形成盲導孔的碳酸氣體雷射的時 候’可配合需要事先用蝕刻除去所定位置的導電體，施行 所謂遮罩加工。 使用黏合膠片類或具樹脂的銅箔，與絕緣層一同形成 導電層時，例如第8圖（a)所示於導孔將配合銀、銅等導 電性粉末的導電糊1 〇利用印刷 '去除等方法埋置，並利 用所定方法使之硬化。或是如第8圖（b)所示，於一般的 通孔電鍍亦即導孔內獲得電鍍觸媒後，進行無電解電鍍， 接著利用施行電解電鍍的方法，連利用形成電鍍層1 1的 方法也會達成電氣連接。使用液狀或薄膜狀的組成物形成 絕緣層的時候，如第8圖（c)所示，例如壓合銅箔1 2，且 於絕緣層外側形成導電層，在所定位置進行遮罩加工後， 經導電糊1 0或電鍍層1 1加以導電化連接盲導孔。此時可 先進行盲導孔的導電化。並如第8圖（d)所示，使形成絕 緣層 '盲導孔的基板獲得觸媒，進行無電解電鍍處理，接 著配合需要進行電解電鍍處理，藉此也能一倂施行形成導 -17- (14) (14)200401603 電層1 3和肓導孔導電化。此時，盲導孔的導電化也可利 用導電糊施行。 $胃胃&以下方法，絕緣層和導電層也可一併施行電 氣連接。亦即如第9圖所示，在內層電路1 d上的所定位 置’使用導電糊等形成前端尖銳的導電性突起電極14後 ’於配合黏合膠片5和銅箔6 (第9圖（a))，或是薄膜狀絕 緣體8和銅箔6(第9圖（b))，或是具樹脂的銅箔7後，藉 由施行壓合加工（第9圖（c))的尖銳導電性突起電極14會 貫通絕緣層’實現與導電層的連接。 再者’使用利用電鍍連接的通孔基板，使用上述液狀 或薄膜狀的絕緣材料的時候，或是一旦更積層在利用增層 法形成的盲導孔的某一絕緣層，的時候，可利用埋孔用的 油墨或是電鍍處理來埋設通孔或是盲導孔，使表面平滑化 〇 或者也可利用以下方法一併積層。絕緣層是針對使用 玻璃環氧系的黏合膠片的四層構造情形做說明。亦即，如 第10圖所示，在銅張單面玻璃環氧基板的基材15的所定 位置，使用雷射等進行開孔加工。接著’以銅箔1 6爲電 極進行電氣電鍍，以電鍍17塡充所產生的孔穴。在其上 緊接著利用電鍍法製作低融點的金屬突起電極1 8。 銅箔1 6乃如第1 1圖所示蝕刻加工成所定圖案。再者 ，當以平行於外部導體的多層基板的導體部分爲條狀導體 時（多層基板內屏蔽線4的情形）’就不需要該蝕刻加工。 在突起電極側薄薄的塗佈與絕緣層所用之同樣的組成物 -18- (15) (15)200401603 1 9，且使之半硬化。由該單面基板製造的作爲最外層亦即 第1層及第4層。 接著，如第12圖所示，使內層Id與第11圖的最外 層定位，藉由壓合加工使其半硬化的組成物，從突起電極 部切除，形成層間絕緣層的同時，突起電極部會與內層的 導電體電氣連接，貫通具有四層構造的線圈，製造配置有 信號線的多層基板內屏蔽線1。藉由應用該方法，也很容 易施行更多層化。 螺旋狀圖案欲更密時，需要更多層化。無論使用上述 那種方法均可更多層化。 藉此對應該些方法，配合需要也很容製造例如利用第 1圖（b)所的多層線圈屏蔽信號線構造的多層基板內屏蔽線 2、具有編織形等外部導體的多層基板內屏蔽線3。 而以上述各種積層方法製造各種基板之際，在所定位 置應用上述方法的話，也容易製造含有本發明之多層基板 內屏蔽線1〜4構造的電子電路元件。 絕緣材料中應用陶瓷材料時，基本上也與有機材料同 樣的工程亦即在各層形成線圈的一部分以及信號線，且藉 由積層這個就能製造完成。以往所施行的方法是依序施行 空白薄片的開孔、利用導電糊的埋孔以及圖案印刷、積層 、燒成就能形成本發明的屏蔽線。 於以下表示在半導體基板上同時形成在與基板平面平 行的方向具有中心軸的線圈或是外部導體與導線的過程。 表示形成電晶體，且在更用鎢等形成電極部的矽晶圓之所 (16) (16)200401603 謂上層的電極配線層，形成第1圖的多層基板內屏蔽線1 的構造例。藉由應用該方法，就可任意設定轉數、歹(1 (層） 數、形成方向等。 首先如第1 3圖所示，於形成電晶體、電極部的砂晶 圓20上形成最下層的絕緣層21。使用CVD等氣相法形 成矽氧化膜，或是將近年受注目的聚醯亞胺、苯環丁烯等 有機素材旋塗後進行事後烘乾就可以形成。接著，如第 14圖所示，使用各種雷射形成需位置的孔22。孔22是在 與下層電極部進行電氣連接的位置。接著，如第1 5圖所 示，形成導電性圖案23。一般使用的鋁濺鍍或是銅層， 是用 CVD等氣相法或是電鍍法等濕式法所形成。接著進 行曝光、蝕刻並予圖案化。此時也可在先形成圖案化的光 阻層後進行導電化。在該工程中於第1 4圖所示的工程中 所開設的孔22也可導電化，第一層與第二層就會電氣連 接。再者，於曝光工程前’一般藉由組合物理式硏磨，或 是稱爲C Μ P法的化學式硏磨和物理式硏磨的方法等，令 表面平坦化。 其次，如第16圖，形成第二絕緣層24。接著如第17 圖’再次開孔，利用形成導體圖案來形成第二層的導電性 圖案2 5。此時，也能同時形成導線。接著如第1 8圖，利 用前述方法形成第三絕緣層2 6，且施以開孔、導電化、 圖案化，形成第三導電性圖案2 7的同時取得第二層、第 三層的導通。在此階段，如第1圖所示，後續就可形成在 半導體上。應用該操作的話，就能簡便地施行轉數的增減 -20- (17) 200401603 、歹U (層）數的增減、具有不同伸長方向的複數個屏蔽線的 形成等。 形成絕緣層、開孔後，在形成導電層的同時，進行線 間的電氣連接之際，如第1 9圖所示，以導電體2 9塡充孔 部分（導孔）28的話，如第20圖所示，線圈斷面就能再次 於一般稱爲疊層導孔的構造亦即塡充的導孔上形成具有導 孔的構造，線圏的邊界可爲直線。-8- (5) (5) 200401603 is used to form a part of the conductive layer which is parallel to the conductor portion of the multilayer substrate by the lamination method, and is formed to be connected by the insulating layer perpendicular to the conductor portion of the multilayer substrate. Vias or vias between adjacent conductive layers. The invention described in item 9 of the scope of patent application is characterized in that the outer area layer includes a multilayer substrate including a shield wire in the multilayer board of any one of the scope of claims 1 to 8 in the scope of patent application. The invention described in the patent application scope item 10 is characterized by being mounted on a multilayer substrate including a shielded wire in the multilayer substrate described in any one of the patent application scope items 1 to 8. The invention described in claim 11 of the patent application scope includes: a step of forming an insulating layer constituting a multilayer substrate; and forming at least a part of a winding portion of a coil parallel to the multilayer substrate in the multilayer substrate. A step on the insulating layer; and a step of forming a lead through the coil and the insulating layer inside the coil; and forming a vertical connection where at least a part of the coiled portion of the coil parallel to the multilayer substrate is electrically connected to each other between the insulating layers A step of forming at least a part of a coiled portion of a coil perpendicular to the multilayer substrate; and a step of forming an insulating layer, a step of forming at least a portion of a coiled portion of a coil parallel to the coil of the multilayer substrate, And at least one of the foregoing steps of forming at least a part of a coiled portion of a coil perpendicular to the multilayer substrate, the coiled portion of the coil that is parallel to the multilayer substrate and the coiled portion of the coil that is perpendicular to the multilayer substrate are formed to support the foregoing Up to a predetermined coil in a multilayer substrate It is characterized by appropriately repeating the steps (6) (6) 200401603 of the currently formed multilayer substrate. For example, the invention described in item 12 of the scope of patent application is the invention described in item 11 of the patent application table. When the unit windings of the aforementioned predetermined coils are viewed from the same direction as the adjacent unit windings, they have each other. The combination of the spiral pattern in the reverse rotation and the unit windings of the predetermined coils adjacent to each other are characterized by the front ends or the ends of the spiral patterns being connected to each other alternately. The invention described in claim 13 of the scope of patent application includes: a step of forming an insulating layer constituting a multilayer substrate; and forming at least a portion of a conductor portion of an outer conductor parallel to the multilayer substrate in the multilayer substrate. A step on the insulating layer; and a step of forming a wire inside the outer conductor through the outer conductor and the insulating layer; and at least a part of the conductor portion forming the outer conductor parallel to the multilayer substrate is electrically connected to each other between the insulating layers. A step of connecting a vertical connection portion and thereby forming at least a portion of a conductor portion perpendicular to the outer conductor of the multilayer substrate; and a step of forming an insulating layer and forming at least a portion of the conductor portion of the outer conductor parallel to the multilayer substrate A part of the foregoing steps, and at least one of the foregoing steps of forming at least a portion of the conductor portion perpendicular to the outer conductor of the multilayer substrate, the conductor portion parallel to the outer conductor of the multilayer substrate is parallel to the conductor portion perpendicular to the multilayer substrate. Conductor part of outer conductor It is characteristic that a step of appropriately repeating a portion of the multilayer substrate formed so far is formed until a predetermined external conductor in the aforementioned multilayer substrate is formed to be supported. For the invention described in item 14 of the scope of patent application, the conductor part of the multilayer substrate parallel to the aforementioned outer conductor is added to the feature of the invention described in item -10- (7) (7) 200401603 of the scope of patent application It belongs to the strip conductor. For example, the invention described in item 15 of the scope of patent application, plus the features of the invention in any one of scope 11 to 14 of the scope of patent application, the shield wire in the aforementioned multi-layer substrate is laminated on the semiconductor crystal. The outer surface of the circle is further characterized by a step of cutting the semiconductor wafer laminated with the shield line in the multilayer shield into semiconductor wafer units. For example, if the invention described in item 16 of the patent application scope is added to the invention feature described in any one of item 11 to 14 of the patent application scope, the shield wire in the aforementioned multi-layer substrate is laminated on the semiconductor wafer. Its exterior is characteristic. If the invention described in item 17 of the scope of patent application is added to the features of the invention described in any one of scopes 11 to 14 of the scope of patent application, the multilayer system including the shielded wire in the multilayer substrate described above is included. It features electronic circuit components mounted on the board. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The structure of the shielded wire 1 in the multilayer substrate according to the first embodiment of the present invention will be described below. Fig. 1 is a schematic structural view showing a shielded wire 1 in a multilayer substrate. The shielded wire 1 in the multilayer substrate is composed of a coil 1a, a lead 1b, and a multilayer substrate 1c. Line 圏 la is a constituent element that functions as an external conductor of the screen line in the formation steps of the plurality of insulating layers and the conductive layer of the multi-layer substrate. The coil -11-200401603 (δ) 1 a belongs to the multilayer substrate having a central axis parallel to the multilayer substrate, and includes a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate. The coil 1 a is most suitable for a unit winding in which the cross-sectional shape is a repeating quadrangular or circular wire pattern and the like is electrically connected in series. The form of the coil 1 a and the unit winding in this detailed description are all forms that are intended to function as external conductors of a shielded wire. It is most suitable that the winding part of the multilayer substrate parallel to the coil 1 a is a part of the conductive layer forming the laminate, and the winding part perpendicular to the multilayer substrate is a protruding electrode, a via hole, or a conductive layer that connects the adjacent conductive layers through the insulating layer. Through holes, etc. By forming the coil 1 a as described above, a known multilayer substrate (printed substrate) manufacturing technique such as a lamination method can be used to simultaneously form the coil 1 a in the multilayer substrate during the manufacturing process of the multilayer substrate. The lead lb may be formed inside the coil 1 a via the coil 1 a and the insulating layer during the manufacturing process of the multilayer substrate. The multilayer substrate 1c is a substrate composed of a laminated insulating layer. Moreover, the actual step of forming the multilayer substrate 1c is to laminate the insulating layer and the conductive layer alternately. Then, a part of the conductive layer belongs to the aforementioned coil 1a, and a part of the other insulating layer belongs to the multilayer substrate 1C. Next, the structure of the shield line 2 in the multilayer substrate according to the second embodiment of the present invention will be described. Fig. 1 (b) is a perspective view showing a schematic configuration of the shield wire 2 in the multilayer substrate. The shielded wire 2 in the multilayer substrate is composed of a coil 2a ', a lead wire 2b, and a multilayer substrate 2c. When viewed from the same direction as the adjacent unit coils, the unit coils of the coil 2a each have a spiral pattern rotating in the opposite direction, and the unit coils adjacent to each other are connected to each other at the front end or the end of the spiral pattern. By constructing the coil 2 a ′ like this -12-200401603 〇), the number of units in the unit coil can be made larger, and a larger shielding effect can be obtained. The lead wires 2b and the multilayer substrate 2c are the same constituent elements as those in the first embodiment. Next, the structure of the shield line 3 in the multilayer substrate according to the third embodiment of the present invention will be described. Fig. 1 (c) is a perspective view showing a schematic configuration of the shield wire 3 in the multilayer substrate. The shielded wire 3 in the multilayer substrate is composed of an outer conductor 3a, a lead 3b, and a multilayer substrate 3c. The outer conductor 3a includes a conductor portion parallel to the multilayer substrate 3c and a conductor portion perpendicular to the multilayer substrate. The conductor portion may be strip-shaped or linear. Figure i (0) shows an example of a braided external conductor formed by a linear conductor portion. The lead 3b and the multilayer substrate 3c are the same constituent elements as the first embodiment. Next, the fourth embodiment of the present invention is described. The structure of the shielded wire 4 in the multilayer substrate will be described. Fig. 1 (d) is a perspective view showing a schematic configuration of the shielded wire 4 in the multilayer substrate. The shielded wire 4 in the multilayer substrate is formed by an external conductor (parallel to the multilayer substrate 4d in parallel). The outer conductor 4a and the vertical outer conductor 4b) perpendicular to the multilayer substrate 4d, the wire 4 and the multilayer substrate 4d. The parallel outer conductor 4a is a strip conductor. With this structure, in the multilayer substrate stacking process, There is no need to carry out fine shape etching on the conductor portion of the parallel multilayer substrate 4c. At the same time, there is no reason that the wires are covered by the surface, which has the advantage of high shielding effect. The vertical outer conductor 4b is most suitable for a linear conductor. The wire 4c and the multilayer substrate 4d belongs to the same constituent elements as the first embodiment. Figs. 1 (e) and (f) are structural examples of other lines. In these examples, only flat Row or orthogonal coil center axis age | -13- (10) (10) 200401603 Direction of the winding part constitutes the coil. This explains the operation of the shielded wires 1 to 4 in the multilayer substrate. The shielded wires 1 to 4 in the multilayer substrate It is also suitable for use as an interposer on which a semiconductor wafer constituting a monolithic IC is mounted. The shielded wires 1 to 4 in the multilayer substrate can form other circuit elements inside or externally, and can be constructed as such The circuit function consisting of other circuit elements and the shielded wires 1 to 4 in the multilayer substrate is added to the semiconductor package itself. The shielded wires 1 to 4 in the multilayer substrate can be adjusted by adjusting the extension direction of the coil or external conductor. The length of the shielded wire is arbitrarily set. The shielded wires 1 to 4 in the multilayer substrate are very suitable for the current flowing into the internal wire to be affected by noise, such as poor signals. At this time, when shielding the electrostatic induction noise, The wire or external conductor is grounded at any point. This achieves electrostatic shielding. When shielding electromagnetic induction noise, the current loop flowing into the wire is used as a coil or external conductor. It can also be used as a coaxial cable. It can achieve electromagnetic shielding. Besides, the wires will not be affected by external noise. The current of the lead wires will not be affected by other wiring and components around it. It belongs to the structure similar to the coaxial cable applied to the printed circuit board, 1C, and signal lines of electronic equipment. That is, by sequentially forming an insulating layer, a hole, and a conductor pattern in parallel with the substrate plane, it is parallel to the substrate plane. By forming a part of the coil and forming an electrical connection by repeating this sequence, a coil-shaped circuit having a circuit surface can be spirally formed in a direction perpendicular to the substrate plane. When making these coils, the circuit is formed in advance with the substrate plane. By forming signal lines in parallel directions, a circuit can be formed in both the direction perpendicular to the plane (11) (11) 200401603 plane of the substrate and the plane direction. In the same structure, a coil is formed on a plane parallel to the plane of the substrate, and a signal line passing therethrough can also be formed by a via hole. However, the signal line is very thin. It is difficult to form a very uniform circuit in a direction perpendicular to the substrate. In fact, it is not even possible to form signal lines only in a direction perpendicular to the plane of the substrate, but it must be formed in a plane parallel to the plane of the substrate. With this method, it is impossible to form a signal line shielded on a plane parallel to the plane of the substrate. On the other hand, if the method of the present invention is used, the coil can be easily obtained only in a desired portion. It can also be a countermeasure against electromagnetic waves inside the substrate. Furthermore, if necessary, applying this method to a certain location where electromagnetic waves may be generated can also be a structure that prevents electromagnetic waves from leaking to the outside of the location. At this time, 'the method of the present invention is like a common coaxial cable and cannot completely cover the periphery of the signal line, but in recent years, electronic and electrical equipment have become the mainstream high-frequency field' It is known that even the method of the present invention is "covering" The structure with gaps is also no problem in the shielding effect. Furthermore, the method of the present invention can set the elongation direction of the coil in any direction on the plane of the substrate, and can also form the coil in the same process in any direction according to the needs. Next, the manufacturing method of the shielded wires 1 to 4 in the multilayer substrate according to the present invention will be described together with advantages compared with conventional techniques. Fig. 1 (a) shows a case where a shielded wire 1 in a multilayer substrate using an organic material as an insulator is used as a shield for a single-layer coil. First, as shown in FIG. 2, a core substrate 1 d having a through hole that is a part of a coil and a conductor 1 b that is a signal line is prepared. The material can use the well-known and commonly used copper laminated board example-15- (12) (12) 200401603 such as glass epoxy resin, bismaleic anhydride imine triazaphenyl board, or use polyphenylene ether with excellent electromotive properties. Resin, polyether ether copper resin, benzene cyclobutene benzene cyclopropylene resin and other substrates. Drilling can be performed using widely used methods such as drills or carbon dioxide gas lasers' YAG lasers. The patterning of the conductor can be performed by a known and conventional method such as a subtractive method and an additive method. Then, on the two sides of the core substrate, as shown in FIG. 8, the material, opening method, and patterning method of the outermost 1 e ° insulation layer can be laminated using the same materials and methods as the core material. The outermost layer is formed and formed for the inner layer material. By forming an insulating layer 'on both sides and then a conductive layer, patterning and electrical connection can be performed. Specific examples for several methods. The case of the so-called build-up method will be described. An insulating layer is formed on a substrate made of the above-mentioned inner layer material. As the insulating layer, a glass epoxy-based resin or a melamine resin-based adhesive film, a liquid or film-shaped thermoplastic or thermosetting resin composition, or a copper foil with resin, Copper foil is integrated with insulating resin layer and so on. The formation of the insulating layer is performed as follows, for example. As shown in FIG. 4 (a), 'the adhesive sheet 5 and the unpatterned copper box 6 are arranged on both sides of the above-mentioned core substrate Id, or the copper fan 7 with resin is shown in FIG. 4 (b), such as As shown in FIG. 5, these are laminated and hardened together by a laminated pressure method to form a solid insulation layer and a conductive layer. Alternatively, as shown in FIG. 6, the substrate 1 d is formed, and the liquid composition is coated by a well-known and conventional method such as screen printing, curtain coating, spray coating, and the like, and UV, electron beam, heating, etc. Wait for it to harden. Alternatively, a method such as rolling, laminating, or the like may be used on the above substrate. (16) (13) (13) 200401603 The film-like composition is bonded and hardened by a predetermined method to obtain the insulating layer 8. A via is then formed. A guide hole 9 is formed at a predetermined position of the substrate obtained by the above method using a drill, a laser, or the like. Fig. 7 (a) shows the case where the adhesive sheet 5 and the copper foil 6 are used as the insulating layer and the conductive layer. Similarly, Fig. 7 (b) shows the use of the copper foil 7 with resin, and Fig. 7 (c) shows the A case where a liquid or film-like thermoplastic or thermosetting resin composition 8 is used is described. When using adhesive film or copper foil with resin and forming a conductive layer together with the insulating layer, 'when using a carbon dioxide gas laser widely used to form blind vias', it can be performed in accordance with the need to remove the conductor at a predetermined position by etching in advance. The so-called mask processing. When an adhesive layer or a copper foil with a resin is used to form a conductive layer together with an insulating layer, for example, as shown in FIG. 8 (a), a conductive paste containing conductive powder such as silver or copper is shown in a via hole. It is buried by other methods, and is hardened by a predetermined method. Or as shown in FIG. 8 (b), after obtaining a plating catalyst in a general through-hole plating, that is, in a via hole, electroless plating is performed, and then electrolytic plating is used to form a plating layer 1 1 The method also achieves an electrical connection. When a liquid or film-like composition is used to form an insulating layer, as shown in FIG. 8 (c), for example, a copper foil 12 is laminated, and a conductive layer is formed on the outside of the insulating layer, and a masking process is performed at a predetermined position. The conductive via 10 or the plating layer 11 is electrically connected to the blind via. In this case, the blind vias can be electrically conductive. And as shown in Figure 8 (d), the substrate on which the insulating layer 'blind via hole is formed is catalyzed, and subjected to electroless plating treatment, and then electrolytic plating treatment is performed in accordance with the need, thereby forming a conductive layer at a time. (14) (14) 200401603 The electrical layer 13 and the samarium via are electrically conductive. At this time, the conduction of the blind vias can also be performed using a conductive paste. In the following methods, the insulating layer and the conductive layer may be electrically connected together. That is, as shown in FIG. 9, a predetermined position on the inner layer circuit 1 d is formed by using a conductive paste or the like to form a sharp conductive tip electrode 14 at the front end, and then the adhesive film 5 and the copper foil 6 are combined (FIG. 9 (a) ), Or thin-film insulator 8 and copper foil 6 (Figure 9 (b)), or copper foil 7 with resin, followed by sharp conductive protrusion electrodes (Figure 9 (c)) 14 will penetrate the insulation layer 'to achieve connection with the conductive layer. Furthermore, when using a through-hole substrate connected by electroplating, using the above-mentioned liquid or film-shaped insulating material, or once more of an insulating layer of a blind via formed by the build-up method, it can be used. Ink for buried holes or plating treatment is used to bury via holes or blind vias to smooth the surface. Alternatively, the following methods can be used for lamination. The insulating layer is explained in the case of a four-layer structure using a glass epoxy-based adhesive film. That is, as shown in Fig. 10, a hole is formed using a laser or the like at a predetermined position of the base material 15 of the copper sheet single-sided glass epoxy substrate. Next, "the copper foil 16 is used as an electrode for electroplating, and 17 holes are filled with electroplating. Immediately after that, a low-melting-point metal bump electrode 18 is produced by electroplating. The copper foil 16 is etched into a predetermined pattern as shown in FIG. 11. Furthermore, when the conductor portion of the multilayer substrate parallel to the external conductor is a strip conductor (in the case of the shielded wire 4 in the multilayer substrate) ', this etching process is not required. Thinly apply the same composition as that used for the insulating layer on the side of the protruding electrode -18- (15) (15) 200401603 1 9 and make it semi-hardened. The outermost layers manufactured from this single-sided substrate are the first and fourth layers. Next, as shown in FIG. 12, the inner layer Id and the outermost layer in FIG. 11 are positioned, and the composition that has been semi-hardened by press-bonding is cut out from the protruding electrode portion to form an interlayer insulating layer, and the protruding electrode is formed. The part is electrically connected to the conductor on the inner layer, passes through a coil having a four-layer structure, and manufactures a multi-layer substrate shielded wire 1 in which signal lines are arranged. By applying this method, it is also easy to implement more layers. When the spiral pattern is to be denser, more layering is required. No matter which method is used, more layers can be used. In this way, it is possible to manufacture the multilayer inner shielded wire of the multilayer substrate using the multilayer coil shielded signal line structure shown in FIG. 1 (b) according to the methods, and the multilayer shielded inner shielded wire with external conductors such as braids. . When manufacturing various substrates by the above-mentioned various lamination methods, it is also easy to manufacture electronic circuit elements including the structure of the shielded wires 1 to 4 in the multilayer substrate of the present invention by applying the above-mentioned method to the position. When ceramic materials are used for insulating materials, basically the same process as organic materials, that is, forming a part of a coil and a signal line in each layer, and manufacturing can be completed by laminating. The conventionally implemented method is to sequentially perform openings of blank sheets, buried holes using conductive paste, and pattern printing, lamination, and firing to form the shield wire of the present invention. In the following, a process of forming a coil having a central axis in a direction parallel to the plane of the substrate or an external conductor and a lead on a semiconductor substrate is shown below. This shows an example of a structure where a transistor is formed and a silicon wafer is formed with tungsten and the like. (16) (16) 200401603 is called the upper electrode wiring layer, and the shield line 1 in the multilayer substrate shown in FIG. 1 is formed. By applying this method, the number of revolutions, 歹 (1 (layer) number, formation direction, etc. can be arbitrarily set. First, as shown in FIG. 13, the bottom layer is formed on the sand wafer 20 where the transistor and the electrode portion are formed. The insulating layer 21. It can be formed by using a vapor phase method such as CVD to form a silicon oxide film, or spin-coating organic materials such as polyimide and phenylcyclobutene that have attracted attention in recent years and then drying it afterwards. Then, as described in Section 14 As shown in the figure, various lasers are used to form holes 22 at desired positions. The holes 22 are at positions where electrical connection is made to the lower electrode portion. Next, as shown in FIG. 15, a conductive pattern 23 is formed. Generally used aluminum sputtering The plating or copper layer is formed by a vapor phase method such as CVD or a wet method such as electroplating. Then exposure, etching and patterning are performed. At this time, a patterned photoresist layer may be formed first and then conductive. In this process, the hole 22 opened in the process shown in FIG. 14 can also be electrically conductive, and the first layer and the second layer will be electrically connected. Moreover, before the exposure process, it is generally combined by Physical honing, or chemical honing and physics The method of honing is used to flatten the surface. Next, as shown in FIG. 16, a second insulating layer 24 is formed. Then, as shown in FIG. 17 ′, holes are formed again, and a conductive pattern is formed to form a second-layer conductive pattern 2 5 At this time, wires can also be formed at the same time. Then, as shown in FIG. 18, the third insulating layer 26 is formed by the aforementioned method, and openings, conductivity, and patterning are applied to form a third conductive pattern 27. Get the conduction of the second and third layers. At this stage, as shown in Figure 1, subsequent formation can be formed on the semiconductor. Applying this operation, you can easily increase or decrease the number of revolutions -20- (17 ) 200401603, increase / decrease in the number of 歹 U (layers), formation of multiple shielded wires with different elongation directions, etc. After forming an insulating layer and openings, while forming a conductive layer, while conducting electrical connections between wires, As shown in FIG. 19, if the hole filling part (guide hole) 28 is filled with a conductive body 29, as shown in FIG. 20, the cross section of the coil can again be referred to as a structure called a laminated guide hole, that is, 塡A structure with a guide hole is formed on the filled guide hole, and the boundary of the coil can be straight .
在矽晶圓20上的多層基板內形成所希望的屏蔽線後 ，將該矽晶圓20與包含屏蔽線的多層基板切割成半導體 晶片單位。 再者，也可在矽晶圓2 0上積層內裝屏蔽線的多層基 板前，將矽晶圓2 0切割成晶片單位。此時，在事先切割 的半導體晶片外面，也可以與上述工程同樣地，積層內裝 屏蔽線的多層基板。After forming a desired shield line in the multilayer substrate on the silicon wafer 20, the silicon wafer 20 and the multilayer substrate including the shield line are cut into semiconductor wafer units. In addition, the silicon wafer 20 may be cut into wafer units before a multilayer substrate with shielded wires is laminated on the silicon wafer 20. At this time, a multilayer substrate with shielded wires can be laminated on the outside of the semiconductor wafer that has been cut in advance in the same manner as the above-mentioned process.
而一般施行的方法，亦即以導電體塡充導孔的方法， 就不能形成疊層導孔構造。此時，製造的線圈乃如第2 1 圖所示’導孔連接部具有階段狀的斷面。即使是此種構造 ，對屏蔽效果在實用上並沒有影響。 如以上，利用本發明方法製造的構造是藉由利用同時 形成的線圈或外部導體覆蓋信號線的構造，與習知者相比 ’小型化有長足的進步’且屏蔽效果提高。 【圖式簡單說明】 第1圖（a)是表示有關本發明第一實施形態的多層基 -21 - (18) 200401603 板內屏蔽線1的槪略構成立體圖，第1圖（b)是表示有關 本發明第二實施形態的多層遮板內屏蔽線2的槪略構成立 體圖，第1圖（c)是表示有關本發明第三實施形態的多層 基板內屏蔽線3的槪略棚成立體圖，第1圖（d)是表示有 關本發明第四實施形態的多層基板內屏蔽線4的槪略構成 立體圖，第1圖（e)及第1圖（f)是表示其他線圈構造例的 圖。 第2圖是多層基板內屏蔽線1〜4製造初期段階的立 體槪念圖。 第3圖是表示多層基板內屏蔽線1〜4製法之一例的 立體槪念圖。 第4圖是表示多層基板內屏蔽線1〜4製法之一例的 立體槪念圖。 第5圖是表示多層基板內屏蔽線1〜4製法之—例的 立體槪念圖。 第6圖是表示多層基板內屏蔽線1〜4製法之一·例的 立體槪念圖。 弟7圖是表不多層基板內屏蔽線1〜4製'法之一·例的 立體槪念圖。 第8圖是表示多層基板內屏蔽線1〜4製'法之―例的 立體槪念圖。 第9圖是表不多層基板內屏蔽線1〜4製'法之一·例的 立體槪念圖。 第1 〇圖是表示多層基板內屏蔽線1〜4製法之一例的 _ - 22 - (19) 200401603 立體槪念圖。 第1 1圖是表示多層基板內屏蔽線1〜4製法之一例的 立體槪念圖。 第1 2圖是表示多層基板內屏蔽線1〜4製法之一例的 立體槪念圖。 第13圖是在半導體晶圓上形成多層基板內屏蔽線1 〜4時的製造初期的斷面圖。 第14圖是說明導孔形成的斷面圖。 φ 第15圖是說明欲形成電路之形成導電圖案的斷面圖 第16圖是說明形成第二絕緣層的斷面圖。 第17圖是說明形成第二導電圖案的斷面圖。 第18圖是形成在半導體晶圓上的多層基板內屏蔽線 的斷面槪念圖。 第1 9圖是導孔的斷面槪念圖。Generally, the method implemented, that is, the method of filling the via hole with a conductive body, cannot form a laminated via structure. At this time, the manufactured coil has a stepped cross-section as shown in Fig. 21 '. Even this structure has no practical effect on the shielding effect. As described above, the structure manufactured by the method of the present invention is a structure in which the signal line is covered by a coil or an external conductor formed at the same time, and the shield effect is improved as compared with the conventional one, as compared with the conventional art. [Brief description of the drawings] Fig. 1 (a) is a perspective view showing a schematic configuration of the multilayer base -21-(18) 200401603 in the first embodiment of the present invention, and Fig. 1 (b) shows A perspective view of a schematic configuration of a shielded wire 2 in a multilayer shield according to a second embodiment of the present invention. FIG. 1 (c) is a perspective view of a schematic shed of a shielded wire 3 in a multilayer substrate according to a third embodiment of the present invention. Fig. 1 (d) is a perspective view showing a schematic configuration of a shield wire 4 in a multilayer substrate according to a fourth embodiment of the present invention, and Figs. 1 (e) and 1 (f) are diagrams showing other coil structure examples. Fig. 2 is a perspective view of the shielded wires 1 to 4 in the multilayer substrate in the early stages of manufacturing. Fig. 3 is a perspective view showing an example of a method for manufacturing shielded wires 1 to 4 in a multilayer substrate. Fig. 4 is a perspective view showing an example of a method for manufacturing shielded wires 1 to 4 in a multilayer substrate. Fig. 5 is a perspective view showing an example of a method for manufacturing shielded wires 1 to 4 in a multilayer substrate. Fig. 6 is a perspective view showing an example and method of manufacturing shielded wires 1 to 4 in a multilayer substrate. Figure 7 is a three-dimensional view of one example of a method for manufacturing shielded wires 1 to 4 in a multilayer substrate. Fig. 8 is a perspective view showing an example of a method for manufacturing shielded wires 1 to 4 in a multilayer substrate. Fig. 9 is a perspective view showing one example of a method for manufacturing shielded wires 1 to 4 in a multilayer substrate. Fig. 10 is an _-22-(19) 200401603 perspective view showing an example of a method for manufacturing shielded wires 1 to 4 in a multilayer substrate. Fig. 11 is a perspective view showing an example of a method for manufacturing shielded wires 1 to 4 in a multilayer substrate. Fig. 12 is a perspective view showing an example of a method for manufacturing shielded wires 1 to 4 in a multilayer substrate. FIG. 13 is a cross-sectional view at the initial stage of manufacturing when the shield lines 1 to 4 in the multilayer substrate are formed on the semiconductor wafer. Fig. 14 is a sectional view illustrating the formation of a guide hole. φ FIG. 15 is a cross-sectional view illustrating formation of a conductive pattern of a circuit to be formed. FIG. 16 is a cross-sectional view illustrating formation of a second insulating layer. Fig. 17 is a cross-sectional view illustrating formation of a second conductive pattern. Fig. 18 is a sectional view of a shield line in a multilayer substrate formed on a semiconductor wafer. Figure 19 is a sectional view of a guide hole.
第20圖是表示形成在半導體晶圓上的多層基板內屏 蔽線之一例的斷面槪念圖。 第21圖是表示形成在半導體晶圓上的多層基板內屏 蔽線之一例的斷面槪念圖。 [圖號說明] 1:多層基板內屏蔽線 1 a:線圈 1 b :導線 -23- (20) (20)200401603 1 c :多層基板 1 d :核心基板 1 e :最外層 5 :黏合膠片 6 :銅箱 7:銅箔 8 :絕緣体 9 :導孔 _ 10:導電糊 1 1 :電鍍層 1 2 :銅箔 13:導電層 ’ 1 4 :導電性突起電極 - 1 5:基材 1 6 :銅箔 1 7 :電鍍 φ 1 8 ·.金屬突起電極 1 9 :組成物 20:矽晶圓 2 1 :絕緣層 2 2 :孔 2 3 :導電性圖案 2 4 :第二絕緣層 25:第二層導電性圖案 -24- (21) (21)200401603 2 6 :第二絕緣層 2 7 :第三導電性圖案 2 8 :孔部分 2 9 :導電體Fig. 20 is a sectional view showing an example of a shield line in a multilayer substrate formed on a semiconductor wafer. Fig. 21 is a sectional view showing an example of a shield line in a multilayer substrate formed on a semiconductor wafer. [Illustration of drawing number] 1: Shielded wire in multilayer substrate 1 a: Coil 1 b: Conductor -23- (20) (20) 200401603 1 c: Multi-layer substrate 1 d: Core substrate 1 e: Outermost layer 5: Adhesive film 6 : Copper box 7: Copper foil 8: Insulator 9: Via_ 10: Conductive paste 1 1: Plating layer 1 2: Copper foil 13: Conductive layer '1 4: Conductive protruding electrode-1 5: Substrate 1 6 : Copper foil 1 7: Plating φ 1 8 ·. Metal bump electrode 1 9: Composition 20: Silicon wafer 2 1: Insulating layer 2 2: Hole 2 3: Conductive pattern 2 4: Second insulating layer 25: No. Two-layer conductive pattern -24- (21) (21) 200401603 2 6: second insulating layer 2 7: third conductive pattern 2 8: hole portion 2 9: conductor