Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/01—Manufacture or treatment
  • H10D12/031—Manufacture or treatment of IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/40—Vertical BJTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/202—FETs having static field-induced regions, e.g. static-induction transistors [SIT] or permeable base transistors [PBT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
  • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
  • H10D62/126—Top-view geometrical layouts of the regions or the junctions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/01—Manufacture or treatment
  • H10D8/051—Manufacture or treatment of Schottky diodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/50—PIN diodes 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/60—Schottky-barrier diodes 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/109—Reduced surface field [RESURF] PN junction structures
  • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures

Definitions

• the present invention relates generally to epitaxially grown guard ring edge
• SiC Silicon carbide
• Avalanche breakdown for SiC devices may occur when the maximum electric field within the device exceeds the critical electric field for SiC, which is believed to be from 2 to 4 MV/cm.
• the maximum electric field of such devices usually occurs
• the depletion region has the smallest width, typically at the surface or
• junction also refers to the interface between a semiconductor and a metal layer.
• the depletion region is the region across the junction where the mobile carrier
• field oxide layer (so called field plates); • formation of a sequence of conductive regions with floating
• guard rings generation of a single wide diffused or implanted ring surrounding the device, with conductivity type opposite to that of the device
• JTE junction termination extension
• junction termination extension structures have been suggested for different types of devices by Bakowskv. et al.. U.S. Patent 5,967,795; Mitlehner. et al.. U.S. Patent 5,712,503; Ueno. et al.. U.S.
• guard rings fabricated by combination of ion
• ion implantation is a costly fabrication step which requires a high temperature post implant annealing, and it may also lead to surface and bulk damage, which may result in a significant increase in leakage current. Therefore,
• diodes and transistors in SiC which implement edge termination structure by guard rings
• BJTs bipolar junction transistors
• PiN diode anode region for example PiN diode anode region, BJT overgrown base region, or SIT overgrown gate region.
• a second aspect of the present invention provides a Schottky barrier diode in SiC having guard rings formed from a doped p-type epitaxial layer, grown on
• lateral SiC semiconductor devices such as LMOSFETs and lateral diodes having guard rings formed from a doped p-type epitaxial layer, grown on top of a lightly doped n-type drift region are provided.
• the present invention is further directed to methods of preparing these
• the enumerated SiC semiconductor devices are representative only, and are not intended to limit the scope of the invention to the disclosed devices.
• the number size, and spacing of the epitaxial guard rings may vary, depending on the application and the desired target blocking
• FIG. 1A is a portion of a schematic cross-section of a PiN diode with guard rings made from the same epitaxial layer as the anode region;
• FIG. 1 B is a portion of a schematic cross-section of a Schottky diode with epitaxial guard rings;
• FIG. 1C is a portion of a schematic cross-section of an advanced fully
• BJT epitaxial bipolar junction transistor
• FIG. 1 D is a portion of a schematic cross-section of an advanced fully
• FIG. 2 A is a portion of a schematic cross section of a lateral MOSFET with epitaxial guard rings (EGR);
• FIG. 2B is a portion of a schematic cross-section of a Lateral PiN diode
• EGR epitaxial guard rings
• FIGs. 3 A - D show cross-sectional views of the respective products of steps
• FIG. 4 shows an aerial view of the PiN diode shown in FIG. 1 A.
• BJTs bipolar junction transistors
• SITs static induction transistors
• implanted guard rings preferable than implanted guard rings, because their fabrication can be combined with etching steps for other parts of the device and because it allows costly
• SiC semiconductor devices comprising SiC layers of differing
• conductivity type i.e., negative (n) and positive (p) types
• n and p positive conductivity type
• pure SiC generates n-type SiC, and introducing electron acceptor atoms into pure
• SiC generates p-type SiC.
• the process of introducing donor or acceptor atoms into SiC, known as doping the SiC is accomplished by ion implantation, or by the introduction of such impurities in situ during growth of the SiC layer. Ion implantation, however, can result in surface and bulk damage. Ion implantation also requires a special treatment after implantation (e.g., a post implant anneal) to
• implant anneal a large percentage of certain implanted impurities (e.g., boron and aluminum which are typically used for p-type doping in SiC) can remain electrically inactive occupying interstitial sites. This phenomenon can result in a reduction in the electron lifetime of the implanted layer, e.g., when the free hole
• rings of the present invention are formed from an epitaxially grown layer, and thus avoid the problems associated with ion implantation.
• epitaxially grown edge termination structures are provided, as are methods for preparing these devices.
• FIG. 1 A shows a portion of a cross sectional view of a portion of a PiN diode with epitaxially grown guard rings according to a first embodiment of the
• the diode 10 comprises a SiC substrate doped with donor atoms (n-
• n-drift layer lightly doped with donor atoms
• n-drift layer comprising a SiC layer doped with acceptor atoms (p-
• the structure shown in FIG. 1A can be made by providing an n-type SiC
• the substrate 12 may be a doped SiC single crystal, such as those which may be obtained commercially
• n-drift layer 13 and p-type layers are preferably formed by known
• the anode 14 and guard rings 17 may be formed
• the anode ohmic contact 15 can then be
• the drift layer is heavily doped with a donor material and the drift layer is lightly or
• Suitable donor materials include arsenic,
• Nitrogen is a preferred donor material according to the invention.
• the above materials are merely exemplary, however, and any suitable donor material for silicon carbide can be used.
• the layer from which the anode and the guard rings are formed is the layer from which the anode and the guard rings are formed.
• doping silicon carbide include aluminum, boron and gallium.
• Aluminum is a preferred acceptor material.
• the above materials are merely exemplary, however, and any acceptor material which can be doped into silicon carbide can be used according to the invention.
• the thickness of this p-type layer can also be varied. Unless otherwise indicated, heavily doped in the context of the invention
• the doping levels of the various layers of the PiN diode according to the invention can be varied to produce a device having desired characteristics for a particular application.
• the PiN diodes according to the present invention can be made without
• guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard bits are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG. 1A, any number of guard rings are shown in FIG.
• guard rings can also be varied according to the invention to achieve the desired edge termination effects.
• FIG. IB shows a portion of a cross section of a typical Schottky barrier rectifier, sometimes referred to as a Schottky diode, with epitaxial guard rings, according to a second embodiment of the present invention.
• shown 20 comprises an n-type SiC substrate 21 having a top and bottom surfaces
• the n-drift layer 23 of the device As with the structure shown in Fig. 1A, the n-drift layer 23 of the device
• Fig. IB is preferably formed by known techniques for epitaxial growth.
• the guard rings 25 may similarly be formed from an epitaxially grown p-layer disposed atop the n-drift layer by masking, patterning and etching through the p-type layer using
• the Schottky contact 24 can then be disposed as shown.
• FIG. 1C shows a portion of the cross section of an advanced fully epitaxial • bipolar junction transistor (BJT) 30 with epitaxial guard rings according to an
• the device 30 comprises an n-type SiC
• n-type SiC base layer 33 formed on the n-drift layer 32, an n-type SiC emitter layer
• drift layer 32 is shown in FIG. 1C, it is not necessary for a BJT
• a drift layer is typically used to improve operating characteristics of the device in certain applications (e.g., in
• the drift layer will have a doping level.
• drift layer thickness can be varied to achieve desirable operating characteristics. Drift layer thickness can be chosen based on the operating voltage and frequency. For high voltage applications, the drift layer preferably may have a thickness of 4 to 10
• the drift layer may preferably be any suitable drift layer.
• the drift layer may preferably be any suitable drift layer.
• the drift layer may preferably be any suitable drift layer.
• a self-aligned process according to the present invention comprises using the ohmic contact material from which the base of a BJT is
• FIG. ID shows a portion of the cross section of an advanced fully epitaxial
• SIT static induction transistor
• the device 40 comprises an n-type SiC substrate layer 41 on top of which a lightly doped n-drift SiC 42 layer is disposed,
• an n-type SiC source layer 43 is formed on the n-drift layer 42, a source contact 44
• a heavily doped overgrown p-type SiC gate 45 disposed over the surface of and contacting the source layer 43 and the
• n-drift layer 42 n-drift layer 42, a gate contact 46 formed on the surface of the overgrown p-type
• Each doped SiC layer of this device may be epitaxially grown on the surface of the underlying layer. and the device may generally be prepared by the same methods disclosed herein and in copending application , Attorney Docket No. 3779-001-27,
• FIG. 2A shows a portion of the cross section of a Lateral MOSFET (LMOSFET) SiC semiconductor device with epitaxial guard rings, according to an embodiment of the present invention.
• the LMOSFET shown 50 comprises an
• ohmic contact 51 formed on the bottom of a p-type or semi-insulating SiC substrate 52, over which a SiC p-type layer 53 is epitaxially grown, n-type source
• n-type drain 55 and n-type drift 56 regions disposed on the epitaxially grown p-type layer 53, a source contact 57 disposed atop the source region 54, a drain
• gate contact 58 disposed atop the drain region 55, a gate oxide layer 59 disposed atop the epitaxially grown p-type SiC layer 53, gate contact 60, and epitaxial guard rings
• LMOSFETs may generally be prepared by well known methods, see, e.g.,
• the guard rings 61 are formed from an epitaxially grown p-type SiC layer.
• FIG. 2B shows a portion of the cross section of a Lateral PiN diode with epitaxial guard rings, according to an embodiment of the present invention.
• Lateral PiN diode shown 70 comprises an ohmic contact 71 formed on the bottom
• n-type cathode SiC region 74 disposed on the n-drift layer 73, a p-type
• SiC anode 75 disposed on the n-drift layer, p-type epitaxial guard rings 76, an anode contact 77 and a cathode contact 78.
• This device may be prepared by well known methods, and, according to the present invention, the guard rings 76 and the anode 75 may be formed from the same epitaxially grown p-type SiC layer. According to the present invention, the number of guard rings employed
• guard rings are spaced closely together
• FIG. 3 A shows a cross-sectional view of the product of the first step in a method of forming a simple PiN diode according to the invention.
• a heavily doped n-type SiC substrate 1 1 1 is shown, having an ohmic contact 1 12
• FIG. 3B shows the product of the second step in the method where a
• SiC layers of the present invention may be formed by any epitaxial growth method known in the art, including chemical vapor deposition (CVD), molecular beam epitaxy and sublimation epitaxy. According to preferred embodiment of the invention, the doped SiC layers according to the invention are formed by doping in
• FIG. 3C shows the results of the selective removal of portions of the heavily doped p-type substrate, which may be accomplished using conventional
• FIG. 3D shows the results of the final step in the method of preparing a simple PiN diode, forming the anode ohmic contact 1 17 disposed on the top surface of the anode 115.
• FIG. 4 shows an example aerial view of the PiN diode shown in FIG. 1 A.
• the visible portion of the PiN diode shown comprises the lightly doped n-drift SiC
• the SiC anode disposed on the n-drift layer 14 the SiC anode disposed on the n-drift layer 14, the ohmic contact disposed on the anode 15, the p-type guard rings 17, and the trenches 18.

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• Insulated Gate Type Field-Effect Transistor (AREA)

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• 2002
  • 2002-02-22 US US10/079,892 patent/US6693308B2/en not_active Expired - Lifetime
• 2003
  • 2003-02-21 EP EP03723635A patent/EP1485942B1/en not_active Expired - Lifetime
  • 2003-02-21 JP JP2003572069A patent/JP2005518672A/ja active Pending
  • 2003-02-21 AU AU2003230555A patent/AU2003230555A1/en not_active Abandoned
  • 2003-02-21 WO PCT/US2003/005156 patent/WO2003073471A2/en not_active Ceased

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