Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F3/217—Class D power amplifiers; Switching amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F3/217—Class D power amplifiers; Switching amplifiers
  • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
  • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
  • H03F3/3022—CMOS common source output SEPP amplifiers
  • H03F3/3023—CMOS common source output SEPP amplifiers with asymmetrical driving of the end stage
  • H03F3/3027—CMOS common source output SEPP amplifiers with asymmetrical driving of the end stage using a common source driving stage, i.e. inverting stage
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/331—Sigma delta modulation being used in an amplifying circuit

Definitions

• the present invention relates to a power amplifier. Background art
• class D amplifier As a power amplifier for audio.
• This class D amplifier performs power amplification by switching, and is configured, for example, as shown in FIG.
• the digital audio signal Pin is supplied to PWM (Pulse Width Modulation) modulation circuits 11 and 12 through the input terminal Tin, and the input signal Pin is converted into a pair of PWM signals PA and PB.
• PWM Pulse Width Modulation
• the pulse widths of the PWM signals PA and PB change in accordance with the level indicated by the input signal Pin (the level of each analog signal sampled as the signal Pin).
• the pulse width of one PWM signal PA is set to a magnitude corresponding to the level indicated by the input signal Pin
• the pulse width of the other PWM signal PB is set to the pulse width of the input signal Pin. It has a size corresponding to the 2's complement of the indicated level.
• the rising point of the PWM signals PA and PB is fixed to the start point of one cycle period (reference cycle) Tc of the PWM signals PA and PB, and the falling point is set to the level indicated by the input signal Pin. It is assumed to change correspondingly.
• Such a PWM signal PA is supplied to the drive circuit 13 to form a pair of drive voltages + PA, _PA having the same level and a level inversion as the signal PA, as shown in FIG. 11A.
• These drive voltages + PA, —PA are a pair of n-channel M ⁇ S—FET (Metal Oxide
• F ET Field Effect Transistor
• Q11 Semiconductor type—Supplied to the gate of Field Effect Transistor (Q11, Q12).
• F ET Ql K Q12
• the drain of FET (Q11) is connected to the power supply terminal TPWR, and its source is connected to the drain of F ET (Q12). Connected and the source of this FET (Q12) is connected to ground.
• a stable DC voltage + VDD is supplied to the power supply terminal TPWR as the power supply voltage.
• the voltage + VDD is, for example, 20V to 50V.
• the source of the FET (Q11) and the drain of the FET (Q12) are connected to one end of the speed force 19 through a single-pass filter 17 having a coil and a capacitor.
• the configuration for the PWM signal PB from the PWM modulation circuit 11 is the same as that for the PWM signal PA. That is, the PWM signal PB is supplied to the drive circuit 14, and as shown in FIG. 11B, a pair of drive voltages + PB and _PB having the same level as that of the signal PB and whose level is inverted are formed.
• the drive voltage + PB and one PB are supplied to the gates of a pair of n-channel MOS FETs (Q13, Q14) constituting the push-pull circuit 16 respectively.
• the push-pull circuits 15 and 16 constitute a BTL (Bridged-Tied Load) circuit.
• the period during which the current i flows changes corresponding to the period during which the original PWM signals PA and PB rise, and when the current i flows through the speaker 19, the current i becomes the low-pass filter 17 and Integrated by 1 8
• the current i flowing through the speaker 19 is an analog current corresponding to the level indicated by the input signal Pin and becomes a power-amplified current, that is, the power-amplified output is supplied to the speaker 19. Will be.
• the circuit in Fig. 10 operates as a power amplifier.
• the FETs (Q11 to Q14) switch the power supply voltage + VDD in accordance with the input digital audio signal Pin. Since power is amplified, high efficiency and high output can be obtained.
• the power amplifier described above switches the power supply voltage + VDD at high speed to form the output voltages VA and VB as shown in Fig. 11 (: and D). Unnecessary radiation is generated by the rising edge and the falling edge. Furthermore, at the time of switching, the power supply voltage + VDD is as high as 20 V to 50 V, so that the radiation becomes considerably large.
• the carrier frequency fc of the signals PA and PB is, for example, 768 kHz as described above, and this is included in the broadcast band of medium-wave broadcasting.
• the class-D power amplifier described above is integrated with the receiver or placed close to the receiver, as in car audio, etc.
• the rising edges and rising edges of the output voltages VA and VB Radiation from falling edges can interfere with broadcast reception.
• the rising and falling edges of the output voltages VA and VB are steep, contain many harmonic components, and the harmonic components are also radiated, which hinders reception by FM receivers and television receivers. May be given.
• An object of the present invention is to provide a power amplifier in which such radiation is reduced. Disclosure of the invention In the present invention, for example,
• a first pulse modulation circuit that converts the input signal into a first pulse modulation signal indicating the level and outputs the first pulse modulation signal
• a second pulse modulation circuit that converts the input signal into a second pulse modulation signal indicating a complement of the level and outputs the second pulse modulation signal
• a first and a second push-pull circuit configured by a pair of switching elements being push-pull connected;
• the first to fourth power supplies for selectively supplying the outputs of the first and second pulse modulation circuits to each of the pair of switching elements of the first and second push-pull circuits as drive signals.
• a load is connected between an output terminal of the first push-pull circuit and an output terminal of the second push-pull circuit;
• the first to fourth selector circuits are set so that the drive signal supplied to each of the switching elements does not change at the break point of each one cycle period of the first and second pulse modulation signals.
• the switching is performed every cycle of the first and second pulse modulation signals.
• FIG. 1 is a system diagram showing one embodiment of the present invention.
• FIG. 2 is a waveform diagram for explaining the circuit of FIG.
• FIG. 3 is a system diagram showing another embodiment of the present invention.
• FIG. 4 is a diagram showing one form of a data table.
• FIG. 5 is a diagram for explaining the relationship between signals and addresses.
• FIG. 6 is a waveform diagram for explaining the circuit of FIG.
• FIG. 7 is a system diagram showing another embodiment of the present invention.
• FIG. 8 is a waveform diagram for explaining the circuit of FIG.
• FIG. 9 is a system diagram showing another embodiment of the present invention.
• FIG. 10 is a system diagram for explaining the present invention.
• FIG. 11 is a waveform diagram for explaining the circuit of FIG.
• FIG. 12 is a waveform diagram for explaining the circuit of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
• FIG. 1 shows an example of a class D power amplifier according to the present invention.
• a digital audio signal Pin is supplied to a ⁇ modulation circuit 111 through an input terminal Tin.
• the ⁇ modulation circuit 1 1 1 constitutes a first PWM modulation circuit 1 1 1 together with a ROM (Read Only Memory) 1 1 2 and a shift register 1 1 3 of a parallel input serial output, and a ROM 1 2 2 Together with the parallel input serial output shift register 123, it constitutes a second PWM modulation circuit 12.
• the digital audio signal Pin is converted by the PWM modulation circuits 11 and 12 into, for example, PWM signals + PA and + PB as shown in FIGS. 2A and 2B.
• the pulse widths of the PWM signals + PA and + PB change in accordance with the level indicated by the input signal Pin, and as shown in FIG.
• the pulse width of the PWM signal + PB is set to a value corresponding to, for example, the two's complement of the level indicated by the input signal P in .
• the rising point of the PWM signal + PA, + PB is fixed to the start point of one cycle period Tc of the PWM signal + PA, + PB, and the falling point is The point changes according to the level indicated by the audio signal Pin.
• the digital audio signal Pin from the input terminal Tin is supplied to the ⁇ modulation circuit
• the audio signal is supplied to the ROM 112 and converted into parallel digital data corresponding to the quantization level, and the parallel digital data is supplied to the shift register 113 and converted into a serial signal, that is, a PWM signal + PA. Is converted.
• the digital audio signal output from the ⁇ modulator 11 1 is supplied to the ROM 122 and the parallel digital data corresponding to the two's complement of the level is supplied to the ROM 122.
• the parallel digital data is supplied to the shift register 123 and is converted into a serial signal, that is,
• timing signal forming circuit 121 various timing signals are formed in the timing signal forming circuit 121, and these timing signals are supplied to the circuits 111 to 113, 122, and 123, respectively.
• the PWM signals + PA and + PB are supplied to the drive circuits 13 and 14, and drive voltages P1 to P4 are formed. That is, the PWM signal + PA is supplied to the selector circuits 13 1 and 14 2, and is also supplied to the inverter 13 5, and as shown in FIG.
• the PWM signal—PA is supplied to the selector circuits 13 2 and 14 1.
• the PWM signal + PB is supplied to the selector circuits 141, 132 and the inverter circuit 145, as shown in FIG. 2B. Then, this PWM signal—PB is supplied to the selector circuits 144 2 and 131.
• FIGS. 2A and 2B are the same as FIGS. 11A and 1B.
• a signal Pc whose level is inverted every cycle period Tc is extracted from the timing signal forming circuit 121, and this signal Pc is used as a selector circuit 131, 1332, The switching control signal is supplied to 14 1 and 14 2.
• the signals + PA, —PA are extracted from the selector circuits 13 1 and 13 2 as the drive voltages P 1 and P 2.
• the signals —PB and + PB are extracted as drive voltages P1 and P2.
• the drive voltages P 1, P 2, P 3, and P 4 are shaped by the flip-flop circuits 13 3, 13 4, 14 3, and 14 4, the drive voltages P 1 and P 2 are These are supplied to the gates of a pair of switching elements, for example, n-channel MOS FETs (Ql K Q12).
• a pair of switching elements for example, n-channel MOS FETs (Ql K Q12).
• the FET (Q1K Q12) constitutes a push-pull circuit 15
• the drain of the FET (Ql 1) is connected to the power supply terminal TPWR, and its source is connected to the drain of the FET (Q12).
• the source of this FET (Q12) is connected to ground.
• a stable DC voltage + VDD for example, a DC voltage of 20 V to 50 V is supplied to the power supply terminal TPWR as a power supply voltage.
• the source of the FET (Q11) and the drain of the FET (Q12) are connected to one end of the speaker 19 through a single-pass filter 17 composed of, for example, a coil and a capacitor.
• the drive voltages P3 and P4 from the drive circuit 14 are configured in the same manner as the drive voltages Pl and P2. That is, the drive voltages P3 and P4 are supplied to the gates of a pair of n-channel MQS-FETs (Q13, Q14) constituting the push-pull circuit 16, respectively.
• the source of F ET (Q13) and the drain of F ET (Q14) are connected to the other end of the speed controller 19 through a single-pass filter 18 having a coil and a capacitor.
• the period during which the current i flows changes according to the period during which the original PWM signals + PA and + PB rise, and when the current i flows through the speaker 19, the current i
• the current i flowing through the loudspeaker 19 is an analog current corresponding to the level indicated by the digital audio signal Pin and is a power-amplified current. Therefore, the circuit shown in FIG. 1 operates as a class D power amplifier, and the power-amplified output is supplied to the speaker 19.
• the power amplifier shown in FIG. 1 can perform power amplification by switching, but as shown in FIG. ⁇ ⁇ 1 ⁇ 1 signal +?, + PB rises and falls once per cycle Tc, but output voltage VA, VB rises and falls one cycle Tc Output voltage only once.
• the number of rising edges and falling edges of VA and VB is one of the number of rising edges and falling edges of output voltages VA and VB (see Fig. 11C and D) in the power amplifier shown in Fig. 10. / 2. Therefore, radiation caused by changes in output voltages VA and VB can be reduced.
• the frequency of the output voltages VA and VB is 1/2 of the frequency of the output voltages VA and VB in the power amplifier shown in Fig. 10, so that the power amplifier is integrated with the receiver, such as a car audio. , Or placed close to the receiver, can reduce the interference that radiation has on the reception of the broadcast. Then, since the interference of the radiation with the reception of the broadcast can be reduced in this manner, the number of members for shielding the receiver against the radiation can be reduced, and the cost can be reduced. Also, because the receiver can be closer to the power amplifier, space can be saved.
• both the drives are instantaneous.
• a period occurs when the voltages Pl and P2 become "L”. During this period, the FETs (Q11 and Q12) are turned on at the same time, and a through current flows through the FETs (Qll and Q12).
• the power amplifier shown in Fig. 1 is different from the power amplifier shown in Fig. 10 in that the frequency of the drive voltages P1 to P4 is 1 Z2, so that FET (Ql K Q12) and FET ( Q13 and Q14) are turned on at the same time, and the number of times through current flows through the FET (Q1K Q12) and FET (Q13, Q14) can be reduced by half.
• R ⁇ M 112 since the digital audio signal output from the ⁇ modulation circuit 111 has one sample of 6 bits, as shown in FIG. 4, R ⁇ M 112 has one more bit of address. 7 bits are A6 to A0, and the data size of each address is 6 bits D63 to D0 corresponding to 6 bits per sample.
• the digital audio signal output from the ⁇ modulation circuit 1 1 1 has 6 bits per sample, the digital audio signal is 0 to ⁇ 31 as shown in the left column of FIG. ( And since this 63 value is expressed in two's complement, if this is shown in binary, it will be as shown in the middle column of Fig. 5, and this binary is natural When converted to decimal, assuming that it is a binary number, the result is as shown in the right column of FIG.
• addresses 0 to 63 of ROM 122 are considered to be equal to addresses 63 to 0 of ROM 112, and addresses 64 to 127 of ROM 122 are 127 to 64 of ROM 112.
• the data is the same as the address. Note that the data at addresses 0 to 63 of R ⁇ M 112 and 122 can be the data at addresses 0 to 63 of ROMs 112 and 122 in FIG.
• the lower 6 bits A5 to A0 of the 7-bit addresses A6 to AO of ROMs 112 and 122 are output from the ⁇ modulation circuit 111.
• a digital audio signal is supplied, and a signal Pc inverted every one sample period Tc is supplied to the most significant bit A6 from the timing signal forming circuit 121.
• the rising point changes according to the complement of the level indicated by the digital audio signal, and at the end of the period Tc Becomes the rising PWM signal P 3.
• the PWM signal P1 is supplied to the gate of the FET (Q11) through the flip-flop circuit 133, and is also supplied to the inverter 135 to invert the level as shown in FIG.
• the signal P 2 The signal P2 is supplied to the gate of FET (Q12) through the flip-flop circuit 134.
• the PWM signal P3 is supplied to the gate of the FET (Q13) through the flip-flop circuit 143, and is also supplied to the inverter 145 to be a signal P4 whose level is inverted as shown in FIG. 6E.
• the signal P4 is supplied to the gate of FET (Q14) through the flip-flop circuit 144.
• the speaker 19 is supplied with the current i shown in FIG. 6H. As a result, the speaker 19 is supplied with a power-amplified output.
• the output stage of the power amplifier is a BTL circuit, but may be a single circuit.
• FIG. 7 shows one form of such a power amplifier.
• the PWM signals + PA and + PB are extracted from the PWM modulation circuits 11 and 12 as shown in FIG. 8A, and the PWM signal + PA is The PWM signal + PB is supplied to the inverter 145, and the PWM signal + PB is supplied to the drive circuit 13 as shown in Fig. 8B. Supplied.
• drive voltages Pl and P2 are extracted from the drive circuit 13. These drive voltages Pl and P2 are supplied to the push-pull circuit 15.
• the drive voltage P 1 is equal to the PWM signal +
• the drive voltage P2 is a signal obtained by alternately taking out the PA and the PWM signal—PB every one cycle period Tc.
• the drive voltage P2 is a signal obtained by inverting the level of the drive voltage P1.
• the push-pull circuit 15 uses positive and negative power supplies, the drain of F ET (Q11) is connected to the positive power supply terminal TPWR +, and the F ET (Q12) Is connected to the negative power supply terminal TPWR-.
• a pair of positive and negative DC voltages + VDD and -VDD are supplied to the power supply terminals TPWR + and TPWR- as power supply voltages. Then, the output end of the push-pull circuit 15 is connected to one end of the speaker 19 through the mouth-pass filter 17 and the other end is grounded.
• the output voltage VA of the push-pull circuit 15 has a waveform as shown in FIG. 8D corresponding to the drive voltage P and P2, and as shown in FIG. A current i having a polarity and magnitude corresponding to the input signal Pin flows, and power amplification is performed.
• the number of rising edges and falling edges of the drive voltages Pl and P2 is 12 of the PWM signals + PA and + PB, and therefore flows to F ET (Q1K Q12).
• the through current is reduced by half.
• the frequency of the output voltage VA is 1 Z 2, radiation caused by the output voltage VA is also reduced.
• the power amplifier shown in FIG. 9 is similar to the power amplifier shown in FIG. 7, except that the output stage is a single circuit and the power supply voltage of the push-pull circuit 15 is only DC voltage + VDD. Therefore, in this case, for example, a DC cut capacitor 21 is connected between the output terminal of the push-pull circuit 15 and the low-pass filter 17.
• the input signal Pin is a digital audio signal, but may be an analog audio signal.
• PWM Signal + PA, + PB, —PA, one PB is PNM (Pulse Number
• the PWM modulation circuits 11 and 12 can be configured by an up counter, a down counter, and a comparison circuit.
• the power amplifier is an amplifier for audio.
• the amplifier can be used as an amplifier for driving a power device such as a motor. If an arbitrary load is connected in place of the speaker 19, the operating voltage can be supplied to the load, and the magnitude of the voltage supplied to the load can be changed by changing the input signal Pin.
• the number of rising edges and falling edges of the output voltage is controlled by the number of rising edges and the number of rising edges of the PWM signal that forms the output voltage. And the number of falling edges is 1 Z 2, so that radiation caused by changes in the output voltage can be reduced.
• the power amplifier is integrated with the receiver or is arranged close to the receiver as in the case of Richiichi Audio, it is possible to reduce the interference of the radiation with the reception of the broadcast. Also, from this, it is possible to reduce the number of members for shielding the receiver against radiation, and The strike can be reduced. Furthermore, since the receiver can be brought closer to the power amplifier, space can be saved.
• the number of rising edges and falling edges of the output voltage is halved, the number of times through current flows through the push-pull circuit for forming the output voltage can be halved, and the loss of the amplifier can be reduced. This can reduce heat generation from the device. Further, since the number of times of switching of the output switching element is halved, deterioration of audio characteristics caused by switching noise can be suppressed.

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• Amplifiers (AREA)
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• 2002
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