WO2003015103A1 - Halbleiterspeciher mit verbesserter leseanordnung sowie zugehörige betriebsart - Google Patents
Halbleiterspeciher mit verbesserter leseanordnung sowie zugehörige betriebsart Download PDFInfo
- Publication number
- WO2003015103A1 WO2003015103A1 PCT/DE2002/002715 DE0202715W WO03015103A1 WO 2003015103 A1 WO2003015103 A1 WO 2003015103A1 DE 0202715 W DE0202715 W DE 0202715W WO 03015103 A1 WO03015103 A1 WO 03015103A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- group
- memory transistors
- memory cell
- transistor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Definitions
- the present invention relates to a control circuit and a differential reading concept for non-volatile single-transistor floating gate memories.
- the information is stored by changing the amount of charge on the floating gate of the memory transistor with one or more high voltages, so that the memory transistor conducts or blocks current under certain conditions.
- the control gates of all memory transistors that are not to be read are kept at a low potential (for example 0 volts), while the control gate of the cell to be read is brought to a higher read potential (for example 1.8 volts) becomes.
- the problem here is that memory transistors with a positive potential on the floating gate on the same signal line as the memory transistor to be evaluated can also contribute to a read current with a low control gate voltage and thus falsify the read result for the memory cell to be read.
- the problem has been solved by setting the floating gate potential for cells which are said to have a conductive information state so low that no current flows through them in the unselected state.
- the disadvantage of this is that the high voltage is applied in pulses and after each pulse it must be measured whether the cell has already reached the correct floating gate potential.
- a recovery mechanism must be provided if the floating gate potential is inadvertently reached.
- the low floating gate potential in the cells reduces the reading current and thus the reading speed and narrows the reading window.
- the object of the present invention is to provide a floating gate memory in which these problems are avoided.
- the problems described at the outset are avoided by inserting a selection transistor for a group of memory cells, preferably 16 to 32 memory cells, into the feed lines to the memory cells. Since the memory cells in a memory are usually arranged in a matrix-like grid and are subdivided into rows and columns, to simplify the description it is assumed that the group of memory cells forms a row group in a preferred exemplary embodiment.
- the arrangement according to the invention can, however, be provided accordingly if a column group is to be addressed in this way or if the names of rows and columns are interchanged.
- the selection transistor is opened to a row group while the control gates of all rows are at a low potential, and the current for each column to be read which leads through this row group is measured and stored.
- the control gate or the control gates of the line to be read are brought to the higher reading potential and the resulting current is compared with the previous one.
- a leakage current through the unselected cells does not interfere, since only the difference between the current with and without selected
- FIGS. 1 and 2 illustrate the two steps of the reading process using a section of the memory cell arrangement.
- FIG. 1 shows a section of a memory cell array in which the memory transistors 1 can be selected together in groups with a selection transistor 2.
- FIG. 1 shows two such groups of 16 to 32 memory transistors each, each of which is connected to a selection transistor 2.
- the selection transistor 2 shown at the top in FIG. 1 was opened by applying a potential of typically 1.8 volts to the gate connection 3, so that the associated memory transistors can be read out. Since all of these memories are still blocked with a gate potential of 0 volts, only the output current II initially flows.
- FIG. 2 shows the next step of the reading process, in which the gate terminal 5 of a selected memory transistor 4 is also set to typically 1.8 volts. The memory content of this transistor can therefore be read out, so that an output current 12 now flows.
Landscapes
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02754426A EP1412949A1 (de) | 2001-07-30 | 2002-07-24 | Halbleiterspeicher mit verbesserter leseanordnung sowie zugehörige betriebsart |
JP2003519944A JP2004538597A (ja) | 2001-07-30 | 2002-07-24 | 改善された読み出しデバイスを有する半導体メモリおよびこれと関連する動作モード |
US10/768,988 US6940755B2 (en) | 2001-07-30 | 2004-01-30 | Semiconductor with an improved read device and operational mode associated therewith |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10137120.9 | 2001-07-30 | ||
DE10137120A DE10137120B4 (de) | 2001-07-30 | 2001-07-30 | Betriebsart einer Ansteuerschaltung einer Speicherzellenanordnung |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/768,988 Continuation US6940755B2 (en) | 2001-07-30 | 2004-01-30 | Semiconductor with an improved read device and operational mode associated therewith |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003015103A1 true WO2003015103A1 (de) | 2003-02-20 |
Family
ID=7693612
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2002/002715 WO2003015103A1 (de) | 2001-07-30 | 2002-07-24 | Halbleiterspeciher mit verbesserter leseanordnung sowie zugehörige betriebsart |
Country Status (6)
Country | Link |
---|---|
US (1) | US6940755B2 (de) |
EP (1) | EP1412949A1 (de) |
JP (2) | JP2004538597A (de) |
CN (1) | CN1537311A (de) |
DE (1) | DE10137120B4 (de) |
WO (1) | WO2003015103A1 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8982625B2 (en) * | 2012-08-31 | 2015-03-17 | Micron Technology, Inc. | Memory program disturb reduction |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6044033A (en) * | 1997-12-30 | 2000-03-28 | Samsung Electronics Co., Ltd. | NOR-type nonvolatile semiconductor memory device and a method for reading therefrom |
US6052307A (en) * | 1998-08-11 | 2000-04-18 | Texas Instruments Incorporated | Leakage tolerant sense amplifier |
US6128227A (en) * | 1998-03-28 | 2000-10-03 | Hyundai Electronics Industries Co., Ltd. | Sense amplifier circuit in a flash memory device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5182725A (en) * | 1987-11-20 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Nonvolatile semiconductor memory device with reduced variation in source potential of floating gate type memory transistor and operating method therefor |
JP3204119B2 (ja) * | 1996-09-30 | 2001-09-04 | 日本電気株式会社 | 不揮発性半導体メモリおよびそのデータ書込方法 |
US6081453A (en) * | 1997-04-15 | 2000-06-27 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
JPH11330426A (ja) * | 1998-05-12 | 1999-11-30 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置およびその製造方法 |
EP1047077A1 (de) | 1999-04-21 | 2000-10-25 | STMicroelectronics S.r.l. | Nichtflüchtige Speicheranordnung mit doppelter hierarchischer Dekodierung |
US6501684B1 (en) * | 1999-09-24 | 2002-12-31 | Azalea Microelectronics Corporation | Integrated circuit having an EEPROM and flash EPROM |
US6563730B1 (en) * | 2002-04-09 | 2003-05-13 | National Semiconductor Corporation | Low power static RAM architecture |
-
2001
- 2001-07-30 DE DE10137120A patent/DE10137120B4/de not_active Expired - Fee Related
-
2002
- 2002-07-24 JP JP2003519944A patent/JP2004538597A/ja active Pending
- 2002-07-24 CN CNA028150937A patent/CN1537311A/zh active Pending
- 2002-07-24 WO PCT/DE2002/002715 patent/WO2003015103A1/de not_active Application Discontinuation
- 2002-07-24 EP EP02754426A patent/EP1412949A1/de not_active Ceased
-
2004
- 2004-01-30 US US10/768,988 patent/US6940755B2/en not_active Expired - Lifetime
-
2006
- 2006-10-02 JP JP2006271292A patent/JP2006351201A/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6044033A (en) * | 1997-12-30 | 2000-03-28 | Samsung Electronics Co., Ltd. | NOR-type nonvolatile semiconductor memory device and a method for reading therefrom |
US6128227A (en) * | 1998-03-28 | 2000-10-03 | Hyundai Electronics Industries Co., Ltd. | Sense amplifier circuit in a flash memory device |
US6052307A (en) * | 1998-08-11 | 2000-04-18 | Texas Instruments Incorporated | Leakage tolerant sense amplifier |
Also Published As
Publication number | Publication date |
---|---|
JP2004538597A (ja) | 2004-12-24 |
US6940755B2 (en) | 2005-09-06 |
US20040218417A1 (en) | 2004-11-04 |
JP2006351201A (ja) | 2006-12-28 |
DE10137120A1 (de) | 2003-02-20 |
CN1537311A (zh) | 2004-10-13 |
EP1412949A1 (de) | 2004-04-28 |
DE10137120B4 (de) | 2009-02-19 |
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