WO2002099872A1 - Dispositif semi-conducteur a circuit integre et procede de fabrication associe - Google Patents

Dispositif semi-conducteur a circuit integre et procede de fabrication associe Download PDF

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Publication number
WO2002099872A1
WO2002099872A1 PCT/JP2002/003944 JP0203944W WO02099872A1 WO 2002099872 A1 WO2002099872 A1 WO 2002099872A1 JP 0203944 W JP0203944 W JP 0203944W WO 02099872 A1 WO02099872 A1 WO 02099872A1
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WIPO (PCT)
Prior art keywords
misfet
active region
element isolation
circuit device
integrated circuit
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PCT/JP2002/003944
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English (en)
Japanese (ja)
Inventor
Kousuke Ishibashi
Yasuo Sonobe
Yasushi Tainaka
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Renesas Technology Corp.
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Publication of WO2002099872A1 publication Critical patent/WO2002099872A1/fr

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Classifications

    • H01L29/7846—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H01L21/823412—
    • H01L21/823481—

Definitions

  • the present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having a metal insulator semiconductor yield effect transistor (MISFET).
  • MISFET metal insulator semiconductor yield effect transistor
  • One of the element isolation technologies for electrically isolating adjacent semiconductor elements from each other is to provide a groove with a depth of, for example, 0.3 to 0.4 jtm on the substrate that is to be the element isolation region, and to form an insulating film There is a groove isolation formed by embedding the trench.
  • the surface of the substrate is etched to form a groove having a depth of about 0.3 to 0.4 m in the element isolation region.
  • a silicon oxide film with a thickness of about 0.6 m is deposited on the substrate including the inside of the groove by chemical vapor deposition (CVD).
  • This silicon oxide film is deposited, for example, by a plasma CVD method using oxygen (or ozone) and tetraethoxysilane (TEOS) as a source gas.
  • heat treatment at about 1000 ° C is performed to densify the film.
  • the inside of the groove is buried with a silicon oxide film by polishing and flattening the surface of the silicon oxide by CMP (Chemical Mechanical Polishing) to form a groove isolation on the main surface of the substrate.
  • CMP Chemical Mechanical Polishing
  • the present inventor has studied and found that the minimum processing size of 0.14 // m
  • the threshold voltage or the drive current varies, for example, the threshold voltage of the n-channel MISF ET fluctuates by about 40 to 70 mV. Became evident.
  • An object of the present invention is to provide a technique capable of obtaining a MISFET having desired characteristics by adjusting an isolation width of an element isolation portion.
  • the present invention controls the threshold voltage or drive current of the MISFET by adjusting at least one isolation width in the gate length direction of the element isolation portion surrounding the active region where the MISFET is formed. .
  • the present invention provides a desired threshold voltage or drive current by adjusting at least one isolation width in the gate length direction of an element isolation portion surrounding an active region in which a MISFET is formed.
  • the MISFET is formed.
  • a semiconductor integrated circuit device that controls a threshold voltage or a drive current of a MISFET by adjusting at least one distance from a gate electrode of a MISFET to an element isolation portion in a gate length direction. It is.
  • the semiconductor integrated circuit device of the present invention surrounds the active region where the MISF ET is formed. By adjusting at least one isolation width in the gate length direction of the element isolation portion and at least one distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction, the threshold voltage of the MISFET is adjusted. It controls the drive current.
  • the method for manufacturing a semiconductor integrated circuit device according to the present invention is characterized in that a desired threshold voltage or drive current is adjusted by adjusting at least one distance from a gate electrode of an MIS FET to an element isolation portion in a gate length direction. To form a MIS FET.
  • the method for manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of:
  • the MISFET By adjusting at least one distance from the gate electrode of the ISFET to the element isolation portion in the gate length direction, the MISFET having a desired threshold voltage or drive current is formed.
  • the semiconductor integrated circuit device of the present invention has a first MISF ET and a second MISF ET having different threshold voltages on a main surface of a substrate, and has a relatively wide separation width.
  • a first MISFET is formed in a first active region surrounded by a portion
  • a second MISFET is formed in a second active region surrounded by an element isolation portion having a relatively small isolation width at least in one direction in a gate length direction. Is formed.
  • the semiconductor integrated circuit device of the present invention has a first MISF ET and a second MISF ET having different threshold voltages on a main surface of a substrate, and a first MISFET is formed.
  • the distance from the gate electrode in the first active region to the element isolation part in the gate length direction is relatively large, and from the gate electrode in the second active area where the second MIS FET is formed to the element isolation part in the gate length direction At least one of the distances is relatively small.
  • the semiconductor integrated circuit device of the present invention has a first MISF ET and a second MISF ET having different threshold voltages on a main surface of a substrate, and has a relatively wide separation width.
  • a first MISFET is formed in a first active region surrounded by a portion
  • a second MISFET is formed in a second active region surrounded by an element isolation portion having a relatively narrow isolation width at least in one direction in the gate length direction.
  • the distance from the gate electrode in the first active region to the gate isolation in the gate length direction is relatively large, and the distance from the gate electrode in the second active region to the gate isolation in the gate length direction is relatively large. At least one of which is relatively small It is.
  • FIG. 1 is a graph showing a threshold voltage of a first group of n-channel MISFETs and a threshold voltage of a second group of n-channel MISFETs for explaining an embodiment of the present invention.
  • FIG. 2 is a graph showing the relationship between the intrinsic stress of the groove isolation and the separation width of the groove isolation for explaining an embodiment of the present invention.
  • FIG. 3A is a graph showing the relationship between the stress applied to the channel region of the MISFET and the number of gate electrodes arranged in the active region for explaining one embodiment of the present invention
  • FIG. FIG. 2 is a cross-sectional view of a main part showing an arrangement of a gate electrode.
  • FIG. 4 is a plan view of a main part showing a first arrangement example of the MISFET according to an embodiment of the present invention.
  • FIG. 5 is a plan view of a principal part showing a second arrangement example of the MISFET according to an embodiment of the present invention.
  • FIG. 6 is a plan view of a principal part showing a third arrangement example of the MISFET according to an embodiment of the present invention.
  • FIG. 7 is a plan view of a principal part showing a fourth arrangement example of the MISFET according to an embodiment of the present invention.
  • FIG. 8 is a plan view of a principal part showing a fifth arrangement example of the MISFET according to an embodiment of the present invention.
  • FIG. 9 is a plan view of a principal part showing a sixth arrangement example of the MISFET according to an embodiment of the present invention.
  • FIG. 10 is a plan view of a principal part showing a seventh arrangement example of MISFET according to an embodiment of the present invention.
  • FIG. 11 is a diagram showing a configuration of a MISF arranged on a semiconductor chip according to an embodiment of the present invention.
  • FIG. 4 is a schematic plan view showing an arrangement area of the ET.
  • FIG. 12 is a schematic plan view showing an example of an arrangement region of MISFETs arranged in a gate array section on a semiconductor chip according to an embodiment of the present invention.
  • FIG. 13 is a schematic plan view of an inverter circuit according to an embodiment of the present invention.
  • FIG. 14 is a schematic plan view of an inverter circuit according to an embodiment of the present invention.
  • FIG. 15 is a schematic plan view of an inverter circuit according to an embodiment of the present invention.
  • FIG. 16 is a schematic plan view of an inverter circuit according to an embodiment of the present invention.
  • FIG. 17 is a schematic plan view of an inverter circuit according to an embodiment of the present invention.
  • FIG. 18 is a schematic plan view of an inverter circuit according to an embodiment of the present invention.
  • FIG. 12 is a schematic plan view showing an example of an arrangement region of MISFETs arranged in a gate array section on a semiconductor chip according to an embodiment of the present invention.
  • FIG. 13 is a schematic plan
  • FIG. 19 is a schematic plan view of an inverter circuit according to an embodiment of the present invention.
  • FIG. 20 is a schematic plan view of an inverter circuit according to an embodiment of the present invention.
  • FIG. 21 is a schematic plan view of a two-input NAND circuit according to an embodiment of the present invention.
  • FIG. 22 is a schematic plan view of a two-input NAND circuit according to an embodiment of the present invention.
  • FIG. 23 is a schematic plan view of a two-input NAND circuit according to an embodiment of the present invention.
  • FIG. 24 is a schematic plan view of a two-input NAND circuit according to an embodiment of the present invention.
  • FIG. 25 is a schematic plan view of a two-input NAND circuit according to an embodiment of the present invention.
  • FIG. 26 is a schematic plan view of a two-input NAND circuit according to an embodiment of the present invention.
  • FIG. 27 is a schematic plan view of a two-input NAND circuit according to an embodiment of the present invention.
  • FIG. 28 is a schematic plan view of a two-input NAND circuit according to an embodiment of the present invention.
  • FIG. 29 is a schematic plan view of a two-input NOR circuit according to one embodiment of the present invention.
  • FIG. 30 is a schematic plan view of a two-input NOR circuit according to one embodiment of the present invention.
  • 1 is a schematic plan view of a two-input NOR circuit according to an embodiment of the present invention.
  • FIG. 32 is a schematic plan view of a two-input NOR circuit according to one embodiment of the present invention.
  • FIG. 33 is a schematic plan view of a two-input NOR circuit according to one embodiment of the present invention.
  • FIG. 35 is a schematic plan view of a two-input NOR circuit according to one embodiment of the present invention.
  • FIG. 35 is a schematic plan view of a two-input NOR circuit according to one embodiment of the present invention.
  • FIG. 37 is a schematic plan view of a two-input NOR circuit according to an embodiment.
  • FIG. 37 is a cross-sectional view of a main part of a semiconductor substrate illustrating a method for manufacturing a CMOS device according to an embodiment of the present invention.
  • FIG. 38 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a CMOS device according to an embodiment of the present invention.
  • FIG. 39 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a CMOS device according to an embodiment of the present invention.
  • FIG. 40 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the CMOS device according to one embodiment of the present invention.
  • FIG. 41 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a CMOS device according to an embodiment of the present invention.
  • FIG. 42 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a CMOS device according to an embodiment of the present invention.
  • FIG. 43 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a CMOS device according to an embodiment of the present invention.
  • FIG. 44 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a CMOS device according to an embodiment of the present invention.
  • FIG. 45 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a CMOS device according to an embodiment of the present invention.
  • FIG. 46 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a CMOS device according to an embodiment of the present invention.
  • FIG. 47 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a CMOS device according to an embodiment of the present invention.
  • FIG. 1 is a graph showing a threshold voltage of a first group of n-channel MISF ETs and a threshold voltage of a second group of n-channel MISF ETs for explaining an embodiment of the present invention.
  • the first group of n-channel MISFETs is formed in an active region surrounded by a trench isolation having a relatively wide isolation width
  • the second group of n-channel MISFETs is formed of a trench isolation having a relatively narrow isolation width. It is formed in the active area surrounded by the lance.
  • the threshold voltage of the first group n-channel MISFET is about 0.07 to 0.09 V, while the threshold voltage of the second group n-channel MISFET is about 0.11 to 0.14 V , which is about 0.04 to 0.05 V higher than the threshold voltage of the n-channel MIS FET of the first group.
  • FIG. 2 is a graph illustrating the relationship between the intrinsic stress of the groove isolation and the separation width of the groove isolation for explaining an embodiment of the present invention.
  • the intrinsic stress in the groove isolation with a separation width wider than about 2 m is almost constant, and is about 123 OMPa. However, for trench isolation with a separation width of less than about 2 ⁇ m, the intrinsic stress increases significantly as the separation width becomes narrower, and the intrinsic stress at a separation width of about 0.25 ⁇ m is about 200 OMPa. .
  • FIG. 3 (a) is a graph illustrating the relationship between the stress applied to the channel region of the MISFET and the number of gate electrodes arranged in the active region for explaining one embodiment of the present invention.
  • FIG. 2B is a cross-sectional view of a main part of the substrate showing the arrangement of the gate electrodes.
  • A indicates an active region
  • STI indicates a trench isolation
  • G indicates a MISFET gate electrode.
  • Groove isolation are separation width L 1 of the STI surrounding the active region A, regardless of the present speed of the gate Bok electrode, both of which are approximately 0.25 m.
  • the distance 2 between the center of the gate electrode of the MIS FET located closest to the trench isolation ST I and the end of the trench isolation ST I is about 0.3 / m, and the adjacent MIS FET is They are arranged at approximately 0 intervals (L 3 ).
  • Fig. 3 (a) shows the stress measured in the channel region below the center of the MISFET gate electrode, and one trench isolation from the center of the active region surrounded by the dotted line in Fig. 3 (b). It shows the stress in the area up to the end of the Shillon STI.
  • the stress in the channel region of the MISFET located approximately 0.3 m from the end of the trench isolation STI is , Increasing to nearly 80 OMPa.
  • the channel of the Ml S FET located approximately 0.3 m from the end of the trench isolation STI
  • the stress in the region is about 160 OMPa, but the stress in the channel region of the MISF ET, located about 0.8 m from the end of the trench isolation STI, decreases to about 350 MPa.
  • the stress in the channel region of MISF ET located approximately 0.3 ⁇ m from the end of the groove isolation STI, is approximately 600MPa, and approximately 0.8m from the end of the groove isolation STI.
  • the stress in the channel region of the MISF ET is about 300 MPa, but the stress in the channel region of the MISFET located in the active region more than about 1.3 jim from the end of the trench isolation STI is: It is reduced to about 200 MPa or less. In other words, it is considered that as the distance from the end of the trench isolation STI increases, the stress applied to the channel region of the active region A decreases, and thus the amount of change in the threshold voltage of the MISFET decreases.
  • the threshold voltage of the MISFET is considered to increase or decrease due to the increase in the stress on the channel region, compared to the threshold voltage of the MISFET which is hardly affected by the stress.
  • the threshold voltage of the MIS FET increases due to an increase in the stress applied to the channel region, and the embodiment will be described below.
  • FIG. 4 is a plan view of a main part showing a first arrangement example of the MISF ET according to an embodiment of the present invention.
  • the first MIS to the 51st ISFET arranged based on the results obtained in FIGS. 1 to 3 will be used.
  • Q figure first 1 MISFET Q 2 is a 2M IS FE Ding
  • Q 3 l * l 3M ISF ET Q 4 is a 4M IS FE Ding
  • ⁇ 3 5 shows a first 51 ⁇ 1 ISF ET.
  • the 1 MIS £ Ding (3 1 to 51 ⁇ 1 and IS FETs Q 5 are disposed, these second 1 MISF ETQ, to third 5M ISF ETQ 5 of the gate electrode 2 having a width (gate The gate length g can be, for example, about 0.14 m
  • the isolation section 4 is formed by, for example, trench isolation.
  • the first MIS FETQ to the fifth MIS FETQ 5 are arranged in the gate length direction, and extend in the direction in which the gate electrode 2 extends (gate In the MIS FETs arranged in the width direction), the separation width of the element separation part 4 is assumed to be 0.35 m or more, and the element separation part 4 in the gate width direction is connected to the first MIS FETQ to the fifth MIS FETQ 5 . , Such as threshold voltage or drive current.
  • the 1 MIS FETs Q and the 2M IS min Hanarehaba of FETs Q 2 and the element isolation portion 4 for separating the L a and the 2 MISF ETQ 2 and the 3M ISFETQ 3 and the separation width La of the isolation unit 4 for separating 'the relative It is provided narrowly.
  • 2M IS
  • the effect of the stress on the channel region of the FETQ 2 is large, and the change in the threshold voltage due to the stress can be relatively large.
  • the separation width L a is, for example, 0.25 ⁇ M.
  • the 3M IS FETs Q 3 and the 4M IS of FET Q 4 and the isolation unit 4 for separating the separation width L b and a 4M IS FETs Q 4 and the 5 MIS FETs Q 5 and the separation width of the element isolation portion 4 separating L is relatively wide.
  • the influence of the stress on the channel region of the fourth MISF ETQ 4 is small, and the change in the threshold voltage due to the stress can be relatively reduced.
  • the distance from the side wall of the first MIS FETQ lj of the gate electrode 2 of the 2M ISF ETQ 2 to the end of the element isolation section 4 and the element from the side wall of the 3M ISF ETQ of the gate electrode 2 of the 4M IS FETQ 4 is almost the same distance c.
  • the distance Lc can be, for example, about 0.305 m.
  • the relationship with the distance Lc "from the side wall of the FETQ 5 to the end of the element isolation section 4 can be arbitrarily selected.
  • FIG. 5 is a plan view of a principal part showing a second arrangement example of the MIS FET according to the embodiment of the present invention. Similar to FIG. 1 described above, the description includes the first MI S FETG ⁇ to the fifth MI S
  • This I Li first 2 MIS FETs Q 2 of ⁇ boss stress effect is large
  • Do Li into the channel region can relatively greatly changes in threshold voltage due to stress.
  • the third MISF ETQ 3 of the gate electrode 2 of the 4M ISF ETQ 4 Away distance from distances d and the side wall of the 4 MIS FE TQ first 5 MISFET Q 5 side of the gate electrode 2 of 4 from the side wall side to the end portion of the isolation portion 4 to the end portion of the isolation portion 4 d, the It is provided relatively widely.
  • the influence of the stress on the channel region of the fourth MISFETQ4 is reduced, and the change in the threshold voltage due to the stress can be relatively reduced.
  • an element separation unit for separating the first MIS FETG ⁇ and the second MISFETQ 2
  • the separation width L a is, for example,
  • the isolation width of the element isolation section 4 for isolating the IS FETQ 5 is almost the same as the isolation width La ′.
  • FIG. 6 is a plan view of a main part showing a third arrangement example of the MISFET according to the embodiment of the present invention. Similar to FIG. 1 described above, the description includes the first MI S FETQ, to the fifth MI S FETQ.
  • the IMIS FETG ⁇ and the 2M IS min Hanarehaba of FETs Q 2 and the element isolation portion 4 for separating the L a and the 2 MIS FETs Q 2 and the 3M ISFETQ 3 and the separation width La of the isolation unit 4 for separating 'the relative It is provided narrowly.
  • the separation width La can be, for example, about 0.25 jUm. Further, the distance from the side wall of the 2M second 1 MISFET Q side of the IS FETs Q 2 of gate one Bok electrode 2 to the end portion of the isolation portion 4
  • the separation width Lb of the element separation section 4 for separating the third M ISFETQ 3 and the fourth M ISFETQ 4 is relatively wide. Further, the distance Ld from the side wall of the gate electrode 2 of the fourth MISFETQ 4 on the fifth MISFETQ 5 side to the end of the element isolation groove 4 is relatively wide. This I Li a 4 MIS FETs Q 4 stress effects are small and Li on the Channel region, the change in threshold voltage due to the stress can be relatively small.
  • FIG. 7 is a plan view of a main part showing a fourth arrangement example of the M 1 S FET according to the embodiment of the present invention.
  • the first MIS FETQ to the fourth MSF ETQ 4 arranged based on the results obtained in FIGS. 1 to 3 will be used.
  • This dummy active area DA DA 2 can be used for, for example, power supply.
  • the separation width La can be, for example, about 0.25; Um.
  • the separation width L b ′ of the element separation part 4 for separating the TQ 3 and the fourth MIS FETQ 4 is relatively wide. This affects the channel area of the third MISF ETQ 3. The effect of the stress is small, and the change in the threshold voltage due to the stress can be relatively reduced.
  • the distance from the side wall of the dummy active area DAj of the gate electrode 2 of the first MISF ETG ⁇ to the end of the element isolation part 4 and the element separation from the side wall of the second MSF ETQ of the gate electrode 2 of the third MISFETQ 3 is almost the same distance c.
  • the gate electrode 2 of the distance L c 'and the 3M ISF ETQ 3 from dummy active region DA 2 side sidewall of the gate electrode 2 of the 1 MISFET Q to the end of the element isolation portion 4 of the 4M ISF ETQ 4 side The distance from the side wall to the end of the element isolation portion 4 and the relationship with c "can be arbitrarily selected.
  • FIG. 8 is a plan view of a main part showing a fifth arrangement example of the MIS FET according to the embodiment of the present invention. Similar to FIG. 7, is used for the explanation first 1 MISF ETG ⁇ ⁇ a 4M ISF ETQ 4 and the dummy active regions DA ⁇ DA 2.
  • the distance L c ′ from the side wall to the end of the element isolation portion 4 is relatively narrow.
  • the separation width of the element separation part 4 for separating the first MIS FETG ⁇ from one dummy active area DA and the separation width of the element separation part 4 for separating the second M IS FETQ 2 and the third M IS FETQ 3 The width is almost the same separation width La. Further, the isolation width of the element isolation section 4 for isolating the first MIS FE from the other dummy active area DA 2
  • the separation width of the element separation unit 4 that separates the MISF ETQ 3 from the fourth M ISFETQ 4 is substantially the same separation width L a ′.
  • FIG. 9 is a plan view of a main part showing a sixth example of a MISFET according to an embodiment of the present invention. Used for the explanation first 1 MIS Mihinoto (3 1 to 51 ⁇ 1 IS FETs Q 5 arranged on the basis of the results obtained in FIG. 1 to FIG. 3.
  • a dummy gate electrode DG is arranged in the active region 3 at a distance L c ′ from the side wall of the gate electrode 2 of the second MISFET Q 2 on the side of the third MISFET Q 3 to the end of the element isolation portion 4. Can be.
  • the dummy gate electrode electrically use but does not affect the second MIS FETs Q 2 properties.
  • the distance Ld 'from the side wall of the second 5M IS FETQ 5 to the end of the element isolation section 4 is relatively wide. This allows the channel area of the 4M IS FETQ 4 The effect of the stress on the threshold voltage is small, and the change in the threshold voltage due to the stress can be relatively reduced.
  • the dummy gate electrode DG 2 may be arranged in the active region 3 at a distance L d from the side wall of the gate electrode 2 of the 4M ISF ETQ 4 on the side of the 3M ISF ETQ 3 to the end of the element isolation portion 4. it can.
  • the fifth gate electrode 2 of the 4M ISF ETQ 4 has the fifth MIS FET (35) and the dummy gate electrode DG is located in the active region 3 at a distance L d ′ from the side wall on the 5 side to the end of the element isolation portion 4. 3 can be arranged.
  • the dummy gate electrode DG 2, DG 3 is electrically use, it does not affect the characteristics of the 4M iS FETs Q 4.
  • the separation width of the element separation part 4 for separating the first MIS FETG ⁇ from the second M ISFETQ 2 and the separation width of the element separation part 4 for separating the third M IS FETQ 3 and the fourth M ISFETQ 4 are as follows. , With the same separation width a. Further, the separation width of the element isolation portion 4 which separates the first 2M IS FETs Q 2 and first 3M IS FETs Q 3, and the 4 MISFET TQ 4 and the 5M IS FETs Q 5 and the separation width of the element isolation portion 4 for separating the in And the separation width L a 'is almost the same.
  • FIG. 10 is a plan view of a main part showing a seventh example of a MISFET according to an embodiment of the present invention. As in FIG. 9, the first MIS FETG ⁇ to the fifth MSF ETQ 5 are used for the description.
  • the separation width La of the element separation part 4 for separating the IMIS FETG ⁇ from the second M ISFETQ 2 and the separation width La 'of the element separation part 4 for separating the second MIS FETQ 2 and the third M ISFETQ 3 are relative. It is provided narrowly. Also, the 2M IS FE
  • the distance Lc from the side wall of the gate electrode 2 of the TQ 2 on the side of the first MISFETQ, to the end of the element isolation portion 4 is relatively small. This allows the second MISFETQ The effect of the stress on the second channel region is large, and the change in the threshold voltage due to the stress can be relatively large.
  • a dummy gate electrode DG 4 may be arranged in the active region 3 at a distance L c ′ from the side wall of the gate electrode 2 of the second MIS FETQ 2 on the side of the third MISSFET 3 to the end of the element isolation portion 4. it can.
  • the Damige gate electrode DG 4 is electrically usable but not Succoth affecting especially 1 production of a 2M I SFETQ 2.
  • the separation width Lb of the element separation section 4 for separating the third M ISFETQ 3 and the fourth M ISFETQ 4 is relatively wide. Further, the distance Ld from the side wall of the gate electrode 2 of the fourth MIS FETQ 4 on the fifth MIS FETQ 5 side to the end of the element isolation groove 4 is relatively wide. As a result, the influence of the stress on the channel region of the 4M ISF ETQ 4 is small, and the change in the threshold voltage due to the stress can be relatively reduced.
  • the dummy gate electrodes DG 5 and DG 6 are arranged in the active region 3 with a distance L d from the side wall of the gate electrode 2 of the 4M IS FETQ 2 on the side of the 5M IS FETQ 5 to the end of the element isolation portion 4. be able to.
  • the dummy gate electrodes DG 5 and DG 6 can be used electrically, but do not affect the characteristics of the fourth MISFETQ 4 .
  • FIG. 11 is a diagram showing a configuration of a MISF arranged on a semiconductor chip according to an embodiment of the present invention.
  • FIG. 4 is a schematic plan view showing an example of an ET arrangement region.
  • the area LA is an area where a MIS FET having a relatively low threshold voltage (low V th) is arranged,
  • HA indicates the placement area of the MIS FET having a relatively high threshold voltage (high Vth)
  • area MA indicates the placement area of the MIS FET having a standard threshold voltage (standard Vth).
  • the threshold voltage of the MIS FET located in each region is low. Vth ⁇ standard Vt ⁇ high th.
  • the area LA can be, for example, a circuit area where high-speed operation is required. In this region LA, the influence of the stress on the MISFET is reduced by making the isolation width of the element isolation portion relatively large, and a MISFET having a relatively low threshold voltage is formed.
  • the area HA can be, for example, a memory cell part. In this region HA, the influence of the stress on the MISFET is increased by making the isolation width of the element isolation portion relatively narrow, and an M1 SFET having a relatively high threshold voltage is formed.
  • the area MA can be, for example, a gate array section, a general logic circuit section, or the like. In this area MA, the isolation width of the element isolation portion should be narrower than the isolation width of the element isolation portion formed in the above-mentioned area LA, and also wider than the isolation width of the element isolation portion formed in the above-mentioned area HA. Then, by setting the influence of the stress on the MIS FET at a level between the above-mentioned area LA and the above-mentioned area HA, an MIS FET having a standard threshold voltage is formed.
  • FIG. 12 is a schematic plan view showing an example of an arrangement region of a plurality of MIS FETs constituting a gate array arranged on a semiconductor chip according to an embodiment of the present invention.
  • the region in which the MISFET is formed is indicated by a rectangle.
  • a cell row is provided periodically according to the relatively large isolation width of the element isolation part. A circuit requiring a relatively low threshold voltage is formed in this area GA. .
  • a cell row is provided periodically according to the isolation width of the relatively small element isolation portion. A circuit requiring a relatively high threshold voltage is formed in the area GA 2 . Is done.
  • FIGS. 1-10 schematic plan views of an inverter circuit according to an embodiment of the present invention are shown in FIGS.
  • a region PMOS indicates a region where a p-channel M 1 SFET is formed
  • a region N MOS indicates a region where an n-channel MISFET is formed
  • 5 indicates an element isolation portion
  • 6 indicates an active region
  • 7 indicates a gate electrode. (shaded hatching)
  • 8 V DD supply wiring 9 V ss power supply wiring
  • 10 denotes an input signal line
  • 12 denotes a contact hole for connecting the wiring and the active region
  • 13 indicates a dummy active region
  • 14 indicates a dummy gate electrode.
  • FIG. 13 is a plan view of an inverter circuit in which a relatively high threshold voltage can be obtained by making the isolation width of the element isolation section 5 relatively narrow (La).
  • FIG. 14 shows the element isolation section.
  • 5 is a plan view of an inverter circuit that can obtain a relatively low threshold voltage by making the separation width of (5) relatively wide (Lb).
  • FIG. 15 is a plan view of an inverter circuit in which a relatively high threshold voltage can be obtained by providing the dummy active region 13.
  • FIG. 16 shows a case where no dummy active region is provided and the element separating section 5 is provided.
  • FIG. 4 is a plan view of an inverter circuit in which a relatively low threshold voltage can be obtained by making the separation width relatively large (L b).
  • FIG. 17 is a plan view of an inverter circuit in which a relatively high threshold voltage can be obtained by making the width of the active region 6 relatively narrow (L c).
  • FIG. 18 shows the width of the active region 6.
  • FIG. 4 is a plan view of an inverter circuit that can obtain a relatively low threshold voltage by making Ld relatively large. When the width of the active region 6 is relatively wide (Ld), the dummy gate electrode 14 can be provided in the active region 6.
  • FIG. 19 shows that a relatively high threshold voltage can be obtained by making the isolation width of the element isolation portion 5 relatively narrow (La) and the width of the active region 6 relatively small (Lc).
  • FIG. 20 is a plan view of the inverter circuit.
  • FIG. 20 shows that the isolation width of one of the element isolation portions 5 is relatively wide (Lb) and the width of the active region 6 in contact with the other of the element isolation portion 5 is relatively large.
  • FIG. 9 is a plan view of an inverter circuit that can obtain a relatively low threshold voltage by making it wider.
  • a dummy gate electrode 14 can be provided in the active region 6.
  • FIGS. 21 to 28 show schematic plan views of a two-input NAND circuit according to an embodiment of the present invention.
  • FIG. 21 is a plan view of a two-input NAND circuit in which a relatively high threshold voltage can be obtained by relatively narrowing the isolation width of the element isolation unit 5
  • FIG. FIG. 9 is a plan view of a two-input NAND circuit that can obtain a relatively low threshold voltage by making the width relatively wide.
  • FIG. 23 is a plan view of a two-input NAND circuit in which a relatively high threshold voltage can be obtained by providing the dummy active region 13, and FIG.
  • FIG. 3 is a plan view of the obtained two-input NAND circuit.
  • FIG. 25 is a plan view of a two-input NAND circuit in which a relatively high threshold voltage can be obtained by relatively narrowing the width of the active region 6, and FIG. 26 shows the width of the active region 6.
  • FIG. 9 is a plan view of a two-input NAND circuit in which a relatively low threshold voltage can be obtained by making the width relatively large.
  • Figure 27 shows a two-input NAND circuit in which a relatively high threshold voltage can be obtained by making the isolation width of the element isolation part 5 relatively narrow and the width of the active region 6 relatively small.
  • FIG. 28 is a plan view in which the isolation width of one of the element isolation sections 5 is relatively widened, and the width of the active region 6 in contact with the other of the element isolation section 5 is relatively wide.
  • FIG. 4 is a plan view of a two-input NAND circuit obtained by obtaining a particularly low threshold voltage. If the width of active region 6 is relatively widened, dummy gate electrode 14 can be provided in active region 6.
  • FIGS. 29 to 36 show schematic plan views of a two-input NOR circuit according to an embodiment of the present invention.
  • FIG. 29 is a plan view of a two-input NOR circuit in which a relatively high threshold voltage can be obtained by relatively narrowing the isolation width of the element isolation unit 5
  • FIG. FIG. 11 is a plan view of a two-input NOR circuit in which a relatively low threshold voltage can be obtained by making the isolation width relatively wide.
  • FIG. 31 is a plan view of a two-input NOR circuit in which a relatively high threshold voltage can be obtained by providing the dummy active 1 active region 13.
  • FIG. 9 is a plan view of a two-input NOR circuit that can obtain a relatively low threshold voltage by making a separation width of a separation unit 5 relatively wide.
  • FIG. 33 is a plan view of a two-input NOR circuit in which a relatively high threshold voltage can be obtained by relatively narrowing the width of the active region 6, and FIG. FIG. 4 is a plan view of a two-input NOR circuit in which a relatively low threshold voltage can be obtained by making the width relatively large.
  • a dummy gate electrode 14 can be provided in the active region 6.
  • FIG. 35 shows that the isolation width of the element isolation portion 5 is relatively narrow and the width of the active region 6 is relatively small.
  • FIG. 36 is a plan view of a two-input NOR circuit in which a relatively high threshold voltage can be obtained by making the width narrower.
  • FIG. 9 is a plan view of a two-input NOR circuit in which a relatively low threshold voltage can be obtained by making the width of an active region 6 in contact with the other side of the element isolation part 5 relatively wide.
  • dummy gate electrode 14 can be provided in active region 6.
  • region A 1 is a region where a CMOS device having a relatively thin gate insulating film and relatively high threshold voltage is formed
  • region A 2 is a film thickness of a gate insulating film. Is a region where a CMOS device with a relatively thin and relatively low threshold voltage is formed
  • region A3 is a region where a CMOS device with a relatively thick gate insulating film is formed.
  • a semiconductor substrate 21 composed of a silicon single crystal having a specific resistance of about 10 ⁇ cm is prepared, and a shallow groove 22 is formed on the main surface of the semiconductor substrate 21.
  • a thermal oxidation process is performed on the semiconductor substrate 21 to form a silicon oxide film (not shown), a silicon oxide film 23 is deposited thereon, and then, this is polished by a CMP method to form a shallow groove 22.
  • An element isolation portion is formed by leaving the silicon oxide film 23 only in the inside. At this time, the isolation width (L H ) of the element isolation portion formed in the region A 1 is relatively narrow, and the isolation width (L L ) of the element isolation portion formed in the region A 2 is relatively wide. Is performed.
  • a p-type impurity such as boron is formed in the regions for forming the n-channel MISs and FETs in the regions A 1 and A 2.
  • (B) is ion-implanted to form a p-type ⁇ : i: 25, and then an impurity for adjusting the threshold voltage of the n-channel MISFET is ion-implanted to control the threshold voltage.
  • Form layer 26 is ion-implanted to form a p-type ⁇ : i: 25.
  • the p-channel M of the region A 1 and the region A 2 is formed using the patterned resist film 27 as a mask.
  • n-type impurity for example, phosphorus (P) is ion-implanted into a region for forming the ISFET to form an n-type well 28, and then the threshold voltage of the p-channel MISFET is formed.
  • the threshold voltage control layer 29 is formed by ion-implanting an impurity for adjusting the pressure.
  • a p-type impurity is formed in the region for forming the n-channel MISFET in the region A3.
  • boron is ion-implanted to form a p-type well 31, and then an impurity for adjusting the threshold voltage of the n-channel MISFET is ion-implanted to form a threshold voltage control layer 32. .
  • the patterned resist film 33 is used as a mask to form an n-type impurity in a region for forming a p-channel MISFET in the region A 3.
  • phosphorus is ion-implanted to form an n-type well 34, and then an impurity for adjusting the threshold voltage of the p-channel MISFET is ion-implanted to form a threshold voltage control layer 35. I do.
  • a relatively thin gate insulating film is formed on the surface of the semiconductor substrate 21 in the regions A 1 and A 2, and a relatively thin gate insulating film is formed on the surface of the semiconductor substrate 1 in the region A 3.
  • a thick gate insulating film is formed.
  • the following method can be exemplified.
  • the semiconductor substrate 21 is subjected to a thermal oxidation treatment, and the surface of the semiconductor substrate 21 has a thickness of about 6 to 7 nm.
  • a silicon oxide film 36 is formed.
  • the silicon oxide film 36 in the regions A 1 and A 2 is removed, thereby leaving the silicon oxide film 36 in the region A 3 as shown in FIG.
  • a gate insulating film 37 a is formed on the surface of the semiconductor substrate 21 in the regions A 1 and A 2.
  • a silicon oxide film of about 4 nm is formed, and at the same time, a silicon oxide film of about 8 nm forming a gate insulating film 37b is formed on the surface of the semiconductor substrate 21 in the region A3.
  • a polycrystalline silicon film doped with impurities is deposited on the semiconductor substrate 21 by the CVD method, and the patterned polycrystalline silicon film is used as a mask. The film is etched to form a gate electrode 38 composed of a polycrystalline silicon film.
  • FIG. 44 for example, a polycrystalline silicon film doped with impurities is deposited on the semiconductor substrate 21 by the CVD method, and the patterned polycrystalline silicon film is used as a mask. The film is etched to form a gate electrode 38 composed of a polycrystalline silicon film.
  • the n-type wells 28 and 34 are covered with a resist S (not shown), and the p-type wells 25 and 31 are formed using the gate electrode 38 of the n-channel MISF ET as a mask.
  • An n-type impurity for example, arsenic (As) is ion-implanted to form a low-concentration n-type semiconductor region 39 constituting a source and a drain of the n-channel MISFET.
  • the p-type wells 25 and 31 are covered with a resist film (not shown), and the n-type wells 28 and 34 are p-type impurities such as boron fluoride using the p-channel MISF ET gate electrode 38 as a mask.
  • BF 2 BF 2
  • RIE reactive ion etching
  • the n-type wells 28 and 34 are covered with a resist film (not shown), and the n-type MISFET gate electrodes 38 and sidewall spacers 41 are used as masks to form the n-type wells 25 and 31 into n-type wells.
  • Impurities for example, arsenic are ion-implanted to form a low-concentration n + type semiconductor region 42 constituting the source and drain of the n-channel MISFET.
  • the p-type wells 25 and 31 are covered with a resist film (not shown), the p-channel MISFET gate electrode 38 and the sidewall spacer 41 are masked, and the n-type wells 28 and 34 have p-type impurities.
  • boron fluoride is ion-implanted to form a low-concentration p + type semiconductor region 43 constituting the source and the drain of the p-channel MISFET.
  • the semiconductor substrate 21 is subjected to a heat treatment at, for example, 1000 ° C. for about 5 seconds to activate the n-type impurities and the p-type impurities implanted into the semiconductor substrate 21.
  • the interlayer insulating film 44 is etched using the patterned resist film as a mask to reach the source and drain of the n-channel MISFET.
  • a contact hole 45 n and a contact hole 45 p reaching the source and drain of the p-channel MISF ET are formed.
  • a contact hole reaching the gate electrode 38 of the n-channel MISFET and the p-channel MISFET is formed at the same time.
  • a metal film for example, tungsten (W) is deposited on the interlayer insulating film 44, and the surface of the metal film is flattened by, for example, a CMP method, thereby forming the contact holes 45n, 45p.
  • a plug 46 is formed by embedding a metal film inside.
  • the metal film deposited on the interlayer insulating film 44 is etched to form the wiring layer 47, thereby completing the CMOS device substantially.
  • the isolation width (L H ) of the element isolation portion formed in the region A1 is relatively narrow, and the isolation width (J is relatively large) of the element isolation portion formed in the region A2.
  • the p-type well 25 of the n-channel MISFET, the threshold voltage control layer 26 of the n-channel MISFET, the n-type well 28 of the p-channel MISFET and the p-type MISFET Even if the threshold voltage control layers 29 are formed in the same process, for example, the threshold voltage of the n-channel MISFET in the region A1 is relatively high, and the threshold voltage of the n-channel MISFET in the region A2 is relatively high. Therefore, the isolation width of the element isolation portion formed in the region A1 is equal to the isolation width of the element isolation portion formed in the region A2. 6 steps including the lithography process, and 2 lithography It is possible to reduce the mask for Rafi.
  • the separation width of the element separation part for electrically separating the MISFET by adjusting the separation width of the element separation part for electrically separating the MISFET, the distance from the gate electrode of the MISFET to the element separation part, or both of them, Even if the elements that make up the MISFET, such as the gate length, the thickness of the gate insulating film, or the concentration of the impurity introduced into the substrate, are the same, the characteristics desired for each of the MISFETs, such as the threshold voltage or An electric current can be obtained. Further, since the number of manufacturing steps such as a lithographic process and an ion implantation step can be reduced, manufacturing costs can be reduced.
  • the threshold voltage of the MISFET is increased has been described. Power reduction is also possible, and the threshold voltage of the MIS FET can be adjusted higher or lower than the standard threshold voltage.
  • the element isolation portion is configured by the trench isolation.
  • the present invention is not limited to this.
  • the device isolation portion may be configured by LOCOS (local oxidation of siI icon), and the same effect is obtained. can get.
  • the threshold voltage is mainly exemplified as the characteristic of the MISFET which varies with the stress, but other characteristics, for example, the driving current can also be varied with the stress.

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Abstract

Les largeurs d'isolation (La et La') d'une portion d'isolation d'élément sont relativement petites. C'est pourquoi, l'influence de la contrainte sur une zone de canal d'un deuxième MISFET (Q2) est forte, et la modification de la tension seuil est relativement importante. Les largeurs d'isolation (Lb et Lb') de la portion d'isolation d'élément (4) sont relativement larges. C'est pourquoi l'influence de la contrainte sur une zone de canal d'un quatrième MISFET (Q4) est faible, et la modification de la tension seuil est relativement peu importante.
PCT/JP2002/003944 2001-06-05 2002-04-19 Dispositif semi-conducteur a circuit integre et procede de fabrication associe WO2002099872A1 (fr)

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JP4491605B2 (ja) * 2003-02-19 2010-06-30 株式会社ルネサステクノロジ 半導体集積回路装置
JP4504633B2 (ja) 2003-05-29 2010-07-14 パナソニック株式会社 半導体集積回路装置
JP4608901B2 (ja) * 2004-02-09 2011-01-12 ソニー株式会社 半導体装置
JP2005286341A (ja) * 2004-03-30 2005-10-13 Samsung Electronics Co Ltd 低ノイズ及び高性能のｌｓｉ素子、レイアウト及びその製造方法
KR100541656B1 (ko) * 2004-08-03 2006-01-11 삼성전자주식회사 성능이 향상된 ｃｍｏｓ 소자 및 그 제조 방법
JP4936418B2 (ja) * 2005-05-17 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置とその製造方法、及び半導体装置の設計プログラム
JP2007012855A (ja) 2005-06-30 2007-01-18 Matsushita Electric Ind Co Ltd 半導体集積回路、標準セル、標準セルライブラリ、半導体集積回路の設計方法および半導体集積回路の設計装置
US7259393B2 (en) * 2005-07-26 2007-08-21 Taiwan Semiconductor Manufacturing Co. Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses
JP5091462B2 (ja) * 2006-01-19 2012-12-05 パナソニック株式会社 セルおよび半導体装置
JP5096719B2 (ja) * 2006-09-27 2012-12-12 パナソニック株式会社 回路シミュレーション方法及び回路シミュレーション装置
JP2009021482A (ja) * 2007-07-13 2009-01-29 Nec Electronics Corp 半導体集積回路の自動レイアウト装置及びプログラム
JP2009026829A (ja) * 2007-07-17 2009-02-05 Nec Electronics Corp 半導体集積回路の設計方法及びマスクデータ作成プログラム
JP5292005B2 (ja) * 2008-07-14 2013-09-18 ルネサスエレクトロニクス株式会社 半導体集積回路
JP5464761B2 (ja) * 2011-12-19 2014-04-09 ルネサスエレクトロニクス株式会社 半導体装置とその製造方法、及び半導体装置の設計プログラム
KR101974439B1 (ko) 2012-06-11 2019-05-02 삼성전자 주식회사 반도체 장치 및 그 제조 방법

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