WO2002082542A1 - Dispositif de puissance à semi-conducteurs - Google Patents
Dispositif de puissance à semi-conducteurs Download PDFInfo
- Publication number
- WO2002082542A1 WO2002082542A1 PCT/JP2001/002876 JP0102876W WO02082542A1 WO 2002082542 A1 WO2002082542 A1 WO 2002082542A1 JP 0102876 W JP0102876 W JP 0102876W WO 02082542 A1 WO02082542 A1 WO 02082542A1
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- semiconductor device
- control
- power semiconductor
- control board
- relay terminal
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/14—Mounting supporting structure in casing or on frame or rack
- H05K7/1422—Printed circuit boards receptacles, e.g. stacked structures, electronic circuit modules or box like frames
- H05K7/1427—Housings
- H05K7/1432—Housings specially adapted for power drive units or power converters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/14—Mounting supporting structure in casing or on frame or rack
- H05K7/1422—Printed circuit boards receptacles, e.g. stacked structures, electronic circuit modules or box like frames
- H05K7/1427—Housings
- H05K7/1432—Housings specially adapted for power drive units or power converters
- H05K7/14329—Housings specially adapted for power drive units or power converters specially adapted for the configuration of power bus bars
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/30—Technical effects
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- H01L2924/30107—Inductance
Definitions
- the present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a plurality of semiconductor device modules.
- FIG. 11 shows a perspective view of a semiconductor device module 90 as an example of a conventional power semiconductor device. In FIG. 11, a part is cut away to show the internal configuration.
- a power semiconductor element (not shown) is housed in a box-shaped resin case 11, and a control board CB is disposed above the power semiconductor element. Have been.
- the control board CB has control circuits and elements that control the operation of power semiconductor elements such as IGBT (Insulated Gate Bipolar Transistor) elements and diode elements. 90 is an IPM (Intelligent Power Module).
- the control board CB is provided so as to cover almost the entire area of the area where the power semiconductor element is provided, and is electrically connected to the power semiconductor element by connection means (not shown).
- connection means not shown.
- a lead-out terminal 0 T for outputting the operating state of the internal power semiconductor element to the outside and supplying power to the control circuit is provided, and the resin case 11 is provided. It is configured to protrude from the upper part and be electrically connectable to the outside.
- a resin material is sealed in the resin case 11, illustration of the resin is omitted.
- the main circuit terminals Ml and M2 for introducing and deriving the main current flowing through the internal power semiconductor element are arranged on the edge not covered by the control board CB, and the resin case 11 It is configured to protrude from the upper edge and to be electrically connectable to the outside.
- the control board CB is disposed on the same plane as the power semiconductor element.
- the control board Built-in CB which limits the location of main circuit terminals M1 and M2 and increases inductance due to longer paths of main circuit terminals Ml and M2
- the surge voltage may affect the performance of the semiconductor device module.
- the area in which the power semiconductor element is arranged is limited, and the number and layout of the power semiconductor elements mounted are limited. Will be limited.
- the present invention has been made to solve the above-described problems, and solves the inconvenience due to the presence of a control board, and makes it easy to electrically connect a power semiconductor element and a main circuit terminal. It is an object of the present invention to provide a semiconductor device module which is hardly limited by the number of mounted semiconductor elements and the layout rate.
- a plurality of semiconductor device modules having: a main circuit terminal; a control terminal projecting out of the resin case to the outside and receiving a control signal for controlling the power semiconductor element; and the plurality of semiconductor device modules.
- a bus bar electrically connected in common to the main circuit terminals of the plurality of semiconductor device modules, and a bus bar that covers at least the projecting control terminals of the plurality of semiconductor device modules.
- a control board electrically connected to the control terminal.
- the control board since the control board is provided outside the semiconductor device module, the lead-out path of the main circuit terminal of the power semiconductor element can be freely selected. Therefore, electrical connection between the power semiconductor element and the main circuit terminal is facilitated.
- the control board externally, the number of mounted power semiconductor elements and the layout are less restricted.
- the plurality of semiconductor device modules are arranged so that their main circuit terminals are arranged in a line, and the main circuit terminals are electrically connected in common by bus bars. It can also be used as a means of mechanically connecting the body device module, special, connecting means Even without providing, a structurally strong power semiconductor device can be obtained.
- control terminal protrudes to the outside from an edge of the resin case
- control board includes: a control terminal of the plurality of semiconductor device modules; It is disposed so as to cover only the protruding edge portion.
- control board since the control board is disposed so as to cover only the edges of the plurality of semiconductor device modules from which the control terminals protrude, the control board can be made compact.
- the plurality of semiconductor device modules are arranged such that the edge portions from which the control terminals protrude are adjacent to each other.
- the plurality of semiconductor device modules are disposed so as to straddle between the edge portions of the array.
- the size of the control board can be reduced.
- a fourth aspect of the semiconductor device module according to the present invention is the semiconductor device module, wherein the control board is large enough to cover substantially the entire area where the plurality of semiconductor device modules are provided, and is provided above the bus bar. Have been.
- the control board is large enough to cover almost the entire area where the plurality of semiconductor device modules are arranged, and is arranged above the bus bar.
- the control board there is no need to provide an opening or the like in the control board for passing the main circuit terminals, and a control board having strong strength can be obtained.
- the degree of freedom in arranging a plurality of semiconductor device modules is increased.
- control board is provided so as to cover upper portions of the plurality of semiconductor device modules except for a region where the main circuit terminal is provided. .
- the degree of freedom in the layout of the plurality of semiconductor device modules is increased.
- the control board has a wiring pattern that electrically connects the control terminals to each other electrically, and a plan view shape of the wiring pattern is provided. , Non-loop shape.
- the planar shape of the wiring pattern is a non-loop shape, it is influenced by the main circuit current flowing through the main circuit terminal, so that the induced current is annularly formed. Flows, and the characteristics of the power semiconductor element can be prevented from fluctuating.
- a seventh aspect of the semiconductor device module according to the present invention is a semiconductor device module, comprising: a resin case; a power semiconductor element housed in the resin case; A control terminal to which a control signal for control is input; a plurality of semiconductor device modules having: a control board electrically connected to the control terminal; and the plurality of semiconductor device modules are: The edge portions from which the control terminals protrude are arranged adjacent to each other, and the control board is disposed so as to straddle between the edge portions in the array of the plurality of semiconductor device modules. ing.
- the seventh aspect of the semiconductor device module according to the present invention by arranging the plurality of semiconductor device modules such that the edges where the control terminals protrude are adjacent to each other, each control terminal is Since they are present close to each other, the size of the control board can be reduced.
- FIG. 1 is a perspective view showing a configuration of an embodiment of a power semiconductor device according to the present invention.
- FIG. 2 is a diagram showing a connection relationship between power semiconductor elements.
- FIG. 3 is a perspective view showing a configuration of an embodiment of a power semiconductor device according to the present invention.
- FIG. 5 is a plan view showing a configuration of a control board of the power semiconductor device according to the present invention is a plan view showing a configuration of a control board of the power semiconductor device according to the present invention
- FIG. 6 is a plan view showing an example of the arrangement of the semiconductor device modules.
- FIG. 7 is a perspective view showing a configuration of a semiconductor device module.
- FIG. 8 is a diagram showing a connection relationship of the power semiconductor elements.
- FIG. 9 is a perspective view showing a configuration of a modification of the embodiment of the power semiconductor device according to the present invention.
- FIG. 10 is a perspective view showing a configuration of a modification of the embodiment of the power semiconductor device according to the present invention.
- FIG. 11 is a perspective view showing a configuration of a conventional semiconductor device module.
- FIG. 1 shows a perspective view of a semiconductor device module 100 as an embodiment of a power semiconductor device according to the present invention.
- a part is shown in a cutaway view to show the internal configuration.
- an insulating substrate 3 is disposed on a bottom substrate 1 2 formed of a material having good thermal conductivity such as a metal and having a rectangular shape in plan view, and an IGBT element 1 is provided on the insulating substrate 3. And the diode elements 2 are arranged in pairs.
- a box-shaped resin case 11 is provided so as to surround the bottom substrate 12, and a resin material is sealed in a space defined by the bottom substrate 12 and the resin case 11. ing. Illustration of the resin is omitted.
- FIG. 2 shows the connection relationship between the IGBT element 1 and the diode element 2.
- the diode element 2 is connected in parallel to the IGBT element 1 so that the forward current flows.
- the main collector electrode and the main emitter electrode of the IGBT element 1 are connected to the outside via main circuit terminals M 1 and M 2, and the control emitter electrode and the gate electrode are connected to the control emitter relay terminals ⁇ and It is configured to be connected to the outside via the gate relay terminal 8. Since the control emitter relay terminal 7 and the gate relay terminal 8 are terminals to which control signals are input, they can be called control terminals.
- a relay terminal plate 6 is disposed along an insulating substrate 3 at an end of the bottom substrate 12, and on the bottom substrate 12, a relay terminal plate 6 is disposed on an end thereof. end The IGBT element 1 is arranged at the edge.
- the relay terminal plate 6 has, for example, a control emitter pad 71 and a gate pad 81 that are electrically insulated on a main surface of a substrate such as an insulating substrate.
- the control emitter pad 71 is electrically connected to the control emitter electrode (synonymous with the emitter electrode) of the I08 element 1 by a wire WR (aluminum wire), and the gate pad 81 is an IGB II element. It is electrically connected to the 1 gate electrode by wire wiring WR. Further, the emitter electrode of the IGBT element 1 is electrically connected to the anode of the diode element 2 via a wire WR.
- the control emitter pad 71 and the gate pad 81 are configured so that the control emitter relay terminal 7 and the gate relay terminal 8 extending in the vertical direction are connected to the control emitter pad 71 and the gate pad 81, respectively.
- the terminal 7 and the gate relay terminal 8 are configured to protrude outside from the edge of the upper surface of the resin case 11.
- connection between the control relay terminal 7 and the control pad 71 and the connection between the gate relay terminal 8 and the gate pad 81 are performed by, for example, soldering.
- the relay terminal 9 is configured to protrude together with the control emitter relay terminal 7 and the gate relay terminal 8.
- the relay terminal 9 is connected to the pad 91, which is arranged on the relay terminal plate 6 alongside the control emitter pad 71 and the gate pad 81, but the pad 91 is connected to nowhere. Not.
- the pad 91 and the relay terminal 9 are used as needed, and are connected to, for example, the current sensing electrode of the element 108.
- the current sense electrode is an electrode formed so that a current (sense current) of one thousandth of the current flowing to the main emitter electrode flows. By detecting the sense current, the IGB ⁇ element 1 Overcurrent protection and short-circuit protection are enabled.
- the convenience of the user can be considered. Note that only the pad 91 may be provided, and the relay terminal 9 may be connected as necessary.
- the control emitter relay terminal 7, the gate relay terminal 8, and the relay terminal 9 are connected by soldering or the like to the control board 10 disposed above the edge of the semiconductor device module 100. It has become.
- the control board 10 includes a control circuit (not shown) and an element for controlling the operation of the IGBT element 1 and the diode element 2, a control emitter wiring pattern to which the control emitter relay terminal 7 is connected, and a gate relay. It has a gate wiring pattern to which the terminal 8 is connected, and these wiring patterns are configured to be connected to the control circuit.
- the main circuit terminals for connecting the main collector electrode and the main emitter electrode of the IGB element 1 to the outside are not shown, but the control board 10 is located outside the semiconductor device module 100. Since it is arranged so as to partially cover the edge, the lead-out route of the main circuit terminal can be selected relatively freely.
- the control board 10 is a control emitter relay terminal 7, a gate relay terminal 8, and a relay that protrude from one of the four edges on the upper surface of the semiconductor device module 100.
- the configuration for engaging with the terminal 9 is shown, as shown in FIG. 3, the two semiconductor device modules 100 are disposed so as to straddle between the edge portions of the two semiconductor device modules 100, and the two semiconductor device modules 100
- the control terminal 7, the gate terminal 8, and the relay terminal 9 (which may be hereinafter referred to as a relay terminal group) that protrude at the edge of each terminal may be engaged.
- the control terminals of the two semiconductor device modules 100 relay terminals 7 and gate relay terminals 8, that is, the same type of relay terminals are electrically connected in common in the control board 10.
- the two semiconductor device modules 100 can be controlled in parallel.
- Such a configuration in which a plurality of semiconductor device modules are controlled in parallel is referred to as a module unit.
- control board 10 is supported by columns S ⁇ provided at the four corners, and the upper main surface outputs the operating state of the internal power semiconductor element to the outside. And a lead-out terminal 0 ⁇ for supplying power to the control circuit (not shown).
- FIG. 4 is a plan view of the control board 10 engaging with the two semiconductor device modules 100 as viewed from above, and a plan view of the control board 10 as viewed from below. See Figure 5. 4 and 5, the internal configuration of the control board 10 is shown in a partially cutaway view.
- the control board 10 is provided with a gate wiring pattern 82 for connecting the gate relay terminals 8 to each other on the upper main surface side as shown in FIG. 4, and a control board on the lower main surface side as shown in FIG.
- An emitter wiring pattern 72 for connecting the relay terminals 7 is provided, and both main surfaces are covered with an insulator.
- the wiring pattern connecting the relay terminals 9 is formed in a layer between the gate wiring pattern 82 and the emitter wiring pattern 72. It may be provided.
- the wiring pattern 72 should be provided so that the gate relay terminal 8 does not come into contact with the wiring pattern 72, and the connection between each wiring pattern and each relay terminal should be soldered. It is needless to say that electrical connection is surely made by the above method.
- each relay terminal group is arranged in a line other than that shown in FIG.
- a control board that commonly connects the same type of relay terminals may be used.
- a relay terminal group is arranged on the right edge, and the semiconductor device module on the right side in FIG. In 100, a relay terminal group is disposed on the left edge portion.
- the relay terminal groups are disposed so as to be close to each other.
- the area of the control board can be reduced, but for this purpose, the two semiconductor device modules 100 are arranged in the opposite directions so that the edges where the relay terminal groups protrude are adjacent to each other. Just do it.
- FIG. 3 shows a configuration in which the relay terminal groups of the two semiconductor device modules 100 are electrically connected in common by the control board 10 and are controlled in parallel. Is not limited to one, for example, As shown in Fig. 6, a module unit composed of a total of six semiconductor device modules 100 can be obtained by using a control board 20 to which three semiconductor device modules 100 can be connected. .
- the lead-out paths of the main circuit terminals Ml and M2 can be freely selected.
- the main circuit terminals Ml and M2 are not connected.
- terminals of the same kind are electrically connected in common.
- connection means for this purpose for example, in the arrangement of semiconductor device modules as shown in FIG. 6, a strip-shaped bus bar composed of a conductor plate is arranged as shown by a dashed line, and Since it is efficient to connect the circuit terminals in a straight line, it is desirable that the same type of main circuit terminals be arranged in a line and that different types of main circuit terminals do not exist between them.
- a plurality of main circuit terminals Ml and M2 are arranged in parallel and in a line.
- the busbar not only electrically connects the same type of main circuit terminals in common but also functions as a means for mechanically connecting a plurality of semiconductor device modules, and structurally without special connection means. A strong module unit can be obtained.
- FIG. 6 shows a configuration in which the semiconductor device modules 100 are arranged in two rows, a configuration having only one row on one side is also possible. In short, if a control board that can commonly connect the same type of relay terminals is used, it is possible to control a plurality of semiconductor device modules in parallel.
- the semiconductor device module 100 shown in FIG. 1 has a structure in which one element 1 and one diode element 2 are provided, and one set of relay terminal groups is provided for each of them.
- the configuration of the semiconductor device module is not limited to this. For example, as shown in a semiconductor device module 100 A shown in FIG. 7, a plurality of pairs of the IGBT element 1 and the diode element 2 are provided. And a configuration having one set of relay terminal groups for each.
- control board 30 is configured to be connectable to three sets of relay terminals.
- relay terminal plate 6A has a configuration in which three control pads 71, a gate pad 81, and a pad 91 can be disposed in succession.
- the semiconductor device module 100A shown in FIG. 7 has a configuration in which a plurality of pairs of 1.8 elements 1 and a diode element 2 are provided, each of which has one set of relay terminal groups.
- a configuration in which six IGBT elements 1 are connected in parallel and a diode element 2 is connected to them in a one-to-one manner may be adopted.
- the gate electrodes of the respective IGB T elements 1 are commonly connected to a gate relay terminal 8, and the control emitter electrode is commonly connected to a control emitter relay terminal 7.
- the main collector electrode and the main emitter electrode of each IGB T element 1 are commonly connected to the main circuit terminals M1 and M2.
- the relay terminal group is one set, and the main circuit terminals M 1 and M 2 are also one set for six sets of the IGB T element 1 and the diode element 2. Action effect
- the control board 10 is provided outside the semiconductor device module 100, and the control board 10 is provided on the edge of the semiconductor device module 100. Since it is arranged so as to partially cover it, the lead path of the main circuit terminal connecting the main collector electrode and the main emitter electrode of the IGBT element 1 to the outside can be freely selected. Therefore, electrical connection between the power semiconductor element and the main circuit terminal is facilitated.
- control board 10 since the control board 10 is provided externally, the number of mounted power semiconductor elements and the layout rate are less restricted.
- control emitter relay terminal 7 and the gate relay terminal 8 are configured to protrude outward from the upper edge of the resin case 11, a plurality of semiconductor device modules 10 are arranged so that the relay terminal groups face each other. 0 are arranged in parallel in two rows, and the control board 10 is engaged with the relay terminal group of the plurality of semiconductor device modules 100 to control the control board 10. By connecting common relay terminals of the same type, a plurality of semiconductor device modules 100 can be controlled in parallel.
- the relay terminal group (that is, the control emitter relay terminal 7, the gate relay terminal 8, and the relay terminal 9) has the semiconductor device projecting from one of the four edge portions.
- the configuration in which the module 100 is engaged with the control board 10 has been described, the configuration of the control board is different in a semiconductor device module having a plurality of relay terminal groups.
- FIG. 9 shows a semiconductor device module 200 in which the relay terminal group protrudes from two opposing edges of the four edges.
- FIG. 9 shows two left and right semiconductor device modules 200, both have the same configuration.
- the semiconductor device module 200 has a relay terminal group at each of two right and left edges, and has two sets of main circuit terminals M1, M2 and M11 and M12. are doing.
- the main circuit terminals Ml and M2 and the relay terminal group on the left side in the figure form a pair, and the main circuit terminals M11 and M12 and the relay terminal group on the right side in the figure form a group.
- the control board 40 covers the upper part of the two semiconductor device modules 200 except for the areas where the main circuit terminals Ml and M2 and the main circuit terminals M11 and M12 are arranged. Are provided.
- control board 40 Since the control board 40 has a wiring pattern PT that engages with the four relay terminal groups and connects the same type of relay terminals in common, the two semiconductor device modules 200 are controlled in parallel. Will be. The use of such a control board 40 increases the degree of freedom in the layout of the semiconductor device modules.
- the pattern shape of the wiring pattern PT indicated by a broken line in FIG. 9 is an example, but the wiring pattern is not a loop shape similar to the planar shape of the control board 40 but is partially By forming a non-loop shape area where no circuit is provided, the circuit is guided by the influence of the main circuit current flowing through the main circuit terminals M1, M2 and the main circuit terminals M11, M12. Current can be prevented from fluctuating the gate characteristics. Further, as described with reference to FIG. 4, for example, the wiring pattern PT is formed by arranging the emitter wiring pattern 72 on the lower main surface side and the gate wiring pattern 82 on the upper main surface side. What is necessary is just to set it as the structure which prevents the short circuit between wiring patterns.
- the control board 100 described in the embodiment is suitable for parallel control of module units in which the semiconductor device modules 100 are arranged in two rows in parallel so that the relay terminal groups are adjacent to each other.
- the restriction on the layout rate of the semiconductor device modules can be reduced.
- a plurality of semiconductor device modules 100 are arranged in two rows, and above them are connected to each relay terminal group (that is, control emitter relay terminal 7, gate relay terminal 8, and relay terminal 9).
- a control board 50 is provided so as to match.
- the semiconductor device module 100 is arranged such that main circuit terminals of the same type are arranged in a line, but the arrangement of the relay terminal groups is not arranged between the arrays.
- control board 50 has an area that almost covers the entire arrangement of the semiconductor device modules 100, and can engage with the relay terminal group at any position within the area. Because.
- bus bars ⁇ 1 and ⁇ 2 are electrically connected so that the main circuit terminals ⁇ 1 and ⁇ 2 arranged in a line are electrically connected in common. Two are arranged.
- the control board 50 is arranged at a position higher in the height direction than the arrangement position of the bus bars ⁇ 1 and ⁇ 2. It can be installed stably by supporting it with the support S ⁇ provided in module 100 c In order to control all the semiconductor device modules 100 in parallel, the bus bars B 1 and the bus bars B 2 may be connected in common.
- control board 50 does not have an opening or the like, it is structurally strong, and the busbars B1 and B2, together with the connection of the main circuit terminals M1 and M2, are structurally more robust. Module unit can be obtained.
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/276,291 US6717258B2 (en) | 2001-04-02 | 2001-04-02 | Power semiconductor device |
JP2002565154A JPWO2002082542A1 (ja) | 2001-04-02 | 2001-04-02 | 電力用半導体装置 |
PCT/JP2001/002876 WO2002082542A1 (fr) | 2001-04-02 | 2001-04-02 | Dispositif de puissance à semi-conducteurs |
EP01917796A EP1376695A4 (en) | 2001-04-02 | 2001-04-02 | SEMICONDUCTOR POWER DEVICE |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2001/002876 WO2002082542A1 (fr) | 2001-04-02 | 2001-04-02 | Dispositif de puissance à semi-conducteurs |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002082542A1 true WO2002082542A1 (fr) | 2002-10-17 |
Family
ID=11737220
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2001/002876 WO2002082542A1 (fr) | 2001-04-02 | 2001-04-02 | Dispositif de puissance à semi-conducteurs |
Country Status (4)
Country | Link |
---|---|
US (1) | US6717258B2 (ja) |
EP (1) | EP1376695A4 (ja) |
JP (1) | JPWO2002082542A1 (ja) |
WO (1) | WO2002082542A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101098399B1 (ko) | 2008-06-20 | 2011-12-26 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 |
JP2015135891A (ja) * | 2014-01-17 | 2015-07-27 | 株式会社豊田自動織機 | 半導体装置 |
JP2017011926A (ja) * | 2015-06-24 | 2017-01-12 | 富士電機株式会社 | 電力変換装置 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200743035A (en) * | 2006-05-09 | 2007-11-16 | Siliconware Precision Industries Co Ltd | Circuit card module and method for fabricating the same |
JP4720756B2 (ja) * | 2007-02-22 | 2011-07-13 | トヨタ自動車株式会社 | 半導体電力変換装置およびその製造方法 |
US20090091889A1 (en) * | 2007-10-09 | 2009-04-09 | Oman Todd P | Power electronic module having improved heat dissipation capability |
JP2012124294A (ja) * | 2010-12-08 | 2012-06-28 | Sumitomo Electric Ind Ltd | 半導体モジュール及びその製造方法 |
US8466541B2 (en) * | 2011-10-31 | 2013-06-18 | Infineon Technologies Ag | Low inductance power module |
JP6119313B2 (ja) * | 2013-03-08 | 2017-04-26 | 富士電機株式会社 | 半導体装置 |
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EP0772235A2 (en) * | 1995-10-25 | 1997-05-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device comprising a circuit substrate and a case |
JPH09130068A (ja) * | 1995-10-26 | 1997-05-16 | Matsushita Electric Ind Co Ltd | プリント基板 |
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JP2956363B2 (ja) * | 1992-07-24 | 1999-10-04 | 富士電機株式会社 | パワー半導体装置 |
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- 2001-04-02 EP EP01917796A patent/EP1376695A4/en not_active Withdrawn
- 2001-04-02 US US10/276,291 patent/US6717258B2/en not_active Expired - Fee Related
- 2001-04-02 JP JP2002565154A patent/JPWO2002082542A1/ja active Pending
- 2001-04-02 WO PCT/JP2001/002876 patent/WO2002082542A1/ja active Application Filing
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EP0772235A2 (en) * | 1995-10-25 | 1997-05-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device comprising a circuit substrate and a case |
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JPH09312376A (ja) * | 1996-05-21 | 1997-12-02 | Fuji Electric Co Ltd | 半導体装置 |
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KR101098399B1 (ko) | 2008-06-20 | 2011-12-26 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 |
JP2015135891A (ja) * | 2014-01-17 | 2015-07-27 | 株式会社豊田自動織機 | 半導体装置 |
US9756729B2 (en) | 2014-01-17 | 2017-09-05 | Kabushiki Kaisha Toyota Jidoshokki | Semiconductor device having a first circuit board mounted with a plurality of semiconductor elements and a second circuit board mounted with a plurality of electronic components |
JP2017011926A (ja) * | 2015-06-24 | 2017-01-12 | 富士電機株式会社 | 電力変換装置 |
Also Published As
Publication number | Publication date |
---|---|
EP1376695A4 (en) | 2009-04-29 |
US20030168726A1 (en) | 2003-09-11 |
JPWO2002082542A1 (ja) | 2004-07-29 |
US6717258B2 (en) | 2004-04-06 |
EP1376695A1 (en) | 2004-01-02 |
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