CA2751034C - Semiconductor stack and power converter using the same - Google Patents
Semiconductor stack and power converter using the same Download PDFInfo
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- CA2751034C CA2751034C CA2751034A CA2751034A CA2751034C CA 2751034 C CA2751034 C CA 2751034C CA 2751034 A CA2751034 A CA 2751034A CA 2751034 A CA2751034 A CA 2751034A CA 2751034 C CA2751034 C CA 2751034C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 239000000758 substrate Substances 0.000 claims abstract description 119
- 239000003990 capacitor Substances 0.000 claims abstract description 54
- 239000004020 conductor Substances 0.000 claims abstract description 43
- 238000001816 cooling Methods 0.000 claims abstract description 12
- 238000010586 diagram Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
A semiconductor stack (1) has a multilayer substrate (2), a plurality of semiconductor modules (3), a plurality of electrolytic capacitors, a plurality of fuses (5) and a cooling fin (6). In the multilayer substrate (2), a P-phase conductor substrate (21), a C-phase conductor substrate (22) and an N-phase conductor substrate overlap each other, with insulating substrates (24b, 24c) in between. The semiconductor modules (3a-3h) are arranged in a row on the rear surface of the multilayer substrate (2). The electrolytic capacitors (4a-4m) are arranged in a row parallel to the row of the semiconductor module on the rear surface of the multilayer substrate (2). The fuses (5a-5m) are arranged on the front surface of the multilayer substrate (2).
Description
DESCRIPTION
SEMICONDUCTOR STACK AND POWER CONVERTER USING
THE SAME
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor stack and a power converter that uses the semiconductor stack for a three-phase AC electrical rotating machine.
BACKGROUND ART
SEMICONDUCTOR STACK AND POWER CONVERTER USING
THE SAME
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor stack and a power converter that uses the semiconductor stack for a three-phase AC electrical rotating machine.
BACKGROUND ART
[0002] A semiconductor stack used for a conventional power converter includes a multilayer substrate, a plurality of switching elements and electrolytic capacitors (See Patent Document 1, for example).
[0003] The multilayer substrate is made up of a positive electrode-side conductor substrate and a negative electrode-side conductor substrate, which are stacked via an insulating substrate. A positive electrode-side terminal and a negative electrode-side terminal of each switching element are connected to the positive electrode-side conductor substrate and the negative electrode-side conductor substrate of the multilayer substrate, respectively.
A positive electrode-side terminal and a negative electrode-side terminal of an electrolytic capacitor are connected to the positive electrode-side conductor substrate and the negative electrode-side conductor substrate of the multilayer substrate, respectively.
A positive electrode-side terminal and a negative electrode-side terminal of an electrolytic capacitor are connected to the positive electrode-side conductor substrate and the negative electrode-side conductor substrate of the multilayer substrate, respectively.
[0004] A plurality of switching elements are mounted in rows on a surface of the multilayer substrate in the vertical direction. Electrolytic capacitors are placed on lines extending from the rows of the switching elements.
PATENT DOCUMENT 1: Jpn. Pat. Appln. Laid-Open Publication No. 07-131981 DISCLOSURE OF THE INVENTION
PROBLEMS TO BE SOLVED BY THE INVENTION
PATENT DOCUMENT 1: Jpn. Pat. Appln. Laid-Open Publication No. 07-131981 DISCLOSURE OF THE INVENTION
PROBLEMS TO BE SOLVED BY THE INVENTION
[0005] On the above semiconductor stack, the electrolytic capacitors are disposed on lines extending from the rows of the switching elements.
However, the distances between the switching elements and the electrolytic capacitors are not equal. As a result, a large current flows through switching elements that are closer to an electrolytic capacitors, and the current between the switching elements becomes unbalanced.
MEANS FOR SOLVING THE PROBLEM
However, the distances between the switching elements and the electrolytic capacitors are not equal. As a result, a large current flows through switching elements that are closer to an electrolytic capacitors, and the current between the switching elements becomes unbalanced.
MEANS FOR SOLVING THE PROBLEM
[0006] In order to solve the problem, according to the present invention, there is provided a semiconductor stack, comprising: a multilayer substrate including a first conductor substrate, a second conductor substrate and a third conductor substrate, which respectively have a first electrode, a second electrode and a third electrode formed thereon and which are stacked via insulating substrates; a plurality of semiconductor modules that are disposed in rows on one surface of the multilayer substrate and are connected to the first electrode, the second electrode and the third electrode;
a plurality of first electrolytic capacitors that are disposed in a row on the one surface of the multilayer substrate so as to run parallel to the rows of a plurality of the semiconductor modules and are connected to the first electrode and the second electrode; a plurality of second electrolytic capacitors that are disposed so as to form the same row as a plurality of the first electrolytic capacitors on the one surface of the multilayer substrate and are connected to the second electrode and the third electrode; and a plurality of fuses that are disposed on other surface of the multilayer substrate and are each connected to the first electrode, the second electrode or the third electrode.
a plurality of first electrolytic capacitors that are disposed in a row on the one surface of the multilayer substrate so as to run parallel to the rows of a plurality of the semiconductor modules and are connected to the first electrode and the second electrode; a plurality of second electrolytic capacitors that are disposed so as to form the same row as a plurality of the first electrolytic capacitors on the one surface of the multilayer substrate and are connected to the second electrode and the third electrode; and a plurality of fuses that are disposed on other surface of the multilayer substrate and are each connected to the first electrode, the second electrode or the third electrode.
[0007] In order to solve the problem, according to the present invention, there is also provided a power converter for a three-phase AC electrical rotating machine, comprising: a multilayer substrate including a first conductor substrate, a second conductor substrate and a third conductor substrate, which respectively have a first electrode, a second electrode and a third electrode formed thereon and which are stacked via insulating substrates; a plurality of semiconductor modules that are disposed in rows on one surface of the multilayer substrate and are connected to the first electrode, the second electrode and the third electrode; a plurality of first electrolytic capacitors that are disposed in a row on the one surface of the multilayer substrate so as to run parallel to the rows of a plurality of the semiconductor modules and are connected to the first electrode and the second electrode; a plurality of second electrolytic capacitors that are disposed so as to form the same row as a plurality of the first electrolytic capacitors on the one surface of the multilayer substrate and are connected to the second electrode and the third electrode; and a plurality of fuses that are disposed on the other surface of the multilayer substrate and are each connected to the first electrode, the second electrode or the third electrode.
ADVANTAGE OF THE INVENTION
ADVANTAGE OF THE INVENTION
[0008] According to the semiconductor stack of the present invention, it is possible to improve the balance of current between semiconductor modules.
BRIEF DESCRIPTION OF THE DRAWINGS
BRIEF DESCRIPTION OF THE DRAWINGS
[0009]
[FIG. 11 FIG. 1 is a front perspective view of a semiconductor stack according to a first embodiment of the present invention.
[FIG. 2] FIG. 2 is an exploded perspective view of a multilayer substrate of the semiconductor stack according to the first embodiment of the present invention.
[FIG. 3] FIG. 3 is a perspective view of the multilayer substrate of the semiconductor stack according to the first embodiment of the present invention.
[FIG. 4] FIG. 4 is a diagram showing a portion of the circuit configuration of the semiconductor stack according to the first embodiment of the present invention.
EXPLANTAION OF NUMERALS
[FIG. 11 FIG. 1 is a front perspective view of a semiconductor stack according to a first embodiment of the present invention.
[FIG. 2] FIG. 2 is an exploded perspective view of a multilayer substrate of the semiconductor stack according to the first embodiment of the present invention.
[FIG. 3] FIG. 3 is a perspective view of the multilayer substrate of the semiconductor stack according to the first embodiment of the present invention.
[FIG. 4] FIG. 4 is a diagram showing a portion of the circuit configuration of the semiconductor stack according to the first embodiment of the present invention.
EXPLANTAION OF NUMERALS
[0010]
1: semiconductor stack; 2: multilayer substrate; 3: semiconductor module;
4: electrolytic capacitor; 5: fuse; 6: cooling fin; 7: direct current-side electrode; 21: first conductor substrate; 22: second conductor substrate;
23: third conductor substrate; 24: insulating substrate; 25: connection hole; 26: long side direction of conductor stack; 27: short side direction of conductor stack BEST MODE EMBODIMENTS FOR CARRYING OUT THE
INVENTION
1: semiconductor stack; 2: multilayer substrate; 3: semiconductor module;
4: electrolytic capacitor; 5: fuse; 6: cooling fin; 7: direct current-side electrode; 21: first conductor substrate; 22: second conductor substrate;
23: third conductor substrate; 24: insulating substrate; 25: connection hole; 26: long side direction of conductor stack; 27: short side direction of conductor stack BEST MODE EMBODIMENTS FOR CARRYING OUT THE
INVENTION
[0011]
(First Embodiment) A semiconductor stack, which is used in a power converter for a three-phase AC electrical rotating machine, of a first embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 is a front perspective view of a semiconductor stack according to the present embodiment. FIG. 2 is an exploded perspective view of a multilayer substrate of the semiconductor stack according to the present embodiment.
FIG. 3 is a perspective view of the multilayer substrate of the semiconductor stack according to the present embodiment. FIG. 4 is a diagram showing a portion of the circuit configuration of the semiconductor stack according to the present embodiment.
(First Embodiment) A semiconductor stack, which is used in a power converter for a three-phase AC electrical rotating machine, of a first embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 is a front perspective view of a semiconductor stack according to the present embodiment. FIG. 2 is an exploded perspective view of a multilayer substrate of the semiconductor stack according to the present embodiment.
FIG. 3 is a perspective view of the multilayer substrate of the semiconductor stack according to the present embodiment. FIG. 4 is a diagram showing a portion of the circuit configuration of the semiconductor stack according to the present embodiment.
[0012] A semiconductor stack 1 of the present embodiment is made up of the following components mounted on a surface of a multilayer substrate 2:
semiconductor modules 3, electrolytic capacitors 4, fuses 5, and cooling fins 6.
semiconductor modules 3, electrolytic capacitors 4, fuses 5, and cooling fins 6.
[0013] First, the circuit configuration of the semiconductor stack 1 will be described with reference to FIG. 4.
[0014] Circuits of the semiconductor stack 1 are made up of eight semiconductor modules 3a to 3h, twelve electrolytic capacitors 4a to 4m, twelve fuses 5a to 5m, and three direct current-side electrodes 7 (a P-phase electrode 7a, a C-phase electrode 7b and an N-phase electrode 7c).
[0015] The semiconductor modules 3a and 3b are connected to the P-phase electrode 7a, the C-phase electrode 7b and the N-phase electrode 7c. The semiconductor modules 3a and 3b are connected in parallel to each other.
[0016] The electrolytic capacitors 4a to 4c are connected to the P-phase electrode 7a and the C-phase electrode 7b, and are connected in parallel to each other. The electrolytic capacitors 4d to 4f are connected to the C-phase electrode 7b and the N-phase electrode 7c, and are connected in parallel to each other.
[0017] The fuse 5a is connected in series to the P-phase electrode 7a. The fuse 5b is connected in series to the N-phase electrode 7c. The fuses 5a and 5b are provided to protect the semiconductor modules 3a and 3b. The fuses 5c and 5d are connected in series to the C-phase electrode 7b and are connected in parallel to each other. The fuses 5c and 5d are provided to protect the electrolytic capacitors 4d to 4f.
[0018] A circuit made up of the semiconductor modules 3c and 3d and the fuses 5e and 5f has a same structure as a circuit made up of the semiconductor modules 3a and 3b and the fuses 5c and 5d. Both circuits are connected in parallel to each other. The electrolytic capacitors 4a to 4f and the fuses 5a and 5b are shared by the semiconductor modules 3c and 3d and the fuses 5e and 5f, as well as by the semiconductor modules 3a and 3b and the fuses 5c and 5d.
[0019] A circuit made up of the semiconductor modules 3e to 3h, the electrolytic capacitors 4g to 4m and the fuses 5i to 5m has a same structure as a circuit made up of the semiconductor modules 3a to 3d, the electrolytic capacitors 4a to 4f and the fuses 5a to 5f. Both circuits are connected in parallel to each other.
[0020] With the above circuit configuration, the semiconductor modules 3a to 3h convert direct current from the P-phase electrode 7a, the C-phase electrode 7b and the N-phase electrode 7c into three-phase alternate current to output.
[0021] The following describes the configuration of the multilayer substrate 2 with reference to FIGS. 2 and 3.
[00221 The multilayer substrate 2 includes a first conductor substrate (P-phase conductor substrate) 21, on which a first electrode (P-phase electrode 7a) is formed; a second conductor substrate (C-phase conductor substrate) 22, on which a second electrode (C-phase electrode 7b) is formed; a third conductor substrate (N-phase conductor substrate) 23, on which a third electrode (N-phase electrode 7c) is formed; and four insulating substrates 24 (insulating substrates 24a to 24d).
[0023] The above substrates are stacked in the following order (from bottom to top in FIG. 2): the insulating substrate 24a, the N-phase conductor substrate 23, the insulating substrate 24b, the P-phase conductor substrate 21, the insulating substrate 24c, the C-phase conductor substrate 22, and the insulating substrate 24d. The multilayer substrate 2 is in the shape of a plate, whose surface is formed substantially into a rectangle.
[0024] Hole-drilling is performed to make a plurality of connection holes 25 at predetermined locations on the conductor substrates 21 to 23 and the insulating substrates 24a to 24d. Connection bolts (not shown) are inserted into the connection holes. Thanks to the connection bolts, the electrodes 7a to 7c are connected to each other electrically.
[0025] The following describes the mounting configuration of the semiconductor stack 1 with reference to FIG. 1.
[0026] The semiconductor modules 3a to 3h are substantially in the shape of a rectangular plate. The semiconductor modules 3a to 3h each have a P-phase-side terminal, a C-phase-side terminal, an N-phase-side terminal and an AC (Alternate Current)-side terminal on one side portion of a long side thereof.
[0027] The semiconductor modules 3a to 3h are disposed on the insulating substrate 24a-side surface of the multilayer substrate 2 (referred to as "back surface of the multilayer substrate 2", hereinafter) in such a way that the semiconductor modules 3a to 3d face the semiconductor modules 3e to 3h.
[0028] The semiconductor modules 3a to 3d are sequentially placed in a line along a long side of the multilayer substrate 2 so that only the side portions on which the terminals are provided are put on one side portion of a short side of the back surface of the multilayer substrate 2.
[0029] The semiconductor modules 3e to 3h are sequentially placed in a line along a long side of the multilayer substrate 2 so that only the side portions on which the terminals are provided are put on the other side portion (i.e., the side portion that is on the opposite side of the multilayer substrate 2 from the side portion on which the semiconductor modules 3a to 3h are disposed) of the short side of the back surface of the multilayer substrate 2.
[0030] On the side portions of the short sides of the multilayer substrate 2, a plurality of connection holes 25 are made by countersunk-hole punching at locations corresponding to the terminals of the semiconductor modules 3a to 3h. The P-phase-side terminals and P-phase electrodes 7a of the semiconductor modules 3a to 3h, the C-phase-side terminals and the C-phase electrodes 7b, and the N-phase-side terminals and the N-phase electrodes 7c are connected to the connection holes 25.
[0031] Four cooling fins 6a to 6d are provided on surfaces (referred to as "back surfaces of the semiconductor modules 3", hereinafter) opposite to the multilayer substrate 2-side surfaces of the semiconductor modules 3a to 3h (referred to as "front surfaces of the semiconductor modules 3", hereinafter).
[0032] The cooling fins 6a to 6d are placed so that the direction of cooling air, which passes through the cooling fins 6a to 6d, is a direction perpendicular to the rows of the semiconductor modules 3 (i.e., the direction of a short side of the multilayer substrate 2).
[0033] The electrolytic capacitors 4a to 4m each have a cylindrical portion 41 and two terminals, which are provided at one end of the cylindrical portion 41. The electrolytic capacitors 4a to 4c and 4g to 4i each have a P-phase-side terminal and a C-phase-side terminal. Meanwhile, the electrolytic capacitors 4d to 4f and 4j to 4m each have a C-phase-side terminal and an N-phase-side terminal.
[0034] The electrolytic capacitors 4a to 4f and the electrolytic capacitors 4g to 4m face each other and are disposed so as to rise on the back surface of the multilayer substrate 2.
[0035] The electrolytic capacitors 4a to 4f and the electrolytic capacitors 4g to 4m are sequentially placed and arranged in two lines at a central portion of the short sides of the multilayer substrate 2 so as to go along the long sides of the multilayer substrate 2.
[0036] The electrolytic capacitors 4a to 4f and the semiconductor modules 3a to 3d lie side by side; the electrolytic capacitors 4g to 4m and the semiconductor modules 3e to 3h lie side by side.
[0037] At the central portion of the short sides of the multilayer substrate 2, a plurality of connection holes 25 are made by countersunk- hole punching at positions corresponding to the terminals of the electrolytic capacitors 4a to 4c and 4g to 4i. The P-phase-side terminals and the C-phase-side terminals of the electrolytic capacitors 4a to 4c and 4g to 4i are connected to the P-phase-side electrode 7a and the C-phase electrode 7b, respectively, through the connection holes 25.
[0038] At the central portion of the short sides of the multilayer substrate 2, connection holes 25 are made at positions corresponding to the terminals of the electrolytic capacitors 4d to 4f and 4j to 4m. The N-phase-side terminals and the C-phase-side terminals of the electrolytic capacitors 4d to 4f and 4j to 4m are connected to the N-phase electrodes 7c and the C-phase electrodes 7b, respectively, through the connection holes 25.
[0039] The fuses 5a to 5m are substantially in the shape of a rectangular parallelepiped, and each have two terminals. The fuses 5a and 5g each have two P-phase-side terminals. The fuses 5b and 5h each have two P-phase-side terminals. The fuses 5c to 5f and 5i to 5m each have two C-phase-side terminals.
[0040] The fuses 5a to 5f and the fuses 5g to 5m face each other and are disposed on a surface (referred to as "front surface of the multilayer substrate 2", hereinafter) opposite to the back surface of the multilayer substrate 2).
[0041] The fuses 5a, 5c to 5f and 5b are sequentially placed and arranged in one line on the front surface of the multilayer substrate 2 so as to go along the long sides of the multilayer substrate 2 and be disposed between the semiconductor modules 3a to 3d and the electrolytic capacitors 4a to 4f.
[0042] Meanwhile, the fuses 5g, 5i to 5m and 5h are sequentially placed and arranged in one line on the front surface of the multilayer substrate 2 so as to go along the long sides of the multilayer substrate 2 and be disposed between the semiconductor modules 3e to 3h and the electrolytic capacitors 4g to 4m.
[0043] At positions corresponding to the terminals of the fuses 5a to 5m on the multilayer substrate 2, connection holes 25 are provided and brazed.
The P-phase terminals of the fuses 5a and 5g are connected to the P-phase-side electrode 7a. The N-phase terminals of the fuses 5b and 5h are connected to the N-phase-side electrode 7c. The C-phase terminals of the fuses 5c to 5f and of the fuses 5i to 5m are connected to the C-phase-side electrode 7b.
[0044] The semiconductor stack 1 is for example used for a power converter for a three-phase AC electrical rotating machine (not shown).
[0045] In such a case, the semiconductor stack 1 is installed in a housing of the power converter. The semiconductor stack 1 is placed in such a way that the front surface of the multilayer substrate 2 faces a front surface of the housing of the power converter.
[0046] The following describes advantageous effects of the semiconductor stack 1 of the present embodiment.
[0047] According to the present embodiment, the semiconductor modules 3a to 3d and the electrolytic capacitors 4a to 4f are disposed so as to run parallel to each other. Therefore, the wiring distances between the semiconductor modules 3a to 3d and the electrolytic capacitors 4a to 4f substantially become equal. Similarly, the wiring distances between the semiconductor modules 3e to 3h and the electrolytic capacitors 4g to 4m substantially become equal.
Thus, the balance of current between the semiconductor modules 3a to 3h is improved.
[0048] Moreover, according to the present embodiment, the conductors 7a to 7c, which are each used to connect the semiconductor modules 3 and the electrolytic capacitors 4, are stacked, thereby minimizing the distances between the conductors 7a to 7c. Therefore, it is possible to minimize the wiring inductance of each of the conductors 7a to 7c and prevent a surge in the voltage of the semiconductor modules 3.
[0049] Moreover, according to the present embodiment, on the flat surface of the multilayer conductor 2, the semiconductor modules 3, the electrolytic capacitors 4 and the fuses 5 are mounted. Therefore, it is easy to do maintenance and replace the semiconductor modules 3, the electrolytic capacitors 4 and the fuses 5, which frequently break down.
[0050] Furthermore, according to the present embodiment, the plate-like semiconductor modules 3 are disposed in such a way that only the side portions on which the terminals thereof are provided are put on the multilayer substrate 2. Therefore, the heat dissipating performance of the semiconductor modules 3 is improved. Moreover, the direction of the cooling air passing through the cooling fins 6 is the same as the direction of the short sides of the multilayer substrate 2. Therefore, it is possible to cool the semiconductor modules 3 and the electrolytic capacitors 3 at the same time.
[0051]
(Other Embodiments) The above-described embodiment is given for illustrative purposes only. The present invention is not limited to the above-described embodiment.
[0052] The number of semiconductor modules 3, the number of electrolytic capacitors 4, and the number of fuses 5 are not limited to those of the above-described embodiment. For example, in the case of a smaller semiconductor stack than the semiconductor stack 1 of the first embodiment, four semiconductor modules (3a to 3d), six electrolytic capacitors (4a to 41), and four fuses (5a to 51) may be provided.
[0053] Moreover, the order that the first conductor substrate 21, the second conductor substrate 22 and the third conductor substrate 23 are stacked is not limited to that of the above-described embodiment.
[0054] Furthermore, the electrical connection between the electrodes 7a to 7c, as well as of the electrodes 7a to 7c to the semiconductor modules 3 or the like, can be achieved not only by connection bolts but also by copper wires, solder, brazing or the like.
[00221 The multilayer substrate 2 includes a first conductor substrate (P-phase conductor substrate) 21, on which a first electrode (P-phase electrode 7a) is formed; a second conductor substrate (C-phase conductor substrate) 22, on which a second electrode (C-phase electrode 7b) is formed; a third conductor substrate (N-phase conductor substrate) 23, on which a third electrode (N-phase electrode 7c) is formed; and four insulating substrates 24 (insulating substrates 24a to 24d).
[0023] The above substrates are stacked in the following order (from bottom to top in FIG. 2): the insulating substrate 24a, the N-phase conductor substrate 23, the insulating substrate 24b, the P-phase conductor substrate 21, the insulating substrate 24c, the C-phase conductor substrate 22, and the insulating substrate 24d. The multilayer substrate 2 is in the shape of a plate, whose surface is formed substantially into a rectangle.
[0024] Hole-drilling is performed to make a plurality of connection holes 25 at predetermined locations on the conductor substrates 21 to 23 and the insulating substrates 24a to 24d. Connection bolts (not shown) are inserted into the connection holes. Thanks to the connection bolts, the electrodes 7a to 7c are connected to each other electrically.
[0025] The following describes the mounting configuration of the semiconductor stack 1 with reference to FIG. 1.
[0026] The semiconductor modules 3a to 3h are substantially in the shape of a rectangular plate. The semiconductor modules 3a to 3h each have a P-phase-side terminal, a C-phase-side terminal, an N-phase-side terminal and an AC (Alternate Current)-side terminal on one side portion of a long side thereof.
[0027] The semiconductor modules 3a to 3h are disposed on the insulating substrate 24a-side surface of the multilayer substrate 2 (referred to as "back surface of the multilayer substrate 2", hereinafter) in such a way that the semiconductor modules 3a to 3d face the semiconductor modules 3e to 3h.
[0028] The semiconductor modules 3a to 3d are sequentially placed in a line along a long side of the multilayer substrate 2 so that only the side portions on which the terminals are provided are put on one side portion of a short side of the back surface of the multilayer substrate 2.
[0029] The semiconductor modules 3e to 3h are sequentially placed in a line along a long side of the multilayer substrate 2 so that only the side portions on which the terminals are provided are put on the other side portion (i.e., the side portion that is on the opposite side of the multilayer substrate 2 from the side portion on which the semiconductor modules 3a to 3h are disposed) of the short side of the back surface of the multilayer substrate 2.
[0030] On the side portions of the short sides of the multilayer substrate 2, a plurality of connection holes 25 are made by countersunk-hole punching at locations corresponding to the terminals of the semiconductor modules 3a to 3h. The P-phase-side terminals and P-phase electrodes 7a of the semiconductor modules 3a to 3h, the C-phase-side terminals and the C-phase electrodes 7b, and the N-phase-side terminals and the N-phase electrodes 7c are connected to the connection holes 25.
[0031] Four cooling fins 6a to 6d are provided on surfaces (referred to as "back surfaces of the semiconductor modules 3", hereinafter) opposite to the multilayer substrate 2-side surfaces of the semiconductor modules 3a to 3h (referred to as "front surfaces of the semiconductor modules 3", hereinafter).
[0032] The cooling fins 6a to 6d are placed so that the direction of cooling air, which passes through the cooling fins 6a to 6d, is a direction perpendicular to the rows of the semiconductor modules 3 (i.e., the direction of a short side of the multilayer substrate 2).
[0033] The electrolytic capacitors 4a to 4m each have a cylindrical portion 41 and two terminals, which are provided at one end of the cylindrical portion 41. The electrolytic capacitors 4a to 4c and 4g to 4i each have a P-phase-side terminal and a C-phase-side terminal. Meanwhile, the electrolytic capacitors 4d to 4f and 4j to 4m each have a C-phase-side terminal and an N-phase-side terminal.
[0034] The electrolytic capacitors 4a to 4f and the electrolytic capacitors 4g to 4m face each other and are disposed so as to rise on the back surface of the multilayer substrate 2.
[0035] The electrolytic capacitors 4a to 4f and the electrolytic capacitors 4g to 4m are sequentially placed and arranged in two lines at a central portion of the short sides of the multilayer substrate 2 so as to go along the long sides of the multilayer substrate 2.
[0036] The electrolytic capacitors 4a to 4f and the semiconductor modules 3a to 3d lie side by side; the electrolytic capacitors 4g to 4m and the semiconductor modules 3e to 3h lie side by side.
[0037] At the central portion of the short sides of the multilayer substrate 2, a plurality of connection holes 25 are made by countersunk- hole punching at positions corresponding to the terminals of the electrolytic capacitors 4a to 4c and 4g to 4i. The P-phase-side terminals and the C-phase-side terminals of the electrolytic capacitors 4a to 4c and 4g to 4i are connected to the P-phase-side electrode 7a and the C-phase electrode 7b, respectively, through the connection holes 25.
[0038] At the central portion of the short sides of the multilayer substrate 2, connection holes 25 are made at positions corresponding to the terminals of the electrolytic capacitors 4d to 4f and 4j to 4m. The N-phase-side terminals and the C-phase-side terminals of the electrolytic capacitors 4d to 4f and 4j to 4m are connected to the N-phase electrodes 7c and the C-phase electrodes 7b, respectively, through the connection holes 25.
[0039] The fuses 5a to 5m are substantially in the shape of a rectangular parallelepiped, and each have two terminals. The fuses 5a and 5g each have two P-phase-side terminals. The fuses 5b and 5h each have two P-phase-side terminals. The fuses 5c to 5f and 5i to 5m each have two C-phase-side terminals.
[0040] The fuses 5a to 5f and the fuses 5g to 5m face each other and are disposed on a surface (referred to as "front surface of the multilayer substrate 2", hereinafter) opposite to the back surface of the multilayer substrate 2).
[0041] The fuses 5a, 5c to 5f and 5b are sequentially placed and arranged in one line on the front surface of the multilayer substrate 2 so as to go along the long sides of the multilayer substrate 2 and be disposed between the semiconductor modules 3a to 3d and the electrolytic capacitors 4a to 4f.
[0042] Meanwhile, the fuses 5g, 5i to 5m and 5h are sequentially placed and arranged in one line on the front surface of the multilayer substrate 2 so as to go along the long sides of the multilayer substrate 2 and be disposed between the semiconductor modules 3e to 3h and the electrolytic capacitors 4g to 4m.
[0043] At positions corresponding to the terminals of the fuses 5a to 5m on the multilayer substrate 2, connection holes 25 are provided and brazed.
The P-phase terminals of the fuses 5a and 5g are connected to the P-phase-side electrode 7a. The N-phase terminals of the fuses 5b and 5h are connected to the N-phase-side electrode 7c. The C-phase terminals of the fuses 5c to 5f and of the fuses 5i to 5m are connected to the C-phase-side electrode 7b.
[0044] The semiconductor stack 1 is for example used for a power converter for a three-phase AC electrical rotating machine (not shown).
[0045] In such a case, the semiconductor stack 1 is installed in a housing of the power converter. The semiconductor stack 1 is placed in such a way that the front surface of the multilayer substrate 2 faces a front surface of the housing of the power converter.
[0046] The following describes advantageous effects of the semiconductor stack 1 of the present embodiment.
[0047] According to the present embodiment, the semiconductor modules 3a to 3d and the electrolytic capacitors 4a to 4f are disposed so as to run parallel to each other. Therefore, the wiring distances between the semiconductor modules 3a to 3d and the electrolytic capacitors 4a to 4f substantially become equal. Similarly, the wiring distances between the semiconductor modules 3e to 3h and the electrolytic capacitors 4g to 4m substantially become equal.
Thus, the balance of current between the semiconductor modules 3a to 3h is improved.
[0048] Moreover, according to the present embodiment, the conductors 7a to 7c, which are each used to connect the semiconductor modules 3 and the electrolytic capacitors 4, are stacked, thereby minimizing the distances between the conductors 7a to 7c. Therefore, it is possible to minimize the wiring inductance of each of the conductors 7a to 7c and prevent a surge in the voltage of the semiconductor modules 3.
[0049] Moreover, according to the present embodiment, on the flat surface of the multilayer conductor 2, the semiconductor modules 3, the electrolytic capacitors 4 and the fuses 5 are mounted. Therefore, it is easy to do maintenance and replace the semiconductor modules 3, the electrolytic capacitors 4 and the fuses 5, which frequently break down.
[0050] Furthermore, according to the present embodiment, the plate-like semiconductor modules 3 are disposed in such a way that only the side portions on which the terminals thereof are provided are put on the multilayer substrate 2. Therefore, the heat dissipating performance of the semiconductor modules 3 is improved. Moreover, the direction of the cooling air passing through the cooling fins 6 is the same as the direction of the short sides of the multilayer substrate 2. Therefore, it is possible to cool the semiconductor modules 3 and the electrolytic capacitors 3 at the same time.
[0051]
(Other Embodiments) The above-described embodiment is given for illustrative purposes only. The present invention is not limited to the above-described embodiment.
[0052] The number of semiconductor modules 3, the number of electrolytic capacitors 4, and the number of fuses 5 are not limited to those of the above-described embodiment. For example, in the case of a smaller semiconductor stack than the semiconductor stack 1 of the first embodiment, four semiconductor modules (3a to 3d), six electrolytic capacitors (4a to 41), and four fuses (5a to 51) may be provided.
[0053] Moreover, the order that the first conductor substrate 21, the second conductor substrate 22 and the third conductor substrate 23 are stacked is not limited to that of the above-described embodiment.
[0054] Furthermore, the electrical connection between the electrodes 7a to 7c, as well as of the electrodes 7a to 7c to the semiconductor modules 3 or the like, can be achieved not only by connection bolts but also by copper wires, solder, brazing or the like.
Claims (5)
1. A semiconductor stack, comprising:
a multilayer substrate including a first conductor substrate, a second conductor substrate and a third conductor substrate, which respectively have a first electrode, a second electrode and a third electrode formed thereon and which are stacked via insulating substrates;
a plurality of semiconductor modules that are disposed in rows on one surface of the multilayer substrate and are connected to the first electrode, the second electrode and the third electrode;
a plurality of first electrolytic capacitors that are disposed in a row on the one surface of the multilayer substrate so as to run parallel to the rows of the plurality of the semiconductor modules and are connected to the first electrode and the second electrode;
a plurality of second electtolytic capacitors that are disposed so as to form the same row as the plurality of first electrolytic capacitors on the one surface of the multilayer substrate and are connected to the second electrode and the third electrode; and a plurality of fuses that are disposed on other surface of the multilayer substrate and are each connected to the first electrode, the second electrode or the third electrode.
a multilayer substrate including a first conductor substrate, a second conductor substrate and a third conductor substrate, which respectively have a first electrode, a second electrode and a third electrode formed thereon and which are stacked via insulating substrates;
a plurality of semiconductor modules that are disposed in rows on one surface of the multilayer substrate and are connected to the first electrode, the second electrode and the third electrode;
a plurality of first electrolytic capacitors that are disposed in a row on the one surface of the multilayer substrate so as to run parallel to the rows of the plurality of the semiconductor modules and are connected to the first electrode and the second electrode;
a plurality of second electtolytic capacitors that are disposed so as to form the same row as the plurality of first electrolytic capacitors on the one surface of the multilayer substrate and are connected to the second electrode and the third electrode; and a plurality of fuses that are disposed on other surface of the multilayer substrate and are each connected to the first electrode, the second electrode or the third electrode.
2. The semiconductor stack according to claim 1, wherein the plurality of semiconductor modules are disposed in two parallel rows, and the rows of the plurality of electrolytic capacitors are placed in a central portion between the two rows of the plurality of semiconductor modules.
3. The semiconductor stack according to claim 1 or 2, wherein the plurality of semiconductor modules are in a shape of a plate and are so disposed that one plate surface of each of the semiconductor modules is partially placed on the multilayer substrate.
4. The semiconductor stack according to claim 3, comprising cooling fins that are disposed on the plurality of semiconductor modules, the cooling fins each being disposed on a surface, which is further from the multilayer substrate, of the plurality of semiconductor modules in such a way that a direction of cooling air passing therethrough is a direction perpendicular to the rows of the semiconductor modules.
5. A power converter for a three-phase AC electrical rotating machine, comprising:
a multilayer substrate including a first conductor substrate, a second conductor substrate and a third conductor substrate, which respectively have a first electrode, a second electrode and a third electrode formed thereon and which are stacked via insulating substrates;
a plurality of semiconductor modules that are disposed in rows on one surface of the multilayer substrate and are connected to the first electrode, the second electrode and the third electrode;
a plurality of first electrolytic capacitors that are disposed in a row on the one surface of the multilayer substrate so as to run parallel to the rows of the plurality of the semiconductor modules and are connected to the first electrode and the second electrode;
a plurality of second electrolytic capacitors that are disposed so as to form the same row as a the plurality of first electrolytic capacitors on the one surface of the multilayer substrate and are connected to the second electrode and the third electrode; and a plurality of fuses that are disposed on an other surface of the multilayer substrate and are each connected to the first electrode, the second electrode or the third electrode.
a multilayer substrate including a first conductor substrate, a second conductor substrate and a third conductor substrate, which respectively have a first electrode, a second electrode and a third electrode formed thereon and which are stacked via insulating substrates;
a plurality of semiconductor modules that are disposed in rows on one surface of the multilayer substrate and are connected to the first electrode, the second electrode and the third electrode;
a plurality of first electrolytic capacitors that are disposed in a row on the one surface of the multilayer substrate so as to run parallel to the rows of the plurality of the semiconductor modules and are connected to the first electrode and the second electrode;
a plurality of second electrolytic capacitors that are disposed so as to form the same row as a the plurality of first electrolytic capacitors on the one surface of the multilayer substrate and are connected to the second electrode and the third electrode; and a plurality of fuses that are disposed on an other surface of the multilayer substrate and are each connected to the first electrode, the second electrode or the third electrode.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2009/000779 WO2010097830A1 (en) | 2009-02-24 | 2009-02-24 | Semiconductor stack and power converter using the same |
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| CA2751034A1 CA2751034A1 (en) | 2010-09-02 |
| CA2751034C true CA2751034C (en) | 2015-02-17 |
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| CA2751034A Active CA2751034C (en) | 2009-02-24 | 2009-02-24 | Semiconductor stack and power converter using the same |
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| Country | Link |
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| JP (1) | JP5438752B2 (en) |
| KR (1) | KR101189017B1 (en) |
| CN (1) | CN102326326B (en) |
| CA (1) | CA2751034C (en) |
| MX (1) | MX2011008610A (en) |
| WO (1) | WO2010097830A1 (en) |
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| WO2014057622A1 (en) * | 2012-10-09 | 2014-04-17 | 富士電機株式会社 | Power converter |
| WO2015145679A1 (en) | 2014-03-27 | 2015-10-01 | 株式会社日立製作所 | Power conversion unit, power conversion apparatus, and power conversion apparatus manufacturing method |
| JP5778840B1 (en) | 2014-09-25 | 2015-09-16 | 株式会社日立製作所 | Power conversion unit and power conversion device |
| JP5894321B1 (en) * | 2015-07-09 | 2016-03-30 | 株式会社日立製作所 | Power conversion unit and power conversion device |
| JP6617492B2 (en) * | 2015-09-16 | 2019-12-11 | 株式会社デンソー | Power converter |
| JP6474751B2 (en) * | 2016-03-29 | 2019-02-27 | 東芝三菱電機産業システム株式会社 | Cell inverter unit |
| JP6504622B2 (en) * | 2017-06-14 | 2019-04-24 | 三菱電機株式会社 | Capacitor substrate unit for open / close module, open / close module, and motor drive device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH07245951A (en) * | 1994-03-07 | 1995-09-19 | Toshiba Corp | Semiconductor stack |
| JPH1127930A (en) | 1997-07-07 | 1999-01-29 | Toshiba Corp | Power converter device and power converter system |
| JP3648417B2 (en) * | 1999-12-09 | 2005-05-18 | 株式会社東芝 | Power semiconductor module and power conversion device |
| JP4567405B2 (en) * | 2004-09-16 | 2010-10-20 | 東芝三菱電機産業システム株式会社 | Power converter |
-
2009
- 2009-02-24 KR KR1020117018084A patent/KR101189017B1/en active IP Right Grant
- 2009-02-24 CA CA2751034A patent/CA2751034C/en active Active
- 2009-02-24 WO PCT/JP2009/000779 patent/WO2010097830A1/en active Application Filing
- 2009-02-24 MX MX2011008610A patent/MX2011008610A/en active IP Right Grant
- 2009-02-24 CN CN200980157677.3A patent/CN102326326B/en active Active
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| KR101189017B1 (en) | 2012-10-08 |
| KR20110111459A (en) | 2011-10-11 |
| WO2010097830A1 (en) | 2010-09-02 |
| CN102326326B (en) | 2014-03-26 |
| JPWO2010097830A1 (en) | 2012-08-30 |
| CA2751034A1 (en) | 2010-09-02 |
| CN102326326A (en) | 2012-01-18 |
| MX2011008610A (en) | 2011-09-09 |
| JP5438752B2 (en) | 2014-03-12 |
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