WO2002067456A1 - Regulateur automatique de frequence - Google Patents

Regulateur automatique de frequence Download PDF

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Publication number
WO2002067456A1
WO2002067456A1 PCT/JP2001/001148 JP0101148W WO02067456A1 WO 2002067456 A1 WO2002067456 A1 WO 2002067456A1 JP 0101148 W JP0101148 W JP 0101148W WO 02067456 A1 WO02067456 A1 WO 02067456A1
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WIPO (PCT)
Prior art keywords
signal
frequency
clock frequency
clock
unit
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Application number
PCT/JP2001/001148
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English (en)
Japanese (ja)
Inventor
Tetsuya Kikuchi
Original Assignee
Fujitsu Limited
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Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2001/001148 priority Critical patent/WO2002067456A1/fr
Publication of WO2002067456A1 publication Critical patent/WO2002067456A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7085—Synchronisation aspects using a code tracking loop, e.g. a delay-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/02—Automatic frequency control

Definitions

  • the present invention relates to an AFC controller in a CDMA mobile communication terminal in which a known fixed pattern (pilot) is arranged in a lower signal from a base station.
  • AFC control device capable of shortening the initial frequency pull-in time of AFC control at a time and reducing current consumption, and a CDMA mobile communication terminal equipped with the AFC control device.
  • the transmitting side spreads the transmission information using a spreading code string and transmits it, and the receiving side transmits the signal received from the transmitting side.
  • the transmission information is demodulated by despreading using the same despreading code sequence as that of the transmitting side.
  • FIG. 9 is a configuration diagram of a CDMA receiver.
  • the radio unit 1 converts the frequency of the high-frequency signal received by the antenna ATN to a baseband signal (RF ⁇ IF conversion), and the quadrature detector 2 performs quadrature detection of the baseband signal, and outputs in-phase component (I component) data. Outputs quadrature component (Q component) data.
  • 2a is a received carrier generator
  • 2b is a phase shifter that shifts the phase of the received carrier by ⁇ / 2
  • 2c and 2d are multipliers that convert the received carrier to a respread span signal. It multiplies and outputs an I component signal and a Q component signal.
  • the low-pass filters (LPF) 3a and 3b limit the band of the output signal, and the AD converters 4a and 4b convert the I component signal and the Q component signal into digital signals, respectively.
  • the searcher 5 performs a correlation operation using a matched filter (not shown) to detect the multipath, and starts despreading in each path.
  • 3 and delay time adjustment data timing data tau 0 ⁇ Te is input to the finger section 6 i to 6 4.
  • Despreading code generation section 6a of each finger portion 6 i to 6 4 is Te timing data inputting identical code sequence and spreading code sequence on the transmitting side from the searcher 5.
  • the searcher 5 detects the phase of the transmission-side spread code with an accuracy within one chip (synchronous acquisition), and the despread code generator 6a A spreading code sequence for despreading at the receiving side is generated in synchronization with the phase.
  • the DLL (Delayed Locked Loop) circuit 61) detects the time difference between the received signal and the despread code sequence on the receiving side, even if the phase of the received signal changes due to modulation or noise. Control so that it does not happen (synchronous tracking).
  • the despreading Z delay time adjusting unit 6c performs a despreading process on the direct wave or the delayed wave arriving via a predetermined path using the same code as the spreading code to perform dump integration, and then delays according to the path. Performs processing and outputs pilot signal and information signal. At the time of communication, a pilot signal is inserted into a predetermined bit position of each time slot of the lower signal from the base station.
  • the phase compensator 6d performs AFC (Automatic Frequency Control) control and calculates the rotation angle ⁇ 0 on the I-jQ plane of the pilot signal included in the received signal. Output sin component.
  • Synchronous detector 6e is cos A 0, despread information signals using sinA 0, Q; undo phase. That is, the pilot signal undergoes phase rotation during transmission due to the effects of fading, temperature change, multipath, etc., but if the signal point position vector PACT (see Fig. 10) is known on the receiving side, the ideal signal of the Pipit symbol is obtained. Since the point position vector P IDL is known, the phase rotation angle ⁇ ⁇ ⁇ ⁇ of the symbol due to transmission can be obtained. Thus, the phase compensator 6d detects the pilot symbol and calculates the phase rotation angle ⁇ ⁇ , and the synchronous detector 6e uses cos ⁇ ⁇ and sinA ⁇
  • the received information signal ( ⁇ ', Q') is subjected to phase rotation processing to return to the original state, and then the received information signal (1, Q) is demodulated (synchronous detection).
  • RAKE combining section 7 you output error correction decoder as soft decision data string by synthesizing the signals output from each finger portion 6-6 4.
  • the erroneous correction decoder 8 performs erroneous correction processing to decode and output transmission information.
  • Figure 11 is an explanatory diagram of the matched filter that constitutes Searcher 5-5a is a matched filter that performs a correlation operation between the received spread data sequence of the base span and the base station spreading code, and 5b is the timing identification. Section of the correlation value output from the matched filter.
  • the base station identifies the base timing as the base station's spread start timing, that is, the base station's reference timing.
  • 51 b is a base station base station.
  • An N-chip register ( C 1 to C N ) in which a spreading code (for example, a spreading code for timing identification) is set, 51 c is a base-band spreading data sequence and a corresponding bit of a base station spreading code sequence N multipliers (MPi MPw :) for multiplying by, and 51 d are adders for adding the outputs of the respective multipliers.
  • a spreading code for example, a spreading code for timing identification
  • 51 c is a base-band spreading data sequence and a corresponding bit of a base station spreading code sequence N multipliers (MPi MPw :) for multiplying by
  • 51 d are adders for adding the outputs of the respective multipliers.
  • the matched filter 5a outputs one correlation value R (t) per one chip period, and thereafter sequentially outputs correlation values having different phases according to one chip period Tc, and outputs N correlation values in one symbol period. Output different correlation values.
  • the timing identification unit 5b monitors the correlation value R (t) output from the adder 51d and checks whether the correlation value has become larger than the set level. , Ie, the reference timing of the base station. At the beginning of each time slot of the lower signal transmitted from the base station, a timing identification pattern (spread with a timing identification spreading code) is arranged. When the power is turned on or when the mobile station returns to the service area from outside the service area, the spread code for timing identification is set in the register 51b of the matched filter 5a as the base station spread code. As a result, the output R (t) of the adder 51d indicates a peak when the base station sets the spreading code for retiming identification in the shift register 51a.
  • FIG. 12 is an explanatory diagram for explaining such a situation.
  • (1) shows a lower signal frame (broadcast channel frame), and (2) shows a time slot configuration.
  • One frame is 10 msec and consists of 15 time slots.
  • 1 timeslot is 1 0 symposium Le, leading first bit portion timing identification pattern of 1 timeslot, 2 second to sixth bit unit data unit D 0 to D 5, seventh to 3 1 0 bit portion is a fixed pattern portion for data demodulation (the pilot) P 0 to P 4.
  • the spreading factor is 256
  • a signal obtained by spreading and modulating the first bit data of the time slot with the 256 timing identification spreading code becomes a timing identification pattern and arrives at the matched filter 5a for each time slot.
  • the despreading unit 6c will thereafter synchronize with the phase of the spreading code on the receiving side. Generates a despreading code sequence for despreading, and performs despreading. DLL circuit 61) ensures that even if the phase of the received signal changes due to the influence of modulation, noise, etc., the despreading code sequence on the receiving side does not cause a time lag with respect to the received signal once successfully acquired. Control (synchronous tracking).
  • FIG. 13 is a configuration diagram of a DLL circuit, 6a is a despread code generator, and 61) is a DLL circuit.
  • 6a-2 is a voltage controlled oscillator (VC0) that varies the clock frequency (chip frequency) based on the DLL circuit output (DLL correlation value R ( ⁇ )).
  • 6b-1 is a delay circuit that delays the first despread code string by one chip period and outputs a second despread code string A2, and 6b ⁇ is an output from the despread code generator.
  • a despreader freezer that multiplies the first despreading code sequence and the received data sequence B and despreads each chip
  • 61) -3 is the second despreading code sequence A delayed by one chip.
  • a despreader (multiplier) that despreads by multiplying 2 by 2 and the received data sequence B for each chip, and 6b-4 inverts the sign of the output of the despreader 6b-2 and the output of the despreader 6b-3 6b-5 is an integrator (low-pass filter).
  • the despreader 6b-3 and the low-pass filter 6b-5 have a function of calculating the correlation between the second despread code sequence A2 delayed by one chip period and the received data sequence B, and the second despread code sequence A If the phase of 2 and the received data string B match, the maximum The correlation value R ( ⁇ ) shown in Fig. 14 (B) is output.
  • the correlation value R ( ⁇ ) becomes 1 / N.
  • the adder 6b_4 adds the inverted output of the despreader 61) -2 and the output of the despreader 6b_3 with the sign inverted to add the S-curve characteristic shown in Fig. 14 (C) to the phase difference ⁇ .
  • a 1 "raw DLL correlation value signal R ( ⁇ ) is output via the low-pass filter 6b-5.
  • the voltage-controlled oscillator 6a-2 of the despreading code generator 6a controls the clock frequency based on the output of the low-pass filter so that the phase difference becomes zero. For example, if the phase of the despreading code is advanced with respect to the spreading code on the transmitting side included in the received data sequence, the control is performed so that the peak frequency is reduced so that the phase difference becomes zero. If the phase of this signal lags behind the spreading code on the transmitting side, the peak frequency is increased and the phase difference is controlled to be zero.
  • Despreading is performed, the power difference of the despread signal is calculated at each timing, and the sign of the code is used to determine the phase lead / lag of the PN sequence (despread code) and follow the path.
  • FIG. 15 is a block diagram of the phase compensator.
  • the spectrum despread outputs It and Qt of the pilot signal are phase-rotated by the phase detector 6d-l and corrected to I and Qt 7. .
  • the phase difference calculator 6D-2 calculates the phase difference ⁇ between the corrected signal point position vector P ACT (I, Qt ') and the pilot signal ideal signal point position vector P IDL (Fig. 10). If the value of the phase difference ⁇ becomes equal to or less than the set value, the state monitoring / switching unit 6d-3 determines that the state is synchronous, and outputs a switching signal.
  • the clock frequency of the mobile communication terminal does not match the reference clock frequency of the base station.
  • Betatoru P ACT after detection according deviation of the end end of the clock frequency is adapted to the asynchronous state rotated from the ideal position.
  • the switching unit 6d-4 inputs the phase difference signal ⁇ 0 to the phase difference capturing unit 6d-5, and the normal pull-in process is performed until the switching unit 6d-4 becomes the resynchronization state. That is, the phase difference correction unit 6d-5 gradually changes the output phase with time according to the rotation direction (positive or negative) of the phase difference as shown in FIGS.
  • the loop filter 6 d-6 adjusts the response speed of the PLL so that it does not unnecessarily follow sudden changes in the phase
  • the VCO (volume age cont rolled os ci 1 l at or) 6d-7 is the loop filter output voltage.
  • a signal having a frequency corresponding to (a radio signal of a radio section or a baseband master clock signal) is output.
  • the sine wave generator 6 (1-8 generates a sine wave signal corresponding to the phase rotation amount ⁇ ⁇ based on the loop filter output and inputs it to the phase corrector 6d-l, Capture the phase of the vector.
  • the synchronous detector 6e performs the operation of equation (1) to perform a phase rotation process on the information signal (1 ',), and then performs synchronous detection of the received information signal, and passes through a rake combiner (not shown). And outputs it to the error correction decoder 8.
  • the erroneous correction decoder 8 executes erroneous correction decoding processing to decode and output transmission information.
  • the terminal clock frequency of the mobile communication terminal does not match the reference clock frequency of the base station.
  • the orthogonal detector 2 multiplies the reception carrier generated based on the terminal close signal by the reception baseband signal to output the I component signal and the Q component signal, and the matched filter of the searcher 5 outputs the terminal filter.
  • the correlation calculation is performed based on the clock signal, and the base station reference timing is detected based on the peak timing.
  • the despreading unit 6c starts despreading based on the detected base station reference timing, and the phase compensating unit 6d performs the above-described AFC control while scanning the phase, that is, the clock frequency of the terminal.
  • the terminal clock frequency is equal to the reference clock frequency of the base station with the required accuracy, and the error of the reference timing detected by the searcher is also small.
  • the phase of the base station-side spreading code can be detected with an accuracy within one chip (synchronous acquisition state).
  • the synchronous capture state becomes strong, the reference timing detection control by the searcher (matched filter) is stopped, and the AFC control by the DLL circuit 6b is started instead.
  • the synchronous detector 6e starts synchronous detection.
  • the DLL circuit 6b controls the despreading code sequence on the receiving side so that there is no time lag with respect to the received signal once successfully acquired even if the phase of the received signal changes due to modulation or noise. Yes (synchronous tracking).
  • the zero crossing point of the DLL characteristic S-carp
  • the Machito filter is started periodically to restart the AFC control by the phase compensator to reduce the deviation of the zero crossing point.
  • accurate AFC control cannot be performed unless data is demodulated and the pilot signal is recognized.
  • the base station's reference clock is used.
  • the error (frequency deviation) between the frequency and the clock frequency of the terminal must be reduced, and data demodulation cannot be performed if the deviation of the peripheral number is large because synchronous detection is premised. Is large When the rotation speed of the position data vector on the Ij Q plane exceeds the processing capacity, the speed becomes faster, and it becomes impossible to identify the rotation direction position of the position vector on the Ij Q plane. This makes it impossible to demodulate the data.
  • the clock frequency of the terminal is scanned to make the demodulation sensitivity of the pilot signal equal to or higher than a certain level, and the phase difference ⁇ 0 is equal to or lower than the set value. Then, it is necessary to turn on the AFC loop and execute the frequency pull-in operation.
  • the conventional technology has a problem that it takes a very long time to initially pull in the AFC.
  • the AFC control requires a large current consumption because it performs a matrix operation using an arithmetic circuit (DSP: digital signal proc es sor) and a reference timing detection operation using a matched filter.
  • DSP digital signal proc es sor
  • the conventional technology requires a long time for AFC control, which consumes a large amount of energy and increases current.
  • An object of the present invention is to reduce the time required for the initial pull-in of the AFC when the power is turned on or when returning from the outside of the service area to the service area, thereby enabling prompt communication.
  • Another object of the present invention is to reduce the time of AFC control for operating the matched filter and the phase compensator to reduce current consumption.
  • Another object of the present invention is to lengthen the execution cycle of AFC control by a matched filter and a phase compensation unit which needs to be performed periodically during a call under DLL control.
  • a CDMA mobile terminal in which a known pattern (pilot) is regularly arranged in the frame format of the broadcast channel from the base station, when the power is turned on or when returning from outside the service area to the service area, A correlation value between the timing identification spreading code transmitted by the base station and the data sequence received from the base station is calculated, and a base station reference timing is detected based on the peak value of the correlation value. Based on the difference between the calculated reference timing interval and the reference base station reference timing interval, feedback control of the terminal peak frequency is performed, and the terminal peak frequency is promptly obtained from the phase compensation section. It pulls in to a frequency that allows AFC control by the output phase error ⁇ , and reduces the time required for the initial pull-in of AFC (AFC control in the first stage).
  • the AFC control by the phase compensator is started and reception is performed. Control the terminal peak frequency so that the phase error ⁇ ⁇ between the signal point position vector of the pilot symbol on the I-j Q plane and the known signal point position vector of the known pilot symbol becomes zero. (2nd stage AFC control).
  • the terminal clock frequency is set to the reference clock frequency of the base station by the AFC control in the second stage. If the number is equal to the required accuracy, the error in the detected reference timing will be small, and the phase of the base station side spreading code can be detected with an accuracy within one chip (synchronous acquisition state). In such a synchronization capture state, the DLL executes the AFC control. At this time, the DC component of the AFC control voltage of the DLL is detected, and the terminal's peak frequency is controlled so that the DC component becomes zero (the third-stage AFC control). This makes it possible to correct the frequency fluctuations due to changes in the temperature / propagation environment, etc., to keep the frequency deviation small, and to correct the fixed frequency deviation. The interval of AFC control performed by operating the compensator can be increased, and power consumption can be reduced.
  • FIG. 1 is a configuration diagram of a receiving section of a CDMA mobile communication terminal of the present invention.
  • FIG. 2 is an explanatory diagram of the phase error ⁇ between the signal point vector P ACT of the received pilot symbol and the ideal signal point position vector P IDL of the known pilot symbol.
  • FIG. 3 is an explanatory diagram of an error in the detection reference timing due to the frequency deviation at the time of the initial pull-in of the frequency.
  • FIG. 4 is an explanatory diagram of the DC component included in the DLL correlation value R ( ⁇ ) due to the fixed frequency deviation.
  • FIG. 5 is a timing chart for explaining the first-stage AFC control operation of the present invention.
  • FIG. 6 is a second-stage AFC control explanatory diagram.
  • FIG. 7 is an explanatory diagram of the S-carp in the DLL.
  • FIG. 8 is an overall processing flow of the present invention.
  • FIG. 9 is a configuration diagram of a CDMA receiver.
  • FIG. 10 is an explanatory diagram of phase rotation of pilot symbols.
  • FIG. 11 is an explanatory diagram of a configuration of a matched filter and a method of specifying a despread timing.
  • FIG. 12 is a relationship diagram between the reference timing of the terminal and the reference timing of the base station.
  • FIG. 13 is a configuration diagram of a DLL circuit.
  • FIG. 14 is an explanatory diagram of the S curve of the DLL control.
  • FIG. 15 is a configuration diagram of the phase compensation unit.
  • FIG. 16 is an explanatory diagram of a conventional phase difference correction at the time of initial pull-in.
  • FIG. 1 is a configuration diagram of a receiving section of a CDMA mobile communication terminal of the present invention.
  • the radio unit (RF) 101 performs frequency conversion (RF ⁇ IF conversion) of a high-frequency signal received by the antenna ATN into a baseband signal.
  • the IF unit 102 includes a quadrature demodulation unit, a low-pass filter, an AD converter, and the like.
  • the quadrature detector creates a received carrier signal using the local signal of the radio section, multiplies the received carrier by the baseband signal output from the RF section 101 to generate an I component signal and a Q component signal, and the low-pass filter
  • the band of the I-component signal and the Q-component signal is limited, and the AD converter converts the I-component signal and the Q-component signal into digital signals, respectively, and outputs a searcher 103 having a matched filter configuration and a despreading unit 104 of each finger unit. Enter in.
  • the searcher 103 calculates the correlation value between the timing identification spreading code transmitted by the base station and the data string received from the base station when the power is turned on or when the mobile station returns from the service area to the service area, and based on the peak position of the correlation value.
  • the base station detects the reference timing of the base station, and inputs the despreading timing to the despreading unit 104 based on the detected reference timing.
  • the searcher with the matched filter configuration has a large circuit scale and large power consumption.
  • the despreading unit 104 includes a despreading code generating unit 104a, a despreading circuit 104b, and a DLL circuit 104c.
  • the despreading code generating unit 104a transmits a spreading code sequence on the transmission side based on the despreading timing input from the searcher 103.
  • the despreading circuit 104b generates the same despreading code sequence, and the despreading circuit 104b multiplies the I component signal and the Q component signal input from the IF unit 102 by the despreading code and despreads, thereby obtaining pilot symbols and information symbols.
  • the DLL circuit 104c has the configuration shown in Fig.
  • the DLL circuit 104c controls the phase of the despread code sequence by the correlation value signal R ( ⁇ ), and this signal is used for AFC control as described later.
  • the DLL circuit 104c has a smaller circuit size and a smaller current consumption than the match filter.
  • the phase compensation unit 105 calculates the phase error delta 0 signal points vector P AC T of the received pilot symbol (Fig.
  • phase error ⁇ is the sum of the phase error 0 moVe due to temperature / fading / multipath and the phase error 0 error due to the frequency deviation.
  • the synchronous detector 106 uses co s A 0 and sin ⁇ 0 to add the received information symbol, Q f to the following equation (1)
  • the error correction decoder 107 performs an error correction decoding process on the synchronous detection output signal and decodes transmission data.
  • the timing error integrator 111 integrates the difference between the reference timing interval detected by the searcher 103 and the regular reference timing interval, and uses the integrated value as a frequency pull-in control signal to control the clock signal generator (VC-TCX0) 112 Input to the control voltage control unit 110.
  • the matched filter of Searcher 103 calculates the correlation value between the timing identification spreading code (known) transmitted by the base station and the data sequence received from the base station, and calculates the peak position of the correlation value.
  • the reference timing of the base station is detected. When the frequency is initially pulled in, the terminal's peak frequency does not match the base station's reference peak frequency, and there is a frequency deviation. In addition to this frequency deviation, the reference timing detected as shown in FIG.
  • the interval of the frame timing does not coincide with the regular reference timing interval of 10 ms e c and includes a time error Te-MF.
  • the timing error integration section 111 integrates the time error Te-MF, and inputs the integrated value to the control voltage control section 110 as a frequency pull-in control signal.
  • the DLL correlation value integration unit 113 integrates the DLL correlation value R ( ⁇ ), and inputs the integrated value to the control voltage control unit 110 of the clock signal generation unit (VC-TCX0) 112 as an AFC control signal.
  • the DLL circuit 104c is to detect the deviation of the despreading timing of ⁇ 1/2 chip or less due to fading, movement, frequency fluctuation, etc., but if there is a fixed frequency deviation, as shown in FIG. Includes the DC component CNTe-DLL in the DLL correlation value R (). Then, the DLL correlation value integration unit 113 integrates the DLL correlation value R ( ⁇ ) to obtain the DC component CNTe-DLL. Therefore, this DC component is input to the control voltage control unit 110 as an AFC control signal.
  • the VC0 clock signal generator (VC-TCX0) 112 outputs a terminal reference clock signal having a frequency corresponding to the control voltage output from the control voltage controller 110.
  • the PLL unit 114 generates a local frequency signal of the radio unit and outputs a baseband master clock signal CLK.
  • the terminal reference timing generator 115 generates various timing signals based on the baseband master clock signal CLK. Generates a click signal and inputs it to each part of the terminal.
  • the AFC control unit 116 controls the phase compensation unit 105, the timing error integrator 111, and the DLL correlation value integrator 113 to control the frequency of the terminal's peak signal.
  • the searcher 103 matched filter calculates the correlation value between the timing identification spreading code transmitted by the base station and the data string received from the base station when the power is turned on or when the mobile station returns from the outside of the service area to the service area.
  • the base station's reference timing is detected based on the peak position of the value. Initially, the terminal clock frequency and the base station reference clock frequency do not match, and there is a frequency deviation. Due to this frequency deviation, the interval of the detected reference timing does not match the interval of the normal reference timing, and a time error is included.
  • the timing error integrator 111 integrates the time error Te-MF.
  • the AFC control unit 116 inputs the integrated value output from the timing error integration unit 111 to the control voltage control unit 110 as a frequency pull-in control signal at the time of initial frequency pull-in immediately after power-on or immediately after returning from outside the service area to the service area. I do.
  • the control voltage controller 110 controls the frequency of the clock signal output from the clock signal generator 112 based on the integrated value so that the time error Te-MF of the reference timing caused by the frequency deviation becomes zero. According to this feedback control, the clock frequency of the terminal can be quickly drawn to a frequency at which AFC control based on the phase error ⁇ 0 output from the phase compensation section 105 is possible. As mentioned above, the time required for the initial pull-in of the AFC control can be reduced. ⁇ ⁇ ⁇ First stage AFC control
  • the AFC control unit 116 inputs the phase error ⁇ output from the phase compensation unit 105 to the control voltage control unit 110 as an AFC control signal.
  • the phase error ⁇ ⁇ is the signal point position vector of the received pilot symbol on the j j plane and the ideal signal point position of the known pilot symbol.
  • the control voltage control unit 110 controls the frequency of the clock signal output from the clock signal generator 112 so that the phase error ⁇ becomes zero.
  • the phase of the base station side spreading code can be detected with an accuracy within one chip (synchronous acquisition).
  • the AFC control unit 116 stops the operations of the timing error integrator 111 and the phase compensator 105 and sets their outputs to zero, instead of the DLL.
  • the circuit 104c and the DLL correlation value integration unit 113 are activated. As described with reference to FIGS. 13 and 14, the DLL circuit 104c controls the phase of the despreading code based on the DLL correlation value R () (synchronous tracking). Further, the DDL correlation value integration section 113 detects a DC component CNTe-DLL of the DDL correlation value R ( ⁇ ), and inputs the DC component to the control voltage control section 110 as an AFC control signal.
  • the control voltage control unit 110 controls the terminal's peak frequency so that the DC component of the DDL correlation value R ( ⁇ ) becomes zero. As described above, it is possible to correct the frequency fluctuation due to a change in the temperature / propagation environment and the like, thereby suppressing the frequency deviation width to a small extent, and to correct the fixed frequency deviation. As a result, the period of the AFC control (the second-stage AFC control) performed by operating the matched filter and the phase compensation unit can be lengthened, and the number of times can be reduced to reduce power consumption. .
  • the AFC control unit 116 stops the operation of the Dl 1 circuit 104c and the DLL correlation value integration unit 113 after performing the third-stage AFC control for a predetermined time, and starts the operation of the phase compensation unit 105 instead. Performs normal AFC control based on the phase error ⁇ ⁇ (the second-stage AFC control). When the correction of the frequency error in the second-stage AFC control is completed, the third-stage AFC control is performed. Thereafter, the second and third steps of the AFC control are repeated.
  • the AFC control unit 116 monitors the output voltage of the DLL correlation value integration unit 113 in the third-stage AFC control, and immediately executes the second-stage AFC control when the voltage value exceeds the set value. To correct the frequency error. As described above, the frequency error can always be kept within the set value.
  • the rough AFC control based on the error Te-MF of the timing information from the searcher 103 (the first stage) AFC control) to pull in the clock frequency to the level that enables synchronous detection. Then, based on the information of the phase error ⁇ from the phase compensator 105, the clock frequency is drawn with high accuracy so that the click frequency matches the reference clock frequency of the base station (AFC in the second stage). control).
  • the operation of the searcher is stopped, the DLL circuit 104c is started up instead, and the despreading timing correction information (DLL correlation value) output from the DLL circuit is output.
  • R ( ⁇ )) to perform AFC control (AFC control in the third stage).
  • AFC control AFC control in the third stage.
  • it switches to the regular second-stage AFC control periodically or by detecting an alarm state before demodulation is disabled. Thereafter, the second and third stages of AFC control are repeated.
  • FIG. 5 is a timing chart for explaining the first stage AFC control operation of the present invention, and shows a case where reference timings of three base stations are detected.
  • (1) shows the lower signal frame (broadcast channel frame) from the base station, and (2) shows the time slot configuration.
  • (3) is the reference timing (time slot) of the terminal
  • (4) to (6) are the reference timings of base stations A, B, and C detected in the searcher
  • (7) is the base stations A, B, and C.
  • (8) is the detection reference timing of base stations A, B, and C, ⁇ - ⁇ , ⁇ - ⁇ , ⁇ -C, and the delay time from terminal reference timing ⁇ -sA, T-sB , T-s C.
  • (9) shows the error of the terminal reference timing
  • (9-1) shows the absolute reference timing of the base station
  • (9-2) shows the terminal reference timing relative to the absolute reference timing. is there.
  • the searcher 103 with the matched filter configuration in Fig. 1 is implemented in the initial synchronization pull-in, but the detection timing of each base station detected is as shown in (8) and (9) in Fig. 5. Flows over time.
  • the matched filter can instantaneously calculate the correlation value of two code strings at a predetermined timing by one operation, but has the disadvantage of increasing the circuit size and Z power consumption. Even when a matched filter is used, it is necessary to take an average of the correlation values in order to increase the accuracy of the measurement. The time gets longer. As described above, the conventional technology using the matched filter has a problem that the initial synchronization pull-in time is long, the power consumption is large, and the life of the battery is short!
  • the flow of the peak timing (reference timing) of the correlation value calculated by the searcher 103 is quantitatively measured, and rough frequency adjustment is performed using the result.
  • AFC control second-stage AFC control
  • the base station oscillates at the radio carrier frequency and the baseband frequency. Therefore, the frequency error between the terminal clock frequency and the base station reference clock frequency appears as a flow on the time axis of the matched filter detection timing as shown in (9) of FIG.
  • the time difference ⁇ ((8) in Fig. 5) at which the peak of the correlation value is obtained is observed differently from the actual detection interval.
  • Figure 5 shows a state in which three valid pilots are being received.Each of them is affected by Doppler shift due to movement.However, by averaging information from multiple base stations, the effect is reduced. Can be eased.
  • the detection of the timing error which is a problem here, can be easily realized by a counter that operates at a rate of about eight times the chip rate.
  • the count value is smaller by -19 than the case of the frequency error force SO.
  • the timing error integrator 111 detects and integrates the frequency error, and controls the clock signal generator (VC-TC X0) 112 to correct the detected error.
  • the frequency error with respect to the reference cook signal can be reduced.
  • the second stage AFC control can be used to control the terminal clock frequency at high speed to the required accuracy.
  • each symbol is mapped on the i-jQ plane at a position, where 1 corresponds to 1 and 0 corresponds to 1. If the amplitude of the input is constant and the frequencies on the transmitting and receiving sides (carrier frequency / baseband frequency) match, the signal point of each symbol sticks to one point as shown in Fig. 6 (A). If the values of each symbol are known, all points can be collected into one point by matrix operation (phase rotation).
  • Fig. 6 (B) shows an example of collection in the first quadrant. For example, if it is (1, 0), it will be rotated by (- ⁇ / 2). Actually, the vector rotates from the dotted line position as shown in Fig. 6 (C) due to the influence of fogging and frequency error due to movement. After all, the received signal point position vector (Rq, Qi) is calculated using the actual signal point position vector (Dq, Di) as
  • Ri is the I component of the received electric field
  • Rq is the Q component of the received electric field.
  • ⁇ ⁇ is obtained from the output of the memory whose amplitude is the amplitude of the standardized I and Q components.
  • the phase error ⁇ 0 at the measurement interval becomes large, the position on the I-jQ plane cannot be specified, and the calculation itself becomes impossible.
  • the measurement interval is 1 ms
  • the error is 1 ppm
  • the rotation angle exceeds 2 ⁇ , and the calculation cannot be performed, and AFC control cannot be performed.
  • the initial pull-in of the frequency is performed in the first-stage AFC control so that the AFC control using the despread pilot data (the second-stage AFC control) becomes possible.
  • AFC control section 116 activates phase compensation section 105.
  • the phase compensator 105 calculates the phase error ⁇ 0 by the above method and inputs the calculated phase error ⁇ 0 to the control voltage controller 110.
  • the control voltage controller 110 controls the frequency of the clock signal output from the clock signal generator 112 so that the phase error ⁇ ⁇ becomes zero.
  • the reference frequency of the terminal fluctuates due to temperature changes and so on, so it is necessary to continue the second-stage AFC control.
  • complex operations in the AFC control in the second stage are performed by a DSP (digital signal processor), and the reference timing detection operation is performed by a multi-filter, resulting in considerable current consumption. Need. Therefore, it is not efficient to always perform the second-stage AFC control in order to keep processing load and power consumption low. Therefore, it is conceivable to perform AFC control in some way (for example, DLL control) that consumes a small amount of current, and then perform AFC control in the second stage at a predetermined cycle. You. In this case, it is not preferable to perform the second-stage AFC control in a short cycle for the same reason as described above, and it is preferable to perform the AFC control in a long cycle.
  • the phase of the despreading code is controlled by the DLL, and the DLL correlation value R ( ⁇ AFC control is performed using the integrated value of (2), thereby increasing the period for performing the second-stage AFC control.
  • the phase control of the despreading code by the DLL becomes impossible, an alarm is output and the second-stage AFC control is forcibly performed, and the phase control by the DLL becomes impossible. Avoid the situation that becomes.
  • FIG. 7 is an explanatory diagram of the S-carp in the DLL.
  • A shows the case where the frequency deviation is zero
  • B shows the case where the frequency deviation is ten
  • C shows the case where the frequency deviation is one.
  • DLL control corrects the deviation of the despreading timing (caused by fading, movement, frequency fluctuation, etc.) of ⁇ 1/2 chip or less, but the fixed frequency deviation of the terminal clock signal is It becomes visible if the control amount (DLL correlation value) is integrated over a long period. This is because, unlike other factors, the deviation direction is always constant.
  • the output of the DLL correlation value integration unit 113 is the DC component CNTe-DLL of FIG.
  • the DC component is monitored, and when the output signal value reaches a set level and approaches a dangerous state in which the DLL cannot control the phase of the despreading code, an alarm is output and the second-stage AFC control is performed. . Executing AFC control switching based on such an alarm can lengthen the period of the second-stage AFC control that is performed periodically, and reduce power consumption.
  • the AFC control unit 116 stops the operations of the timing error integrator 111 and the phase compensator 105, sets their outputs to zero, and replaces them. Then, the DLL circuit 104c and the DLL correlation value integrator 113 are activated. The DLL circuit 104c controls the phase of the despread code based on the DLL correlation value R ( ⁇ ) (synchronous tracking). Further, the DDL correlation value integration section 113 detects a DC component of the DDL correlation value R (r), and inputs the DC component to the control voltage control section 110 as an AFC control signal. The control voltage control unit 110 controls the clock frequency of the terminal so that the DC component of the DDL correlation value R ( ⁇ ) becomes zero. (D) Overall processing flow
  • FIG. 8 is an overall processing flow of the present invention.
  • the AFC control unit 116 activates the searcher 103 and the timing error integrator 111, and the searcher performs a timing search to specify the reference timing of the base station.
  • the searcher 103 performs a timing search for each of the n paths M times, and finds that the time difference (M-1) -To between the M-th timing 0 and the first timing To and the frequency deviation Time difference when 0 and difference between and [( ⁇ -1) ⁇ ⁇ . -T M — Determine the frequency error by averaging the ⁇ paths of J. Note that ⁇ may be 1.
  • the timing error integrator 111 integrates the average of the time differences, and inputs the integrated value to the control voltage controller 110 as a frequency pull-in control signal.
  • the control voltage controller 110 controls the frequency of the clock signal output from the clock signal generator 112 based on the integrated value so that the time error of the reference timing caused by the frequency deviation becomes zero.
  • rough frequency correction is performed, and the clock frequency of the terminal is drawn to a frequency at which the second-stage AFC control for controlling the terminal based on the phase error ⁇ is possible (Step 203). ... First stage AFC control
  • the AFC control unit 116 activates the inverse diffusion unit 104 and the phase compensation unit 105.
  • Despreading section 104 starts despreading processing based on the reference timing detected by the searcher, and demodulates the I and Q components of the pilot symbol (step 204).
  • the phase compensation unit 105 calculates a phase error ⁇ based on the I and Q components of the pilot symbol, and inputs the phase error ⁇ to the control voltage control unit 110 as an AFC control signal.
  • the control voltage control unit 110 controls the frequency of the clock signal output from the clock signal generator 112 so that the phase error ⁇ becomes zero.
  • This feed-pack control allows the clock frequency of the terminal to be as high as required (less than 0.1 ppm), and the DLL circuit 104c can detect the phase of the base station side spreading code with an accuracy within one chip. (Step 205).
  • AFC control in the second stage With the above control, if the terminal's peak frequency falls within the required accuracy, data can be demodulated.Synchronous detection unit 106 performs synchronous detection. Perform an error correction decoder 107 executes error correction / decoding processing based on the synchronous detection output signal to decode transmission data (step 206). At the time of data demodulation, the AFC control unit 116 stops the operations of the searcher 103 and the phase compensation unit 105 to make their outputs zero, and starts the DLL circuit 104c and the DLL correlation value integration unit 113 instead.
  • the DLL circuit 104c controls the phase of the despreading code based on the DLL correlation value R ( ⁇ ), and inputs the DLL correlation value R (T) to the DDL correlation value integration unit 113.
  • the DDL correlation value integration unit 113 detects the DC component by integrating the DDL correlation value R ( ⁇ ), and outputs the DC component as a fixed frequency deviation (step 207).
  • the control voltage control section 110 uses the integrated output of the DDL correlation value integration section 113 as an AFC control signal, and controls the clock frequency of the terminal so that the integrated output becomes zero (step 208). As described above, the fixed frequency deviation can be corrected. ⁇ ⁇ ⁇ Third-stage AFC control
  • the AFC control unit 116 checks whether the third-stage AFC control has been performed continuously for the set time, in other words, checks whether the second-stage normal AFC control start time has come (step 209). If “Yes”, the process returns to step 205 to restart the normal AFC control of the second stage. If “No”, the integrated output of the DDL correlation value integration unit 113 exceeds the set value and DL L It is checked whether or not the approach to a dangerous state in which the phase control of the despreading code by using is impossible (step 210). If “Yes”, return to step 205 and execute the normal AFC control of the second stage. If “NoJ”, check if the call has ended (step 211). If not, go to step 207 and after. The AFC control of the third stage is continued, and when the call ends, the power save is performed (step 212), and the AFC process ends.
  • the present invention it is possible to greatly reduce the AFC pull-in time at the time of power-on or recovery from out of service area without adding special hardware, and to reduce the number of AFC activations during a call to the minimum required. It is possible to limit to the limit. As a result, the transition to the standby state is quickened, and the power consumption is reduced and the battery life is prolonged.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Dans un régulateur automatique de fréquence d'horloge pour terminal de communication CDMA (accès multiple par répartition de code), une unité de régulation automatique de fréquence AFC (1) régule la fréquence d'horloge en envoyant à une unité de génération de signal d'horloge un signal correspondant à l'erreur temporelle entre une synchronisation de référence normale et une synchronisation de référence détectée en fonction d'une opération de corrélation assurée par l'intermédiaire d'un filtre accordé au moment de la capture initiale de la fréquence d'horloge après la mise en marche du commutateur de puissance ou après le retour de la station mobile à la zone depuis l'extérieur ; (2) régule la fréquence d'horloge en fonction d'une fréquence d'horloge de référence par l'exploitation de la différence de phase de l'angle de rotation sur le plan I-jQ d'un symbole spécifié contenu périodiquement dans le signal de liaison descendante provenant d'une station de base, lors de l'achèvement de la capture initiale de l'horloge de fréquence et de l'entrée d'un signal de différence de phase dans l'unité de génération de signal d'horloge ; (3) régule la fréquence d'horloge, de manière qu'une valeur moyenne de valeur de corrélation DLL soit de zéro lorsque la précision requise du signal d'horloge correspond à celle de la fréquence d'horloge de référence en ramenant le signal de différence de phase à zéro et en entrant le signal moyen dans l'unité de génération de signal d'horloge.
PCT/JP2001/001148 2001-02-19 2001-02-19 Regulateur automatique de frequence WO2002067456A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2391751A (en) * 2002-08-06 2004-02-11 Nec Technologies Clock frequency correction in a mobile communications system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000059266A (ja) * 1998-08-11 2000-02-25 Nippon Telegr & Teleph Corp <Ntt> スペクトル拡散信号復調回路
JP2000232394A (ja) * 1999-02-09 2000-08-22 Matsushita Electric Ind Co Ltd Ｃｄｍａ受信装置及びｃｄｍａ受信方法
JP2000341354A (ja) * 1999-05-27 2000-12-08 Matsushita Electric Ind Co Ltd 発振器制御回路及び発振器制御方法
JP2000349849A (ja) * 1999-06-02 2000-12-15 Japan Radio Co Ltd 周波数誤差検出装置及び自動周波数制御装置
JP2001016285A (ja) * 1999-06-25 2001-01-19 Nec Corp Ａｆｃ回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000059266A (ja) * 1998-08-11 2000-02-25 Nippon Telegr & Teleph Corp <Ntt> スペクトル拡散信号復調回路
JP2000232394A (ja) * 1999-02-09 2000-08-22 Matsushita Electric Ind Co Ltd Ｃｄｍａ受信装置及びｃｄｍａ受信方法
JP2000341354A (ja) * 1999-05-27 2000-12-08 Matsushita Electric Ind Co Ltd 発振器制御回路及び発振器制御方法
JP2000349849A (ja) * 1999-06-02 2000-12-15 Japan Radio Co Ltd 周波数誤差検出装置及び自動周波数制御装置
JP2001016285A (ja) * 1999-06-25 2001-01-19 Nec Corp Ａｆｃ回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2391751A (en) * 2002-08-06 2004-02-11 Nec Technologies Clock frequency correction in a mobile communications system
GB2391751B (en) * 2002-08-06 2006-01-04 Nec Technologies Improvement to clock frequency correction in mobile communication systems

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