WO2002067456A1

WO2002067456A1 - Afc controller

Info

Publication number: WO2002067456A1
Application number: PCT/JP2001/001148
Authority: WO
Inventors: Tetsuya Kikuchi
Original assignee: Fujitsu Limited
Priority date: 2001-02-19
Filing date: 2001-02-19
Publication date: 2002-08-29

Abstract

In a clock frequency controller for CDMA mobile communication terminal, an AFC control section (1) controls the clock frequency by providing a clock signal generating section with a signal corresponding to the time error between a normal reference timing and a reference timing detected based on correlation operation through a matched filter at the time of initial pull-in of the clock frequency after the power switch is turned on or after the mobile station returns to the zone from the outside, (2) controls the clock frequency to agree with a reference clock frequency by operating the phase difference of the rotational angle on the I-jQ plane of a specified symbol contained periodically in the downlink signal from a base station upon finishing initial pull-in of the clock frequency and inputting a phase difference signal to the clock signal generating section, (3) controls the clock frequency so that an average value of DLL correlation value becomes zero when the required accuracy of the clock signal agrees with that of the reference clock frequency by bringing the phase difference signal to zero and inputting the average signal to the clock signal generating section.

Description

Specification

AFC controller

Technical field

The present invention relates to an AFC controller in a CDMA mobile communication terminal in which a known fixed pattern (pilot) is arranged in a lower signal from a base station. AFC control device capable of shortening the initial frequency pull-in time of AFC control at a time and reducing current consumption, and a CDMA mobile communication terminal equipped with the AFC control device.

Background art

In a CDMA (Code Division Multiple Access) mobile communication system using the spread spectrum method, the transmitting side spreads the transmission information using a spreading code string and transmits it, and the receiving side transmits the signal received from the transmitting side. The transmission information is demodulated by despreading using the same despreading code sequence as that of the transmitting side.

FIG. 9 is a configuration diagram of a CDMA receiver. The radio unit 1 converts the frequency of the high-frequency signal received by the antenna ATN to a baseband signal (RF → IF conversion), and the quadrature detector 2 performs quadrature detection of the baseband signal, and outputs in-phase component (I component) data. Outputs quadrature component (Q component) data. In the quadrature detector 2, 2a is a received carrier generator, 2b is a phase shifter that shifts the phase of the received carrier by π / 2, and 2c and 2d are multipliers that convert the received carrier to a respread span signal. It multiplies and outputs an I component signal and a Q component signal. The low-pass filters (LPF) 3a and 3b limit the band of the output signal, and the AD converters 4a and 4b convert the I component signal and the Q component signal into digital signals, respectively. Is input to each finger section 6 i to 6 ₄ . When the direct spread signal (DS signal) affected by the multipath is input, the searcher 5 performs a correlation operation using a matched filter (not shown) to detect the multipath, and starts despreading in each path. ₃ and delay time adjustment data timing data tau ₀ ~ Te is input to the finger section 6 i to 6 _4. Despreading code generation section 6a of each finger portion 6 i to 6 ₄ is Te timing data inputting identical code sequence and spreading code sequence on the transmitting side from the searcher 5. Occurs based on ~ ₃ . That is, the searcher 5 detects the phase of the transmission-side spread code with an accuracy within one chip (synchronous acquisition), and the despread code generator 6a A spreading code sequence for despreading at the receiving side is generated in synchronization with the phase. The DLL (Delayed Locked Loop) circuit 61) detects the time difference between the received signal and the despread code sequence on the receiving side, even if the phase of the received signal changes due to modulation or noise. Control so that it does not happen (synchronous tracking).

The despreading Z delay time adjusting unit 6c performs a despreading process on the direct wave or the delayed wave arriving via a predetermined path using the same code as the spreading code to perform dump integration, and then delays according to the path. Performs processing and outputs pilot signal and information signal. At the time of communication, a pilot signal is inserted into a predetermined bit position of each time slot of the lower signal from the base station.

The phase compensator (channel estimator) 6d performs AFC (Automatic Frequency Control) control and calculates the rotation angle Δ0 on the I-jQ plane of the pilot signal included in the received signal. Output sin component. Synchronous detector 6e is cos A 0, despread information signals using sinA 0, ^Q; undo phase. That is, the pilot signal undergoes phase rotation during transmission due to the effects of fading, temperature change, multipath, etc., but if the signal point position vector PACT (see Fig. 10) is known on the receiving side, the ideal signal of the Pipit symbol is obtained. Since the point position vector P _IDL is known, the phase rotation angle Δ シンボル of the symbol due to transmission can be obtained. Thus, the phase compensator 6d detects the pilot symbol and calculates the phase rotation angle Δ 、, and the synchronous detector 6e uses cos Δ Θ and sinA 次

I \ / cos Δ Θ -sinA θ \ (

No (to sinA Θ cos Δ 0

Then, the received information signal (Ι ', Q') is subjected to phase rotation processing to return to the original state, and then the received information signal (1, Q) is demodulated (synchronous detection). RAKE combining section 7 you output error correction decoder as soft decision data string by synthesizing the signals output from each finger portion 6-6 _4. The erroneous correction decoder 8 performs erroneous correction processing to decode and output transmission information.

• Matched filter

Figure 11 is an explanatory diagram of the matched filter that constitutes Searcher 5-5a is a matched filter that performs a correlation operation between the received spread data sequence of the base span and the base station spreading code, and 5b is the timing identification. Section of the correlation value output from the matched filter. The base station identifies the base timing as the base station's spread start timing, that is, the base station's reference timing. In the matched filter 5 a, 5 la is an N-chip (eg, N = 256) shift register ( _{S 1} to s _N ) for sequentially shifting the baseband received spread data sequence at the chip frequency, and 51 b is a base station base station. An N-chip register ( _{C 1} to _C _N ) in which a spreading code (for example, a spreading code for timing identification) is set, 51 c is a base-band spreading data sequence and a corresponding bit of a base station spreading code sequence N multipliers (MPi MPw :) for multiplying by, and 51 d are adders for adding the outputs of the respective multipliers.

The matched filter 5a outputs one correlation value R (t) per one chip period, and thereafter sequentially outputs correlation values having different phases according to one chip period Tc, and outputs N correlation values in one symbol period. Output different correlation values. The timing identification unit 5b monitors the correlation value R (t) output from the adder 51d and checks whether the correlation value has become larger than the set level. , Ie, the reference timing of the base station. At the beginning of each time slot of the lower signal transmitted from the base station, a timing identification pattern (spread with a timing identification spreading code) is arranged. When the power is turned on or when the mobile station returns to the service area from outside the service area, the spread code for timing identification is set in the register 51b of the matched filter 5a as the base station spread code. As a result, the output R (t) of the adder 51d indicates a peak when the base station sets the spreading code for retiming identification in the shift register 51a.

FIG. 12 is an explanatory diagram for explaining such a situation. (1) shows a lower signal frame (broadcast channel frame), and (2) shows a time slot configuration. One frame is 10 msec and consists of 15 time slots. 1 timeslot is 1 0 symposium Le, leading first bit portion timing identification pattern of ① timeslot, ② second to sixth bit unit data unit D ₀ to D _5, seventh to ③ 1 0 bit portion is a fixed pattern portion for data demodulation (the pilot) P ₀ to P _4. Assuming that the spreading factor is 256, a signal obtained by spreading and modulating the first bit data of the time slot with the 256 timing identification spreading code becomes a timing identification pattern and arrives at the matched filter 5a for each time slot. For this reason, (3) is calculated based on the terminal time slot If the signal is delayed, the output of the Matsuchito filter 5a shows a peak at a position delayed by a predetermined time from the terminal time slot reference timing due to transmission delay or other reasons, and this peak position becomes the base station reference timing. .

• DLL circuit

If the phase of the spreader base station side spreading code can be detected within one chip (synchronization acquisition), the despreading unit 6c will thereafter synchronize with the phase of the spreading code on the receiving side. Generates a despreading code sequence for despreading, and performs despreading. DLL circuit 61) ensures that even if the phase of the received signal changes due to the influence of modulation, noise, etc., the despreading code sequence on the receiving side does not cause a time lag with respect to the received signal once successfully acquired. Control (synchronous tracking).

FIG. 13 is a configuration diagram of a DLL circuit, 6a is a despread code generator, and 61) is a DLL circuit. In the despreading code generating section 6a, 6a- 1 is the inverse spreading code generator for generating the despreading code sequence A i, consists of N chips, 1 Shinporu period T (= NXT _C, T _c is the chip period) per It is designed to occur cyclically. 6a-2 is a voltage controlled oscillator (VC0) that varies the clock frequency (chip frequency) based on the DLL circuit output (DLL correlation value R (τ)). In the DLL circuit 6b, 6b-1 is a delay circuit that delays the first despread code string by one chip period and outputs a _second despread code string A2, and 6b ^ is an output from the despread code generator. A despreader freezer that multiplies the first despreading code sequence and the received data sequence B and despreads each chip), 61) -3 is the second despreading code sequence A delayed by one chip. _A despreader (multiplier) that despreads by multiplying _{2 by 2} and the received data sequence B for each chip, and 6b-4 inverts the sign of the output of the despreader 6b-2 and the output of the despreader 6b-3 6b-5 is an integrator (low-pass filter).

The despreader 6b-2 and the low-pass filter 6b-5 have a function of calculating the correlation between the first despread code sequence and the received data sequence B. If the phases match, the maximum value is output, as shown in Fig. 14 (A), where the correlation value R (τ) = 1 for one chip period width is output for each symbol. The correlation value R (τ) is 1 / N. The despreader 6b-3 and the low-pass filter 6b-5 have a function of calculating the correlation between the _second despread code sequence A2 delayed by one chip period and the received data sequence B, and the second despread code sequence A If the phase of ₂ and the received data string B match, the maximum The correlation value R (τ) shown in Fig. 14 (B) is output. If the phase is shifted by one chip period or more, the correlation value R (τ) becomes 1 / N. The adder 6b_4 adds the inverted output of the despreader 61) -2 and the output of the despreader 6b_3 with the sign inverted to add the S-curve characteristic shown in Fig. 14 (C) to the phase difference τ. A 1 "raw DLL correlation value signal R (τ) is output via the low-pass filter 6b-5.

The voltage-controlled oscillator 6a-2 of the despreading code generator 6a controls the clock frequency based on the output of the low-pass filter so that the phase difference becomes zero. For example, if the phase of the despreading code is advanced with respect to the spreading code on the transmitting side included in the received data sequence, the control is performed so that the peak frequency is reduced so that the phase difference becomes zero. If the phase of this signal lags behind the spreading code on the transmitting side, the peak frequency is increased and the phase difference is controlled to be zero. As described above, the spread spectrum method DLL circuit 6b uses the phase difference τ = ± 0.5 chip (= ± _Tc / 2) with respect to the timing of the desired signal (the base station-side spread code string). Despreading is performed, the power difference of the despread signal is calculated at each timing, and the sign of the code is used to determine the phase lead / lag of the PN sequence (despread code) and follow the path.

AFC control by phase compensator

Figure 15 is a block diagram of the phase compensator. The spectrum despread outputs It and Qt of the pilot signal are phase-rotated by the phase detector 6d-l and corrected to I and Qt ^7. . The phase difference calculator 6D-2 calculates the phase difference Δ between the corrected signal point position vector P _ACT (I, Qt ') and the pilot signal ideal signal point position vector P _IDL (Fig. 10). If the value of the phase difference ΔΘ becomes equal to or less than the set value, the state monitoring / switching unit 6d-3 determines that the state is synchronous, and outputs a switching signal.

When the power is turned on or when the mobile terminal returns to the service area from outside the service area, the clock frequency of the mobile communication terminal does not match the reference clock frequency of the base station. In this state, Betatoru P _ACT after detection according deviation of the end end of the clock frequency is adapted to the asynchronous state rotated from the ideal position. When the switching unit 6d-4 is in the asynchronous state, the switching unit 6d-4 inputs the phase difference signal Δ 0 to the phase difference capturing unit 6d-5, and the normal pull-in process is performed until the switching unit 6d-4 becomes the resynchronization state. That is, the phase difference correction unit 6d-5 gradually changes the output phase with time according to the rotation direction (positive or negative) of the phase difference as shown in FIGS. Alternatively, gradually reduce the value and input it to the loop filter 6 d-6. The loop filter 6 d-6 adjusts the response speed of the PLL so that it does not unnecessarily follow sudden changes in the phase, and the VCO (volume age cont rolled os ci 1 l at or) 6d-7 is the loop filter output voltage. A signal having a frequency corresponding to (a radio signal of a radio section or a baseband master clock signal) is output. In addition, the sine wave generator 6 (1-8 generates a sine wave signal corresponding to the phase rotation amount Δ · based on the loop filter output and inputs it to the phase corrector 6d-l, Capture the phase of the vector.

Thereafter, when the above control is repeated, the clock frequency of the terminal output from the VCO 6d-7 approaches the reference clog frequency of the base station, the rotation of the signal point position vector P _ACT stops, and the phase difference Δ Θ It becomes less than the set value.

When the phase difference ΔΘ becomes equal to or less than the set value, the synchronization state monitoring switching unit 6d-3 determines that the synchronization state has been established, and inputs a switching signal to the switching unit 6d-4. Accordingly, the switching unit 6d-4 inputs the phase difference Δ0 directly to the loop filter 6d_6 to turn on the AFC loop. Thereafter, AFC control is performed so that ΔΘ = 0 (frequency pull-in).

The synchronous detector 6e performs the operation of equation (1) to perform a phase rotation process on the information signal (1 ',), and then performs synchronous detection of the received information signal, and passes through a rake combiner (not shown). And outputs it to the error correction decoder 8. The erroneous correction decoder 8 executes erroneous correction decoding processing to decode and output transmission information.

• Conventional frequency Z-phase control

When the power is turned on or when returning from the outside of the service area to the service area, the terminal clock frequency of the mobile communication terminal does not match the reference clock frequency of the base station. In such a situation, the orthogonal detector 2 multiplies the reception carrier generated based on the terminal close signal by the reception baseband signal to output the I component signal and the Q component signal, and the matched filter of the searcher 5 outputs the terminal filter. The correlation calculation is performed based on the clock signal, and the base station reference timing is detected based on the peak timing. The despreading unit 6c starts despreading based on the detected base station reference timing, and the phase compensating unit 6d performs the above-described AFC control while scanning the phase, that is, the clock frequency of the terminal. When the clock frequency of the terminal approaches the base clock frequency of the base station and the phase difference Δ 設定 falls below the set value to be in a synchronous state, the phase compensation unit 6d turns on the AFC loop and Δ 0 = AFC control so that it becomes 0 Perform (frequency pull-in).

By repeating the above AFC control, the terminal clock frequency is equal to the reference clock frequency of the base station with the required accuracy, and the error of the reference timing detected by the searcher is also small. In addition, the phase of the base station-side spreading code can be detected with an accuracy within one chip (synchronous acquisition state). When the synchronous capture state becomes strong, the reference timing detection control by the searcher (matched filter) is stopped, and the AFC control by the DLL circuit 6b is started instead. In addition, the synchronous detector 6e starts synchronous detection. The DLL circuit 6b controls the despreading code sequence on the receiving side so that there is no time lag with respect to the received signal once successfully acquired even if the phase of the received signal changes due to modulation or noise. Yes (synchronous tracking). In synchronous tracking, the zero crossing point of the DLL characteristic (S-carp) gradually shifts, and if it exceeds the range of τ = ± Τ (; / 2, the servo by the DLL becomes impossible. Before it becomes impossible, the Machito filter is started periodically to restart the AFC control by the phase compensator to reduce the deviation of the zero crossing point. In the conventional technology, accurate AFC control cannot be performed unless data is demodulated and the pilot signal is recognized.In order to demodulate data, the base station's reference clock is used. The error (frequency deviation) between the frequency and the clock frequency of the terminal must be reduced, and data demodulation cannot be performed if the deviation of the peripheral number is large because synchronous detection is premised. Is large When the rotation speed of the position data vector on the Ij Q plane exceeds the processing capacity, the speed becomes faster, and it becomes impossible to identify the rotation direction position of the position vector on the Ij Q plane. This makes it impossible to demodulate the data.

For this reason, in the prior art, during the initial pull-in operation when the power is turned on, the clock frequency of the terminal is scanned to make the demodulation sensitivity of the pilot signal equal to or higher than a certain level, and the phase difference Δ0 is equal to or lower than the set value. Then, it is necessary to turn on the AFC loop and execute the frequency pull-in operation. However, the conventional technology has a problem that it takes a very long time to initially pull in the AFC.

If the pilot signal cannot be demodulated due to the lower reception level, The path is cut, and AFC control itself becomes impossible. For this reason, frequency pull-in control is required when returning from outside the service area to the service area, but a long pull-in time was required as in the case of the I-lock operation when the power was turned on.

Furthermore, the AFC control requires a large current consumption because it performs a matrix operation using an arithmetic circuit (DSP: digital signal proc es sor) and a reference timing detection operation using a matched filter. The conventional technology requires a long time for AFC control, which consumes a large amount of energy and increases current.

An object of the present invention is to reduce the time required for the initial pull-in of the AFC when the power is turned on or when returning from the outside of the service area to the service area, thereby enabling prompt communication.

Another object of the present invention is to reduce the time of AFC control for operating the matched filter and the phase compensator to reduce current consumption.

Another object of the present invention is to lengthen the execution cycle of AFC control by a matched filter and a phase compensation unit which needs to be performed periodically during a call under DLL control.

Disclosure of the invention

In a CDMA mobile terminal in which a known pattern (pilot) is regularly arranged in the frame format of the broadcast channel from the base station, when the power is turned on or when returning from outside the service area to the service area, A correlation value between the timing identification spreading code transmitted by the base station and the data sequence received from the base station is calculated, and a base station reference timing is detected based on the peak value of the correlation value. Based on the difference between the calculated reference timing interval and the reference base station reference timing interval, feedback control of the terminal peak frequency is performed, and the terminal peak frequency is promptly obtained from the phase compensation section. It pulls in to a frequency that allows AFC control by the output phase error ΔΘ, and reduces the time required for the initial pull-in of AFC (AFC control in the first stage).

After the frequency deviation between the terminal clock frequency and the base station reference clock frequency is brought into a certain range by the first stage AFC control, the AFC control by the phase compensator is started and reception is performed. Control the terminal peak frequency so that the phase error Δ Δ between the signal point position vector of the pilot symbol on the I-j Q plane and the known signal point position vector of the known pilot symbol becomes zero. (2nd stage AFC control).

The terminal clock frequency is set to the reference clock frequency of the base station by the AFC control in the second stage. If the number is equal to the required accuracy, the error in the detected reference timing will be small, and the phase of the base station side spreading code can be detected with an accuracy within one chip (synchronous acquisition state). In such a synchronization capture state, the DLL executes the AFC control. At this time, the DC component of the AFC control voltage of the DLL is detected, and the terminal's peak frequency is controlled so that the DC component becomes zero (the third-stage AFC control). This makes it possible to correct the frequency fluctuations due to changes in the temperature / propagation environment, etc., to keep the frequency deviation small, and to correct the fixed frequency deviation. The interval of AFC control performed by operating the compensator can be increased, and power consumption can be reduced.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a configuration diagram of a receiving section of a CDMA mobile communication terminal of the present invention.

FIG. 2 is an explanatory diagram of the phase error Δø between the signal point vector P _ACT of the received pilot symbol and the ideal signal point position vector P _IDL of the known pilot symbol.

FIG. 3 is an explanatory diagram of an error in the detection reference timing due to the frequency deviation at the time of the initial pull-in of the frequency.

FIG. 4 is an explanatory diagram of the DC component included in the DLL correlation value R (τ) due to the fixed frequency deviation.

FIG. 5 is a timing chart for explaining the first-stage AFC control operation of the present invention. FIG. 6 is a second-stage AFC control explanatory diagram.

FIG. 7 is an explanatory diagram of the S-carp in the DLL.

FIG. 8 is an overall processing flow of the present invention.

FIG. 9 is a configuration diagram of a CDMA receiver.

FIG. 10 is an explanatory diagram of phase rotation of pilot symbols.

FIG. 11 is an explanatory diagram of a configuration of a matched filter and a method of specifying a despread timing. FIG. 12 is a relationship diagram between the reference timing of the terminal and the reference timing of the base station. FIG. 13 is a configuration diagram of a DLL circuit.

FIG. 14 is an explanatory diagram of the S curve of the DLL control.

FIG. 15 is a configuration diagram of the phase compensation unit. FIG. 16 is an explanatory diagram of a conventional phase difference correction at the time of initial pull-in.

BEST MODE FOR CARRYING OUT THE INVENTION

(A) Receiver configuration of CDMA mobile communication terminal

FIG. 1 is a configuration diagram of a receiving section of a CDMA mobile communication terminal of the present invention. The radio unit (RF) 101 performs frequency conversion (RF → IF conversion) of a high-frequency signal received by the antenna ATN into a baseband signal. The IF unit 102 includes a quadrature demodulation unit, a low-pass filter, an AD converter, and the like. The quadrature detector creates a received carrier signal using the local signal of the radio section, multiplies the received carrier by the baseband signal output from the RF section 101 to generate an I component signal and a Q component signal, and the low-pass filter The band of the I-component signal and the Q-component signal is limited, and the AD converter converts the I-component signal and the Q-component signal into digital signals, respectively, and outputs a searcher 103 having a matched filter configuration and a despreading unit 104 of each finger unit. Enter in.

The searcher 103 calculates the correlation value between the timing identification spreading code transmitted by the base station and the data string received from the base station when the power is turned on or when the mobile station returns from the service area to the service area, and based on the peak position of the correlation value. The base station detects the reference timing of the base station, and inputs the despreading timing to the despreading unit 104 based on the detected reference timing. The searcher with the matched filter configuration has a large circuit scale and large power consumption. The despreading unit 104 includes a despreading code generating unit 104a, a despreading circuit 104b, and a DLL circuit 104c. The despreading code generating unit 104a transmits a spreading code sequence on the transmission side based on the despreading timing input from the searcher 103. The despreading circuit 104b generates the same despreading code sequence, and the despreading circuit 104b multiplies the I component signal and the Q component signal input from the IF unit 102 by the despreading code and despreads, thereby obtaining pilot symbols and information symbols. I, Q components I, Qt,; 1 ', and outputs the Q ^7, respectively. The DLL circuit 104c has the configuration shown in Fig. 13 and starts control (synchronization acquisition) when the phase of the spread code on the transmitting side can be detected with an accuracy within one chip, and the received signal is modulated or noise The feedback control is performed so that the despreading code sequence on the receiving side does not cause a time lag with respect to the spreading code sequence even if the phase changes due to the influence (synchronous tracking). The DLL circuit 104c controls the phase of the despread code sequence by the correlation value signal R (τ), and this signal is used for AFC control as described later. The DLL circuit 104c has a smaller circuit size and a smaller current consumption than the match filter. The phase compensation unit 105 calculates the phase error delta 0 signal points vector P _{AC T} of the received pilot symbol (Fig. 2) and the base ideal signal point positions of the pi port Ttoshinboru already known vector P _IDL, phase error delta 0 Is input to the control voltage control unit 110 of the clock signal generation unit (VC-TCX0) 112, and its cos component and siii component are output. The phase error ΔΘ is the sum of the phase error 0 moVe due to temperature / fading / multipath and the phase error 0 error due to the frequency deviation.

The synchronous detector 106 uses co s A 0 and sin Δ 0 to add the received information symbol, Q ^f to the following equation (1)

And performs synchronous detection. The error correction decoder 107 performs an error correction decoding process on the synchronous detection output signal and decodes transmission data.

The timing error integrator 111 integrates the difference between the reference timing interval detected by the searcher 103 and the regular reference timing interval, and uses the integrated value as a frequency pull-in control signal to control the clock signal generator (VC-TCX0) 112 Input to the control voltage control unit 110. As described above, the matched filter of Searcher 103 calculates the correlation value between the timing identification spreading code (known) transmitted by the base station and the data sequence received from the base station, and calculates the peak position of the correlation value. , The reference timing of the base station is detected. When the frequency is initially pulled in, the terminal's peak frequency does not match the base station's reference peak frequency, and there is a frequency deviation. In addition to this frequency deviation, the reference timing detected as shown in FIG. 3, for example, the interval of the frame timing does not coincide with the regular reference timing interval of 10 ms e c and includes a time error Te-MF. The timing error integration section 111 integrates the time error Te-MF, and inputs the integrated value to the control voltage control section 110 as a frequency pull-in control signal.

The DLL correlation value integration unit 113 integrates the DLL correlation value R (τ), and inputs the integrated value to the control voltage control unit 110 of the clock signal generation unit (VC-TCX0) 112 as an AFC control signal. The DLL circuit 104c is to detect the deviation of the despreading timing of ± 1/2 chip or less due to fading, movement, frequency fluctuation, etc., but if there is a fixed frequency deviation, as shown in FIG. Includes the DC component CNTe-DLL in the DLL correlation value R (). Then, the DLL correlation value integration unit 113 integrates the DLL correlation value R (τ) to obtain the DC component CNTe-DLL. Therefore, this DC component is input to the control voltage control unit 110 as an AFC control signal.

The VC0 clock signal generator (VC-TCX0) 112 outputs a terminal reference clock signal having a frequency corresponding to the control voltage output from the control voltage controller 110. The PLL unit 114 generates a local frequency signal of the radio unit and outputs a baseband master clock signal CLK. The terminal reference timing generator 115 generates various timing signals based on the baseband master clock signal CLK. Generates a click signal and inputs it to each part of the terminal. The AFC control unit 116 controls the phase compensation unit 105, the timing error integrator 111, and the DLL correlation value integrator 113 to control the frequency of the terminal's peak signal.

(B) Outline of AFC control

The searcher 103 matched filter calculates the correlation value between the timing identification spreading code transmitted by the base station and the data string received from the base station when the power is turned on or when the mobile station returns from the outside of the service area to the service area. The base station's reference timing is detected based on the peak position of the value. Initially, the terminal clock frequency and the base station reference clock frequency do not match, and there is a frequency deviation. Due to this frequency deviation, the interval of the detected reference timing does not match the interval of the normal reference timing, and a time error is included. The timing error integrator 111 integrates the time error Te-MF.

The AFC control unit 116 inputs the integrated value output from the timing error integration unit 111 to the control voltage control unit 110 as a frequency pull-in control signal at the time of initial frequency pull-in immediately after power-on or immediately after returning from outside the service area to the service area. I do. The control voltage controller 110 controls the frequency of the clock signal output from the clock signal generator 112 based on the integrated value so that the time error Te-MF of the reference timing caused by the frequency deviation becomes zero. According to this feedback control, the clock frequency of the terminal can be quickly drawn to a frequency at which AFC control based on the phase error Δ0 output from the phase compensation section 105 is possible. As mentioned above, the time required for the initial pull-in of the AFC control can be reduced. · · · First stage AFC control

When the initial pull-in of the terminal clock frequency is completed in the first-stage AFC control, the AFC control unit 116 inputs the phase error ΔΘ output from the phase compensation unit 105 to the control voltage control unit 110 as an AFC control signal. The phase error Δ Θ is the signal point position vector of the received pilot symbol on the j j plane and the ideal signal point position of the known pilot symbol. The control voltage control unit 110 controls the frequency of the clock signal output from the clock signal generator 112 so that the phase error ΔΘ becomes zero. This feedback control allows the terminal clock frequency to match the reference clock frequency of the base station with the required accuracy, and the accuracy of the reference timing referenced by the searcher 103 is increased (the time error Te-MF in FIG. 3). = 0), and the timing deviation on the time axis is corrected. In addition, the phase of the base station side spreading code can be detected with an accuracy within one chip (synchronous acquisition). · · · Second stage AFC control

When the re-synchronization is acquired by the second-stage AFC control, the AFC control unit 116 stops the operations of the timing error integrator 111 and the phase compensator 105 and sets their outputs to zero, instead of the DLL. The circuit 104c and the DLL correlation value integration unit 113 are activated. As described with reference to FIGS. 13 and 14, the DLL circuit 104c controls the phase of the despreading code based on the DLL correlation value R () (synchronous tracking). Further, the DDL correlation value integration section 113 detects a DC component CNTe-DLL of the DDL correlation value R (τ), and inputs the DC component to the control voltage control section 110 as an AFC control signal. The control voltage control unit 110 controls the terminal's peak frequency so that the DC component of the DDL correlation value R (τ) becomes zero. As described above, it is possible to correct the frequency fluctuation due to a change in the temperature / propagation environment and the like, thereby suppressing the frequency deviation width to a small extent, and to correct the fixed frequency deviation. As a result, the period of the AFC control (the second-stage AFC control) performed by operating the matched filter and the phase compensation unit can be lengthened, and the number of times can be reduced to reduce power consumption. .

· · · Third-stage AFC control

The AFC control unit 116 stops the operation of the Dl 1 circuit 104c and the DLL correlation value integration unit 113 after performing the third-stage AFC control for a predetermined time, and starts the operation of the phase compensation unit 105 instead. Performs normal AFC control based on the phase error Δ ø (the second-stage AFC control). When the correction of the frequency error in the second-stage AFC control is completed, the third-stage AFC control is performed. Thereafter, the second and third steps of the AFC control are repeated.

Further, the AFC control unit 116 monitors the output voltage of the DLL correlation value integration unit 113 in the third-stage AFC control, and immediately executes the second-stage AFC control when the voltage value exceeds the set value. To correct the frequency error. As described above, the frequency error can always be kept within the set value. (C) Details of AFC control

As the AFC control operation, when the power is turned on or when returning from the outside of the service area to the service area, before the synchronous detection becomes possible, the rough AFC control based on the error Te-MF of the timing information from the searcher 103 (the first stage) AFC control) to pull in the clock frequency to the level that enables synchronous detection. Then, based on the information of the phase error ΔΘ from the phase compensator 105, the clock frequency is drawn with high accuracy so that the click frequency matches the reference clock frequency of the base station (AFC in the second stage). control). After the frequency is pulled down to the reference clock frequency, in order to suppress power consumption, the operation of the searcher is stopped, the DLL circuit 104c is started up instead, and the despreading timing correction information (DLL correlation value) output from the DLL circuit is output. R (τ)) to perform AFC control (AFC control in the third stage). In this third-stage AFC control, it switches to the regular second-stage AFC control periodically or by detecting an alarm state before demodulation is disabled. Thereafter, the second and third stages of AFC control are repeated.

(a) First stage AFC control

FIG. 5 is a timing chart for explaining the first stage AFC control operation of the present invention, and shows a case where reference timings of three base stations are detected. (1) shows the lower signal frame (broadcast channel frame) from the base station, and (2) shows the time slot configuration. (3) is the reference timing (time slot) of the terminal, (4) to (6) are the reference timings of base stations A, B, and C detected in the searcher, and (7) is the base stations A, B, and C. (8) is the detection reference timing of base stations A, B, and C, τ-Α, τ-Β, τ-C, and the delay time from terminal reference timing Τ-sA, T-sB , T-s C. (9) shows the error of the terminal reference timing, (9-1) shows the absolute reference timing of the base station, and (9-2) shows the terminal reference timing relative to the absolute reference timing. is there.

In order to demodulate data from a base station, a CDMA mobile communication terminal needs to accurately specify the phase of a spreading code. However, if the frequency is not synchronized between the terminal and the base station, the reference frequency of the terminal has an error of a few ppm (2 to 3 ppm) with respect to the reference frequency of the base station. In TDMA systems such as PDC and PHS, such errors are not a problem for pull-in, but some measures should be taken for CDMA. There is a need. To increase the specific value, if the chip rate / frame period is 3.84 MHz (= 10 ms), a shift of 0.12 chip / frame will occur if there is an error of 3 ppm. If it takes four frames to process, an error of about 1/2 chip occurs, and it can no longer be treated as meaningful data. For this reason, the searcher 103 with the matched filter configuration in Fig. 1 is implemented in the initial synchronization pull-in, but the detection timing of each base station detected is as shown in (8) and (9) in Fig. 5. Flows over time.

The matched filter can instantaneously calculate the correlation value of two code strings at a predetermined timing by one operation, but has the disadvantage of increasing the circuit size and Z power consumption. Even when a matched filter is used, it is necessary to take an average of the correlation values in order to increase the accuracy of the measurement. The time gets longer. As described above, the conventional technology using the matched filter has a problem that the initial synchronization pull-in time is long, the power consumption is large, and the life of the battery is short!

In the present invention, the flow of the peak timing (reference timing) of the correlation value calculated by the searcher 103 is quantitatively measured, and rough frequency adjustment is performed using the result. This enables AFC control (second-stage AFC control) using the pilot data after despreading immediately after the power is turned on or after returning to the service area, thereby shortening the initial pull-in time.

In general, the base station oscillates at the radio carrier frequency and the baseband frequency. Therefore, the frequency error between the terminal clock frequency and the base station reference clock frequency appears as a flow on the time axis of the matched filter detection timing as shown in (9) of FIG. In other words, based on the reference time of the terminal, the time difference τ ((8) in Fig. 5) at which the peak of the correlation value is obtained is observed differently from the actual detection interval. Figure 5 shows a state in which three valid pilots are being received.Each of them is affected by Doppler shift due to movement.However, by averaging information from multiple base stations, the effect is reduced. Can be eased.

The detection of the timing error, which is a problem here, can be easily realized by a counter that operates at a rate of about eight times the chip rate. To give a concrete example

Chip rate: 4MHz Frequency error: + 3ppm

Measurement interval lms with 8 times oversample

Comparing the counter values for 200 times (= 0.2 seconds) under the condition, the count value is smaller by -19 than the case of the frequency error force SO. By the way, in case of -3P PD1, it is +19. Actually, although the terminal standards fluctuate, the timing of receiving pilots from the base station seems to be shifted. This is equivalent to that the fluctuation of the terminal is counted by the reference clock of the base station. In this procedure, the timing error integrator 111 detects and integrates the frequency error, and controls the clock signal generator (VC-TC X0) 112 to correct the detected error. The frequency error with respect to the reference cook signal can be reduced.

Although it is impossible to achieve the final required accuracy (less than 0.1 ppm) by the above method, it is necessary to pull down the clock frequency to a level that allows AFC control (second stage AFC control) by complex arithmetic. After that, the second stage AFC control can be used to control the terminal clock frequency at high speed to the required accuracy.

(b) Second stage AFC control

The second stage AFC control will be described with reference to FIG. In Fig. 6 (Α), each symbol is mapped on the i-jQ plane at a position, where 1 corresponds to 1 and 0 corresponds to 1. If the amplitude of the input is constant and the frequencies on the transmitting and receiving sides (carrier frequency / baseband frequency) match, the signal point of each symbol sticks to one point as shown in Fig. 6 (A). If the values of each symbol are known, all points can be collected into one point by matrix operation (phase rotation). Fig. 6 (B) shows an example of collection in the first quadrant. For example, if it is (1, 0), it will be rotated by (-π / 2). Actually, the vector rotates from the dotted line position as shown in Fig. 6 (C) due to the influence of fogging and frequency error due to movement. After all, the received signal point position vector (Rq, Qi) is calculated using the actual signal point position vector (Dq, Di) as

ίϋΛ '

.

(Dq ( ² )

The frequency error can be corrected by this calculation. However, the phase error ΔΘ is the phase error 0 move due to temperature / fading / multipath and the frequency deviation This is the sum of the phase error 0 error due to the difference, but converges because the frequency error component 0 error is dominant. From equation (2), if Di = Dq, the phase error △ 次 is

ΔΘ = tan ^_1 (Rq-Ri) / (Rq + Ri) (3)

Can be obtained by Here, Ri is the I component of the received electric field, and Rq is the Q component of the received electric field. Actually, instead of calculating equation (3), Δ リ is obtained from the output of the memory whose amplitude is the amplitude of the standardized I and Q components.

By the way, if the phase error △ 0 at the measurement interval becomes large, the position on the I-jQ plane cannot be specified, and the calculation itself becomes impossible. For example, when the measurement interval is 1 ms, if the error is 1 ppm, the rotation angle exceeds 2π, and the calculation cannot be performed, and AFC control cannot be performed. For this reason, the initial pull-in of the frequency is performed in the first-stage AFC control so that the AFC control using the despread pilot data (the second-stage AFC control) becomes possible.

If AFC control using pilot data after despreading becomes possible in the first-stage AFC control, AFC control section 116 activates phase compensation section 105. The phase compensator 105 calculates the phase error Δ0 by the above method and inputs the calculated phase error Δ0 to the control voltage controller 110. The control voltage controller 110 controls the frequency of the clock signal output from the clock signal generator 112 so that the phase error Δ Δ becomes zero. In accordance with this feedback control, the clock frequency of the terminal can be brought to the required accuracy (= 0.1 ppm or less), whereby the DLL circuit 104c can adjust the phase of the base station side spreading code with an accuracy within one chip. Detection becomes possible (synchronous acquisition).

(c) Third stage AFC control

Even after the frequency has been pulled down to the required accuracy (= 0.1 ppm or less), the reference frequency of the terminal fluctuates due to temperature changes and so on, so it is necessary to continue the second-stage AFC control. However, complex operations in the AFC control in the second stage are performed by a DSP (digital signal processor), and the reference timing detection operation is performed by a multi-filter, resulting in considerable current consumption. Need. Therefore, it is not efficient to always perform the second-stage AFC control in order to keep processing load and power consumption low. Therefore, it is conceivable to perform AFC control in some way (for example, DLL control) that consumes a small amount of current, and then perform AFC control in the second stage at a predetermined cycle. You. In this case, it is not preferable to perform the second-stage AFC control in a short cycle for the same reason as described above, and it is preferable to perform the AFC control in a long cycle.

As described above, in the present invention, after the frequency is pulled down to the required accuracy (= 0. Lppin or less), the phase of the despreading code is controlled by the DLL, and the DLL correlation value R (τ AFC control is performed using the integrated value of (2), thereby increasing the period for performing the second-stage AFC control. Also, in the present invention, when approaching a state where the phase control of the despreading code by the DLL becomes impossible, an alarm is output and the second-stage AFC control is forcibly performed, and the phase control by the DLL becomes impossible. Avoid the situation that becomes.

FIG. 7 is an explanatory diagram of the S-carp in the DLL. (A) shows the case where the frequency deviation is zero, (B) shows the case where the frequency deviation is ten, and (C) shows the case where the frequency deviation is one. DLL control corrects the deviation of the despreading timing (caused by fading, movement, frequency fluctuation, etc.) of ± 1/2 chip or less, but the fixed frequency deviation of the terminal clock signal is It becomes visible if the control amount (DLL correlation value) is integrated over a long period. This is because, unlike other factors, the deviation direction is always constant. When the frequency deviation is +, the output of the DLL correlation value integration unit 113 is the DC component CNTe-DLL of FIG. The AFC control unit 116 inputs the output signal of the DLL correlation value integration unit 113 to the control voltage control unit 110, and controls the clock frequency so that DC component = 0. The DC component is monitored, and when the output signal value reaches a set level and approaches a dangerous state in which the DLL cannot control the phase of the despreading code, an alarm is output and the second-stage AFC control is performed. . Executing AFC control switching based on such an alarm can lengthen the period of the second-stage AFC control that is performed periodically, and reduce power consumption.

As described above, when the second stage AFC control enters the synchronous capture state, the AFC control unit 116 stops the operations of the timing error integrator 111 and the phase compensator 105, sets their outputs to zero, and replaces them. Then, the DLL circuit 104c and the DLL correlation value integrator 113 are activated. The DLL circuit 104c controls the phase of the despread code based on the DLL correlation value R (τ) (synchronous tracking). Further, the DDL correlation value integration section 113 detects a DC component of the DDL correlation value R (r), and inputs the DC component to the control voltage control section 110 as an AFC control signal. The control voltage control unit 110 controls the clock frequency of the terminal so that the DC component of the DDL correlation value R (τ) becomes zero. (D) Overall processing flow

FIG. 8 is an overall processing flow of the present invention. When the mobile communication terminal is turned on or when the mobile communication terminal returns from the service area to the service area, the AFC control unit 116 activates the searcher 103 and the timing error integrator 111, and the searcher performs a timing search to specify the reference timing of the base station. (Step 20 and Step 202). In this case, the searcher 103 performs a timing search for each of the n paths M times, and finds that the time difference (M-1) -To between the M-th timing ₀ and the first timing To and the frequency deviation Time difference when 0 and difference between and [(Μ-1) · Τ. -T _M — Determine the frequency error by averaging the η paths of J. Note that η may be 1.

The timing error integrator 111 integrates the average of the time differences, and inputs the integrated value to the control voltage controller 110 as a frequency pull-in control signal. The control voltage controller 110 controls the frequency of the clock signal output from the clock signal generator 112 based on the integrated value so that the time error of the reference timing caused by the frequency deviation becomes zero. As described above, rough frequency correction is performed, and the clock frequency of the terminal is drawn to a frequency at which the second-stage AFC control for controlling the terminal based on the phase error ΔΘ is possible (Step 203). … First stage AFC control

When the rough frequency correction of the terminal's peak frequency is completed, the AFC control unit 116 activates the inverse diffusion unit 104 and the phase compensation unit 105. Despreading section 104 starts despreading processing based on the reference timing detected by the searcher, and demodulates the I and Q components of the pilot symbol (step 204). The phase compensation unit 105 calculates a phase error ΔΘ based on the I and Q components of the pilot symbol, and inputs the phase error ΔΘ to the control voltage control unit 110 as an AFC control signal. The control voltage control unit 110 controls the frequency of the clock signal output from the clock signal generator 112 so that the phase error ΔΘ becomes zero. This feed-pack control allows the clock frequency of the terminal to be as high as required (less than 0.1 ppm), and the DLL circuit 104c can detect the phase of the base station side spreading code with an accuracy within one chip. (Step 205).

AFC control in the second stage With the above control, if the terminal's peak frequency falls within the required accuracy, data can be demodulated.Synchronous detection unit 106 performs synchronous detection. Perform an error correction decoder 107 executes error correction / decoding processing based on the synchronous detection output signal to decode transmission data (step 206). At the time of data demodulation, the AFC control unit 116 stops the operations of the searcher 103 and the phase compensation unit 105 to make their outputs zero, and starts the DLL circuit 104c and the DLL correlation value integration unit 113 instead. The DLL circuit 104c controls the phase of the despreading code based on the DLL correlation value R (τ), and inputs the DLL correlation value R (T) to the DDL correlation value integration unit 113. The DDL correlation value integration unit 113 detects the DC component by integrating the DDL correlation value R (τ), and outputs the DC component as a fixed frequency deviation (step 207). The control voltage control section 110 uses the integrated output of the DDL correlation value integration section 113 as an AFC control signal, and controls the clock frequency of the terminal so that the integrated output becomes zero (step 208). As described above, the fixed frequency deviation can be corrected. · · · Third-stage AFC control

The AFC control unit 116 checks whether the third-stage AFC control has been performed continuously for the set time, in other words, checks whether the second-stage normal AFC control start time has come (step 209). If “Yes”, the process returns to step 205 to restart the normal AFC control of the second stage. If “No”, the integrated output of the DDL correlation value integration unit 113 exceeds the set value and DL L It is checked whether or not the approach to a dangerous state in which the phase control of the despreading code by using is impossible (step 210). If “Yes”, return to step 205 and execute the normal AFC control of the second stage. If “NoJ”, check if the call has ended (step 211). If not, go to step 207 and after. The AFC control of the third stage is continued, and when the call ends, the power save is performed (step 212), and the AFC process ends.

As described above, according to the present invention, it is possible to greatly reduce the AFC pull-in time at the time of power-on or recovery from out of service area without adding special hardware, and to reduce the number of AFC activations during a call to the minimum required. It is possible to limit to the limit. As a result, the transition to the standby state is quickened, and the power consumption is reduced and the battery life is prolonged.

Claims

The scope of the claims

1. The reference timing of the base station is detected by a correlation operation using a matched filter, a despreading code is generated based on the detected reference timing, and the received signal is despread using the despreading code to transmit data. In a clock frequency controller of a CDMA mobile communication terminal that demodulates

An AFC controller that controls the clock frequency of the CDMA mobile communication terminal to match the reference clock frequency of the base station;

A time error monitoring unit that outputs a signal corresponding to a time error between the reference timing detected by the correlation operation and the normal reference timing,

A clock signal generating unit for generating a click signal of a CDMA mobile communication terminal,

The AFC control unit is configured to input a time error signal output from the time error monitoring unit to the clock signal generation unit when the clock frequency is initially pulled in after power-on or after returning from outside the service area to the service area. Control the

A clock frequency control device, characterized in that:

2. The time error monitoring unit integrates the time error and inputs the integration result to the clock signal generation unit,

2. The click frequency control device according to claim 1, wherein: .

3. At the time of the initial pull-in of the clock frequency, the matched filter calculates a correlation between the received signal and the timing identification spread code included in the lower signal from the base station, and based on the peak timing of the correlation value, 2. The clock frequency control device according to claim 1, wherein timing is detected. '

4. A despreading circuit for despreading a predetermined symbol periodically included in the lower signal from the base station,

A phase error calculator for calculating a phase error of a rotation angle of the symbol on the I-jQ plane and outputting a signal corresponding to the phase error;

After the completion of the initial pull-in of the clock frequency, the AFC control unit inputs a phase error signal to the clock signal generation unit, and matches the clock frequency with the reference clock frequency. To control,

2. The click frequency control device according to claim 1, wherein:

5. DLL circuit that controls the phase of the despreading code by DLL (De laye d Loc ke d Loo p) control,

A DLL correlation value averaging unit that outputs an average value of DLL correlation values output from the DLL circuit, wherein the AFC control unit matches the reference frequency with the reference frequency with required accuracy. At this time, a signal corresponding to the phase error output from the phase error calculation unit is set to zero, and instead, the average value is input to a clock signal generation unit, and the clock frequency is controlled so that the average value becomes zero.

5. The clock frequency control device according to claim 4, wherein:

6. A means for monitoring whether or not the average value of the DLL correlation value is equal to or greater than a set value. The AFC control unit is configured to, when the average value is equal to or greater than the set value, change the phase error signal to the clock signal. Input to a generator to control the clock frequency to match the reference clock frequency;

6. The click frequency control device according to claim 5, wherein:

7. The AFC control section periodically inputs the phase error signal to the peak signal generation section and controls the peak frequency to be equal to the reference peak frequency, The clock frequency control device according to claim 5, wherein the AFC control is performed by inputting the average value to the clock signal generation unit.

8. In CDMA mobile communication terminals,

A reference timing detection unit that detects a reference timing of the base station by a correlation operation using a matched filter,

A clock frequency control unit that generates a peak signal of the CDMA mobile communication terminal and matches a frequency of the peak signal with a reference clock frequency of the base station;

A despreading code generator that generates a despreading code based on the detected reference timing and clock signal;

A demodulation unit that demodulates transmission data by despreading a received signal using the despreading code,

The mouth frequency control unit,

Match the peak frequency of the CDMA mobile communication terminal with the reference peak frequency of the base station. AFC control section, which controls

A time error monitoring unit that outputs a signal corresponding to a time error between the reference timing detected by the correlation operation and the normal reference timing of the base station,

A clock signal generator for generating a clock signal for a CDMA mobile communication terminal,

The AFC control unit is configured to input a time error signal output from the time error monitoring unit to a clock signal generation unit at an initial pull-in of a clock frequency performed after power-on or after returning from outside the service area to the service area. To control the clock frequency,

A CDMA mobile communication terminal.

9. The time error monitoring unit integrates the time error, and inputs the integration result to the clock signal generation unit,

9. The CDMA mobile communication terminal according to claim 8, wherein:

10. At the time of the initial pull-in of the clock frequency, the matched filter calculates the correlation between the received signal and the timing identification spread code included in the lower signal from the base station, and based on the peak timing of the correlation value. 9. The CDMA mobile communication terminal according to claim 8, wherein the reference timing is detected.

1 1. The clock frequency control unit includes:

A despreading circuit for despreading predetermined symbols periodically included in the lower signal from the base station,

A phase error calculator for calculating a phase error of the rotation angle of the symbol on the I-j Q plane and outputting a signal corresponding to the phase error;

The AFC control unit further comprises: after completion of the initial pull-in of the clock frequency, inputs a phase error signal to the peak signal generation unit, and matches the peak frequency with the reference clock frequency. To control,

9. The CDMA mobile communication terminal according to claim 8, wherein:

1 2. The clock frequency control unit includes:

A DLL circuit for controlling the phase of the despreading code controlled by a DLL (Delayed Locked Loop) control, and a DLL correlation value averaging unit for outputting an average value of DLL correlation values output from the DLL circuit; The reference frequency is determined by the reference frequency with the required accuracy. When the frequency coincides with the clock frequency, a signal corresponding to the phase error output from the phase error calculation unit is set to zero, and the average value is input to a clock signal generation unit instead, and the clock is set so that the average value becomes zero. Control the frequency,

12. The CDMA mobile communication terminal according to claim 11, wherein:

1 3. The clock frequency control unit

Means for monitoring whether or not the average value of the DLL correlation values has exceeded a set value;

The AFC control unit, when the average value is equal to or more than a set value, inputs the phase error signal to the peak signal generation unit and converts the peak frequency to the reference threshold. Control to match the clock frequency,

13. The CDMA mobile communication terminal according to claim 12, wherein: