JP2917990B2 - Pseudo-noise code generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-noise code generator used for a spread spectrum signal demodulator used for satellite communication or the like.

[0002]

2. Description of the Related Art GPS receives radio waves from three or more satellites,
This is a system that measures the position by measuring the distance from the satellite to the receiving point. In a GPS receiver, a spread spectrum signal demodulator is used. In GPS, the data edge timing is set to 1 ms for distance measurement.
It is determined with the accuracy of ec. When the spectrum despreading unit of the GPS receiver is configured by a digital method,
Demodulated data can be represented by a digital correlation code. In addition, in order to perform positioning by GPS, the carrier and code of a satellite used for positioning must be tracked.
Carrier tracking is performed by calculating a phase from the I-correlation value / Q-correlation value and calculating a tracking carrier frequency from the phase. Further, the code tracking is based on the I-correlation value
This is performed by calculating a code phase shift from the early and late values of the Q-correlation value.

In a pseudo-noise code generator used in such a spread-spectrum signal demodulator, a code (pseudo-noise) of a target phase is changed by changing the frequency of a clock for driving a shift register provided for generating a code. Sign).

[0004]

However, in the conventional pseudo-noise code generator, it is necessary to shift the phase to perform a code search. It had to wait until the phase was reached, which was time-consuming. In addition, one chip
Full code phase control was not possible. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problem, and enables a code (pseudo-noise code) of a target phase to be quickly set , and
It is an object of the present invention to provide a pseudo-noise code generation device capable of delay-controlling and outputting the phase of a generated code.

[0005]

A pseudo-noise code generator according to the present invention is a pseudo-noise code generator for generating a random pseudo-noise code at a constant period. The pseudo-noise code generator stores a first code having a predetermined phase . a first code register for, first corresponding to the first code stored in the first <br/> code register
A first shift register for storing the first data, the predetermined position
A second code register for storing a second code of the phase;
The second code stored in the second code register
Second shift register for storing corresponding second data
And T for extracting arbitrary bit information from the shift register
Generates an AP selection circuit and a code phase delay of less than one chip
Having a delay circuit for receiving a predetermined command signal,
First data corresponding to the first code stored in the first code register is stored in the first shift register, and second data stored in the second code register is stored in the first code register.
Second data corresponding to the second shift register.
Data and store them in the TAP selection circuit.
A pseudo noise code based on the first data and the second data.
And setting the phase of the set pseudo noise code to the delay circuit
And outputs the result after delay control .

[0006]

According to the present invention, when a predetermined command signal is received, the two codes stored in the two code registers are converted into two codes.
Each two corresponding data husband two shift registers
It s stored, and two of these by the TAP selection circuit
, A pseudo-noise code is set . Further delay times
Depending on the path, the phase of the set pseudo noise code
It is. Therefore, by loading the pseudo-noise code of the target phase state into the shift register, the comparison code can be immediately validated by inputting the command signal.

As a result, the pseudo-noise code of the target phase can be set quickly, and it is possible to cope with a case where the data of the shift register is to be changed quickly. Further, 1 for the set pseudo noise code
Delay the phase to cause a code phase lag of less than a chip.
The output can be controlled.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied in a GPS receiver will be described below with reference to the drawings. FIG. 1 shows the entire configuration of a GPS receiver, which is mounted on a vehicle. The GPS receiver includes an antenna 1, a high-frequency processing circuit 2, a spectrum despreading unit 3, and a positioning calculation microcomputer 4. The antenna 1 receives a radio wave transmitted from a GPS satellite. The high-frequency processing circuit 2 amplifies a signal received by the antenna 1 and converts the signal into a target frequency.

The spectrum despreading section 3 is for despreading and demodulating the spread spectrum signal, and the positioning calculation microcomputer 4 performs positioning (measurement of latitude and longitude) of the vehicle. The spectrum despreading unit 3 includes an A / D conversion circuit 5,
Two exclusive OR circuits 6 and 7 and a carrier NCO 8
, C / A code generator 9 and digital I-correlator 1
0, digital Q-correlator 11 and controller 12
It is composed of The A / D conversion circuit 5 receives the frequency-converted signal from the high frequency processing circuit 2 and binarizes the signal. The carrier NCO 8 generates a carrier having a 0 ° phase and a 90 ° phase of the target frequency by numerical control. The exclusive OR circuit 6 inputs the signal from the A / D conversion circuit 5 and the 0 ° phase carrier from the carrier NCO 8 and sets the output to “0” when both inputs match. That is, the 0 ° phase (in-phase) carrier component of the binarized received signal is canceled. In addition, the exclusive OR circuit 7 outputs A
The signal from the / D conversion circuit 5 and the carrier having a 90 ° phase from the carrier NCO 8 are input, and when both inputs match, the output is set to “0”. That is, the carrier component of the 90 ° phase (quadrature phase) of the binarized received signal is canceled.

The C / A code generator 9 outputs the C / A of the target phase.
Generate code. The digital I-correlator 10
The signal from the exclusive OR circuit 6 and the C / A code from the C / A code generator 9 are input, and every 1 msec,
A correlation value between a signal in which the 0 ° phase carrier component of the received signal is canceled and a C / A code generated in the receiver is simultaneously measured for a plurality of phases in half-chip units. The digital Q-correlator 11 is provided with an exclusive OR circuit 7.
And a signal obtained by inputting the C / A code from the C / A code generator 9 and canceling the 90 ° phase carrier component of the binarized received signal every 1 msec.
The correlation value with the C / A code generated in the receiver is halved
Simultaneous measurement is performed for multiple phases at chip increments.

The controller 12 uses the output values of the digital I-correlator 10 and the digital Q-correlator 11 to perform C /
The A code generator 9 controls the carrier NCO 8. Then, the controller 12 demodulates the satellite data and measures a pseudo distance between the satellite and the receiver. The positioning calculation microcomputer 4 selects a satellite to be used for positioning, and instructs the controller 12 of the spectrum despreading unit 3 to perform data demodulation and measure a pseudo distance between the satellite and the receiver. Measure the positioning value.

FIG. 2 shows C of the spectrum despreading unit 3.
The specific configuration of the / A code generator 9 is shown. 2, the C / A code generator 9 includes a G1 code register 13, a G2 code register 14, and a 10-bit shift register 1.
5, a TAP selection circuit 17 and a delay circuit 18 are provided. The G1 code register 13 stores the G1 code from the controller 12, and the G2 code register 14 stores the G2 code from the controller 12. The 10-bit shift register 15 stores data corresponding to the G1 code from the G1 code register 13, and the 10-bit shift register 16 stores data corresponding to the G2 code from the G2 code register 14. TAP selection circuit 17
Receives a TAP command signal from the controller 12 and generates a C / A code based on each data of the 10-bit shift registers 15 and 16 corresponding to the command. Delay circuit 18
Receives the C / A code generated by the TAP selection circuit 17, delays the C / A code, and
Output to the correlator 11. The delay circuit 18 enables code phase control of less than one chip, and a delay instruction is sent from the controller 12.

Next, the operation of the thus configured GPS receiver will be described. FIG. 3 shows a positioning calculation routine executed by the positioning calculation microcomputer 4. FIG. 4 shows a spectrum despreading processing routine executed by the controller 12 of the spectrum despreading unit 3. The spectrum despreading routine includes a satellite acquisition routine and a satellite tracking routine. The satellite acquisition routine is shown in FIG. 5, and the satellite tracking routine is shown in FIG. The satellite tracking routine of FIG. 6 includes a data demodulation routine, a carrier tracking routine, and a C / A code tracking routine. The data demodulation routine is shown in FIG.
The carrier tracking routine is shown in FIG. 8, and the C / A code tracking routine is shown in FIG. The data demodulation routine in FIG. 7 includes a demodulation code determination routine in step 320, which is shown in FIG.

First, the processing up to the start of satellite tracking will be described. In FIG. 3, the positioning calculation microcomputer 4 performs step 1
In step 102, the optimum combination of satellites for positioning calculation is calculated, and in step 102, the Doppler shift amount of the target satellite and the received radio wave is instructed to the controller 12 of the spectrum despreading unit 3. Then, the controller 12 starts a satellite acquisition routine in step 200 of FIG. At the time of this satellite acquisition, the controller 12 determines whether or not reacquisition is performed in step 201 in FIG. And the controller 12
Performs a C / A code synchronous phase search process in step 202 in order to capture a satellite in accordance with an instruction from the positioning calculation microcomputer 4. In this process, first, the controller 12 sets the carrier NCO 8 and the C / A code generator 9. As a result, the carrier NCO 8 generates a frequency in consideration of the Doppler shift instructed by the positioning operation microcomputer 4.
In the C / A code generator 9, the code registers 13 and 14 and the shift registers 15 and 16 shown in FIG. At 17, the TAP of the satellite to be captured is selected, and C /
The A code is output to digital correlators 10 and 11.

Then, in FIG.
The radio wave transmitted from the PS satellite is received, and the high frequency processing circuit 2 amplifies the received signal and converts it into a target frequency. Further, the signal from the high frequency processing circuit 2 is binarized by the A / D conversion circuit 5 of the spectrum despreading unit 3, and the signal from the A / D conversion circuit 5 and the carrier NCO 8 by the exclusive OR circuit 6. And the 0 ° phase carrier component of the binarized received signal is canceled. Also, the exclusive OR circuit 7 performs A / D
Signal from conversion circuit 5 and 90 ° from carrier NCO 8
The phase of the received signal is compared with that of the
° The carrier component of the phase is canceled. In addition, 1
Every msec, the digital I-correlator 10 and the signal from the exclusive OR circuit 6 and the C / A code
The digital Q-correlator 11 measures the correlation value between the signal from the exclusive OR circuit 7 and the C / A code from the C / A code generator 9 while measuring the correlation value with the / A code. Is done.

Thereafter, the controller 12 of the spectrum despreading unit 3 operates the digital I-correlator 1 every 1 msec.
A correlation value is continuously obtained from the measurement results of 0 and the digital Q-correlator 11, and the sum (sum) thereof is used as the correlation value. Further, similarly, the C / A code generator 9 is controlled to measure each of the C / A code phases 0 to 1023 chips at 1/2 chip intervals as shown in FIG. Thereby, the reception C / A code and the C / A generated in the receiver are obtained.
The phase with which the code is synchronized is searched.

In this search, the synchronous phase search direction is the opposite direction in which the received C / A code phase is displaced during the search, as shown in FIG. That is, if the Doppler shift is plus, the direction is from “0” to “1023” chips, and if the Doppler shift is minus, “1023”.
The correlation value is measured in the direction from “0” chip to “0” chip. And
After performing the correlation measurement in this manner, the controller 12 of the spectrum despreading unit 3 performs step 20 in FIG.
In step 3, it is determined whether or not a correlation equal to or greater than the threshold is obtained (see FIG. 11). On the other hand, if a correlation equal to or greater than the threshold cannot be confirmed, the controller 12 proceeds to step 204 and outputs a signal to that effect to the positioning microcomputer 4. With this signal,
The positioning calculation microcomputer 4 changes the Doppler shift amount,
The controller 12 is instructed to search for the C / A code synchronization phase again, and thereafter, it repeats until a correlation equal to or greater than the threshold is obtained.

After detecting the C / A code synchronization phase, the controller 12 performs a C / A code synchronization confirmation process at step 205 to confirm the synchronization. This is based on the code phase for which synchronization is detected, for example, in the region Z1 in FIG.
The synchronous phase search is performed again as shown in
A correlation value within the region is obtained. However, the number of continuous measurement of the correlation value is made larger than the number of continuous measurement at the time of the C / A code synchronous phase search in step 202, and a more reliable check is performed. Thereafter, the controller 12 proceeds to step 2
If a correlation within the range of 06 (not less than the threshold value) is obtained, it is determined that synchronization has been confirmed, and the process proceeds to step 207. If the synchronization cannot be confirmed, the process proceeds to step 204 and a signal to that effect is output to the positioning microcomputer 4. With this signal, the positioning calculation microcomputer 4 changes the Doppler shift amount and instructs the controller 12 to perform the synchronous phase search again.

After confirming the synchronization phase of the C / A code in this way, the controller 12 proceeds to steps 208 to 2
At 11, a carrier search is performed. In this case, a carrier search is performed around the carrier of the Doppler shift instructed by the positioning calculation microcomputer 4 to a range where the carrier can be tracked. This carrier search is performed in two stages by changing the search step size as described below in order to search carriers in a wide frequency range in a short time. The correlation value of the carrier search of the first stage is calculated by the digital I-correlator 1 in step 208.
A correlation value is continuously obtained from the measurement results of 0 and the digital Q-correlator 11 and the sum is used.

As a result, when the C / A code is synchronized, as shown in FIG. 12, the correlation value is minimized at a period of 1 KHz with the carrier frequency error Δf centered on the correlation value at 0 Hz. The controller 12 sets the carrier NCO 8 every 1 KHz around the carrier of the Doppler shift instructed from the positioning operation microcomputer 4 using the correlation value, and determines the frequency with the strongest correlation to the spectrum despreading unit 3. Is predicted to be the carrier frequency of the signal input to. However, if the difference is equal to or smaller than the threshold value in FIG.

Subsequently, in the carrier search at the second stage in step 210, a value obtained by summing the measurement results of the digital I-correlator 10 and the digital Q-correlator 11 for 10 times each of 1 msec is used. I do. As a result, when the C / A code is synchronized, as shown in FIG.
It becomes minimum at z periods. Using the correlation value, step 2
The carrier NCO 8 is set every 100 Hz before and after the carrier frequency predicted by the carrier search of 08, and the frequency with the strongest correlation is the frequency of the carrier finally input to the spectrum despreading unit 3. Predict. However, if no correlation equal to or greater than the threshold value is obtained in step 210, it is determined that the carrier search has failed, and the positioning calculation microcomputer 4 is notified of this fact. The microcomputer 4 instructs the controller 12 to change the amount of Doppler shift and perform a synchronous phase search again.

The controller 12 thus operates as shown in FIG.
After processing the satellite acquisition routine at step 300, the satellite tracking routine at step 300 is executed. The satellite tracking performs data demodulation, carrier tracking, and code tracking as shown in FIG. In the data demodulation routine of FIG.
In step 311, it is determined whether the C / A code / carrier synchronization check flag FCL is “1”. Since FCL = 0 at the beginning, the process exits the routine of FIG. 7 and executes the carrier tracking routine of FIG. When the C / A code / carrier synchronization check flag FCL becomes "1" in the subsequent carrier tracking routine, it is determined that the carrier and the C / A code are synchronized, and the data is demodulated. At the time of data demodulation, since the spectrum despreading unit 3 is constituted by a Costas loop, the edge timing is determined by the timing when the sign of the I-correlation value changes from plus to minus or from minus to plus and the C / A code phase. it can. Then, as shown in FIG. 14, if the C / A code phase is other than the vicinity of the intermediate point (0.5 msec = 1023/2 chips), the sign of the I-correlation value is instantaneously changed, and 1 msec. The edge timing can be determined from the sign inversion timing of the I-correlation value measured every time and the C / A code phase. However, as shown in FIG. 15, when the C / A code phase is near the middle point, the sign of the I-correlation value measured when the input data is inverted becomes ambiguous, and the sign inversion timing of the I-correlation value and C If the edge timing is determined from the / A code phase, the possibility of erroneous detection is very high.

Therefore, when the C / A code phase is in the vicinity of the intermediate point, a threshold value (having a value of ± β centering on “0”) shown in FIG. 15 is provided for the I-correlation value measured every 1 msec. When an I-correlation value within the threshold range is detected, it is determined that the input data sign is inverted, thereby preventing erroneous detection of edge timing. Specifically, data demodulation is performed in the process of FIG. That is, step 320-1
In step 320-2, the I-correlation value is inverted.
It is determined whether the correlation value is within the threshold value (± β), and if it is within the threshold value, the sign is inverted with a delay of 1 msec in step 320-3.
If the I-correlation value deviates from the threshold, step 320-
In step 4, the direction of the phase of the C / A code is checked.
If it is between 11 chips, 1 ms at step 320-5
The sign is inverted with a delay of c. If the phase is between 511 chips and 1023 chips, the sign is immediately inverted at step 320-6.

However, when the C / N of the received signal is bad,
Since the fluctuation of the I-correlation value is large and it is difficult to determine the threshold value (± β), there is a high possibility that the edge timing is incorrect. Thus, in FIG. 7, the processing of steps 312 to 319 is added. FIG. 16 shows a functional block diagram for that purpose. That is, in FIG.
A timing counter 20, an edge timing data sampling unit 21, an edge timing determination unit 22, a demodulation data synchronization signal output unit 23, and a demodulation code determination unit 24. In addition, the edge timing sample section 21 has the configuration shown in FIG.
Is prepared, and the buffer has storage areas W1 to W20 obtained by time-dividing the bit length (20 msec) of the received data into 20 pieces.

First, unless the flag Fetk = 1 in step 312 in FIG. 7, the controller 12 (the data edge detection unit 19 in FIG. 16) surely determines the data edge timing in step 313 with an accuracy of less than ± 1 msec. In the state where the C / A code is synchronized, data edge detection is performed in step 314 to detect the sign inversion timing of the I-correlation value, and the result is sent to the edge timing data sampling section 21 in FIG. The counter 20 is started. Thereafter, the edge timing data sampler 21 signals the data edge detection in step 315 and, as shown in FIG. 18, synchronizes the I-correlation value with the timing counter 20 in a period of 20 msec as shown in FIG. Save and add to W1 to W20.

However, the 20 I-correlation values to be saved are only those when a data edge is detected, and when saving, the codes are matched so that the previous data is not canceled. For example, suppose that the 20 I-correlation values for which the data edge is detected for the first time are the falling edges, and if the sampled 20 I-correlation values are the falling edges for the next time, 20 I sampled if it is the rising edge of the edge.
-Invert the sign of the correlation value and take the sum with the previous one.

Thus, an average I-correlation value of the edge timing is obtained. When the creation of the I-correlation value histogram is completed in step 316, the flag Fetk is set to 1 in step 317. Further, since the flag Fetk = 1 in step 312, the controller 12 proceeds to step 312.
Proceed to 18. The controller 12 (the edge timing determination unit 22 in FIG. 16) determines the edge timing based on the I-correlation value sample result in step 317, and resets the timing counter 20. Thus, C / N
Edge timing can be reliably obtained even in a poor condition. Subsequently, the controller 12 (the demodulated data synchronizing signal output unit 23 in FIG. 16) adjusts the timing counter to output a synchronizing signal of data to be demodulated from the period 4
A rectangular wave of 0 msec is output several times. Thereafter, data demodulation is performed according to the algorithm shown in FIG. 10 (steps 318, 319, 320 in FIG. 7).

Next, carrier tracking and code tracking are performed.
Carrier tracking is for keeping the carrier searched at the time of satellite acquisition in a synchronized state and maintaining synchronization. These operations are realized by PLL control by the controller 12. In the carrier pull-in process of the PLL control, the carrier synchronization flag is FCL = 0.
Thus, in the carrier tracking process of FIG. 8, in step 334, a carrier phase error is obtained from the I-correlation value and the Q-correlation value. Subsequently, in step 335, a carrier frequency to be followed is calculated from the carrier phase error value, and the carrier N
Feed back to CO8. Further, step 336
In step 337, FCL = 1 is set in step 337 if synchronization is determined from the carrier phase error.

The carrier phase error used for the PLL control can be calculated using the I-correlation value and the Q-correlation value. However, as shown in FIG. 19, the I-correlation value measured when the input data code switches is smaller than usual even when the carrier and the C / A code are synchronized. This becomes remarkable when the C / A code phase is near the midpoint. In such an abnormal correlation value, the result of calculating the carrier phase error also becomes an abnormal value, and the carrier frequency fed back to the carrier NCO 8 fluctuates greatly even after carrier synchronization as shown in FIG. There is. Therefore, after detecting the carrier synchronization, the controller 12 compares the threshold value with the correlation value used in the phase error calculation in step 333 if FCL = 1 in step 332 at the control timing in step 331 in FIG. .

Only when the absolute value of the "I-correlation value" is equal to or larger than the threshold value (only when it is considered normal), a carrier phase error is obtained from the I and Q correlation values in step 334, and step 335 Calculates the carrier frequency from the carrier phase error and feeds it back to the carrier NCO 8. As a result, there is no such thing as shown in FIG.
Synchronization is maintained as shown in FIG.

A similar operation is performed for C / A code tracking. That is, while maintaining the synchronization of the C / A code is performed by the DLL control, before the DLL control, when the control timing is the control timing in the step 341 in FIG. 9, the correlation degree of the synchronization phase (the correlation degree of the punctual) is determined in the step 342. Is determined. In other words, the absolute value of the “correlation value” for several times is compared with the threshold value to determine whether the correlation value is equal to or greater than the threshold value. Calculate the code phase error by the accompanying DLL control,
In step 344, feedback is made to the C / A code generator 9 to correct the code from the code phase error. By performing the above operations sequentially, the synchronization can be stably maintained as shown in FIG. 22 without the situation shown in FIG.

Next, the processing at the time of positioning will be described. The microcomputer 4 for position calculation calculates data of three or more satellites and a pseudo distance (C /
Positioning is started by collecting (A code phase).
In order to collect the pseudo-range after data collection, the positioning calculation microcomputer 4 measures the pseudo-range in step 104 in FIG. 3 and calculates the Doppler shift amount of the carrier input to the spectrum despreading unit 3 based on the value obtained during tracking. The C / A code phase is predicted, and the controller 12 is instructed to re-acquire. The controller 12 sets the carrier NCO 8 and the C / A code generator 9 according to the instruction of the positioning operation microcomputer 4, and performs the C / A by the same processing as step 205 in FIG.
Check code synchronization and check code phase synchronization again.

Further, after confirming the code phase synchronization, the controller 12 performs the same carrier search as in step 210 in FIG. At this time, the carrier search 2
The second method is adopted, but the search range is made narrower than that at the time of capturing. If a correlation equal to or larger than the threshold is obtained, it is determined that the carrier search has been performed. Thereafter, the controller 12 sets the carrier in a synchronized state as in the case of capturing, measures the pseudo distance by maintaining the synchronization of the C / A code, and notifies the result to the positioning calculation microcomputer 4. The positioning calculation microcomputer 4 calculates a positioning value in step 105 in FIG.

As described above, in this embodiment, the carrier NCO
8. Exclusive OR circuits 6, 7 (carrier component removing means)
, Carrier components are removed from the spread spectrum signal received by the antenna 1, and the signals from the exclusive OR circuits 6, 7 and the C / A code generation are performed by the digital correlators 10, 11 (correlation value detecting means). Vessel 9 (of the present invention
Pseudonoise the C / A code from the corresponding to the code generator) is compared with the chromatic <br/> signal that to detect the correlation value of the two signals, further, the controller 12 (data acquisition unit, inversion timing Detecting means) samples a plurality of correlation values obtained by time-dividing the bit length of the received data into a plurality of times, adds each sampled value, and calculates the received data from the added correlation value corresponding to the bit length of the received data. Is detected. That is, in the ring buffer of FIG. 17, the storage areas W1 to W
20 are prepared, and a plurality of sampling values of the bit length of the received data are added to each of the storage areas W1 to W20 and input.
The inversion timing of the received data is detected from the value of each storage area (the histogram in FIG. 18), and thereafter, data demodulation is performed at the inversion timing (edge timing). As a result, a large number of samplings are performed at the bit length of the received data and smoothed to obtain a stable value.

When the digital component is inverted, as in the process of step 333 in FIG. 8 for carrier tracking and the process of step 342 in FIG. 9 for C / A code tracking, the controller 12 (determination means) determines the correlation. It is determined whether or not the value is within a predetermined range. If the value is not out of the range, the value is validated. That is, the steps 334, 3 in FIG.
35 and the step 34 in FIG.
3,344 code phase arithmetic processing is not performed. As a result, if the data is inverted at the midpoint of the C / A code phase, noise occurs and an erroneous control signal is generated.
The comparison between the correlation value and the threshold does not result in an erroneous control signal;

Further, as shown in FIG. 11, the code phase search direction is changed according to the prediction of the Doppler shift.
That is, if the Doppler shift is positive, the code phase is increased, and conversely, if the Doppler shift is negative, the code phase is decreased. As a result, a fast search can be performed based on the positional correlation between the signal generation source and the reception position.

Further, as shown in FIG. 12, a carrier frequency close to a true value can be searched with a high probability by performing a correlation measurement over a code cycle time (1 msec or more).
The resolution can be improved. As a carrier search method, as shown in steps 207 and 209 in FIG. 5, a search is performed in two stages, large and small, around the predicted value. Therefore, in order to improve the resolution, the first stage can roughly detect a wide range quickly and quickly, and the second stage can sample a narrow range and perform fine and accurate detection.

Further, the C / A code generator 9 shown in FIG.
By loading the G1 and G2 codes of the desired phase state into the shift registers 15 and 16, the codes can be immediately activated by inputting the reference signal. That is, it is possible to cope with a case where the data in the shift registers 15 and 16 needs to be changed quickly. Note that the present invention is not limited to the above embodiment. For example, in the above embodiment, demodulation was performed after edge timing detection. However, the positioning calculation microcomputer 4 collects I-correlation values and performs edge timing detection. And data demodulation may be performed in parallel. That is, save the I-correlation value,
Edge timing and data demodulation may be performed using the saved I-correlation value.

Further, instead of the routine (demodulation code determination routine) shown in FIG. 10, a routine shown in FIG. 24 may be used. That is, when the sign inversion of the correlation value is detected in step 320-1-1, if the C / A code phase is a chip between “0” and “511-α” in step 320-2-1, step 320 The sign is inverted by delaying 1 msec by -3-1, and if 511 + α ≦ phase <1023, step 3 is performed.
In step 20-4-1, the sign is immediately inverted, and if 511-α≤phase <511 + α, then in step 320-5-1, if the correlation value is within the threshold range, 1 msec in step 320-6-1.
The sign is inverted with a delay, and if it is out of the threshold, step 320
The sign is immediately inverted at -7-1.

[0040]

As described in detail above, according to the present invention,
Quickly set the target phase code (pseudo-noise code)
At the same time, the phase of the set code is delayed and output.
Can be .

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a GPS receiver.

FIG. 2 is a configuration diagram of a C / A code generator.

FIG. 3 is a diagram showing a positioning calculation routine.

FIG. 4 is a diagram showing a spectrum despreading processing routine.

FIG. 5 is a diagram showing a satellite acquisition routine.

FIG. 6 is a diagram showing a satellite tracking routine.

FIG. 7 is a diagram showing a data demodulation routine.

FIG. 8 is a diagram showing a carrier tracking routine.

FIG. 9 is a diagram showing a C / A code tracking routine.

FIG. 10 is a diagram showing a demodulation code determination routine.

FIG. 11 is a diagram illustrating a relationship between a code phase and a correlation value.

FIG. 12 is a diagram illustrating a relationship between a carrier error and a correlation value.

FIG. 13 is a diagram illustrating a relationship between a carrier error and a correlation value.

FIG. 14 is a diagram showing a relationship between input data, I-correlation value, and demodulated data with respect to time.

FIG. 15 is a diagram showing a relationship between input data, I-correlation value, and demodulated data with respect to time.

FIG. 16 is a diagram showing functional blocks.

FIG. 17 is a diagram showing a ring buffer.

FIG. 18 is a diagram illustrating a relationship between time and a correlation value.

FIG. 19 is a diagram showing a relationship between input data, I-correlation value, demodulated data, and phase error with respect to time.

FIG. 20 is a diagram illustrating a change in a carrier frequency.

FIG. 21 is a diagram illustrating a change in a carrier frequency.

FIG. 22 is a diagram illustrating a change in the C / A code phase.

FIG. 23 is a diagram illustrating a change in the C / A code phase.

FIG. 24 is a diagram illustrating another example of a demodulation code determination routine.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Antenna 6 Exclusive OR circuit which constitutes carrier component removing means 7 Exclusive OR circuit which constitutes carrier component removing means 8 Carrier NCO which constitutes carrier component removing means 10 Digital I-correlator as correlation value detecting means 11 Digital Q-correlator as correlation value detection means 12 Controller as data collection means, inversion timing detection means, determination means

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-218215 (JP, A) JP-A-63-250210 (JP, A) JP-A-61-280135 (JP, A) JP-A-2-218 218214 (JP, A) JP-A-63-132519 (JP, A) JP-A-60-177719 (JP, A) JP-A-2-77928 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04J 13/00 H03K 3/84

Claims (1)

(57) [Claims] 1. A pseudo-noise code generator for generating a random pseudo-noise code at a constant period, is stored in the first code register for storing a first code of a predetermined phase, to the first code register second code register for storing a first shift register for storing the first data corresponding to the first code, a second code having a predetermined phase
Data and the second code stored in the second code register.
Second shift register for storing corresponding second data
And TAP for extracting arbitrary bit information from the shift register
A selection circuit, 1 and a delay circuit for generating a code phase delay of less than a chip, when receiving a predetermined command signal, first data corresponding to the first code stored in the first code register Is stored in the first shift register, and the second code register is stored in the first shift register.
Second data corresponding to the second code stored in the register.
Is stored in the second shift register, and the TAP selection is performed.
The stored first data and second data
A pseudo noise code is set from the data, and the set pseudo noise is set.
A pseudo-noise code generator , wherein the phase of a sound code is delayed and output by the delay circuit .