JP3826808B2 - Demodulator and receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a demodulator that demodulates a spread spectrum signal, and a receiver to which the demodulator is applied, and receives a signal from a satellite in a so-called GNSS (Global Navigation Satellites System) and calculates its position and velocity. The present invention relates to a receiving device.
[0002]
[Prior art]
In recent years, GNSS systems that measure the position of a moving object on the ground using an artificial satellite are becoming widespread. As this GNSS system, for example, there is a global positioning system (hereinafter referred to as GPS). In this GPS system, a GPS receiver that receives signals from GPS satellites receives signals from at least four GPS satellites, calculates the position of the GPS receiver based on the received signals, and It is a basic function to notify to.
[0003]
In other words, the GPS receiver demodulates the signal from each GPS satellite to obtain the orbit information of each GPS satellite, and based on the orbit and time information of each GPS satellite and the delay time of the received signal, the GPS receiver Is derived by simultaneous equations. In the GPS system, at least four GPS satellites for obtaining received signals are required because there is an error between the internal time due to the clock provided in the GPS receiver and the time due to the atomic clock provided in the GPS satellite. This is because the pseudo distances from at least four GPS satellites are necessary to calculate the four unknown parameters of the three-dimensional position and the accurate time from which the influence of the above is removed.
[0004]
In the GPS system, when a consumer GPS receiver is used, a spread spectrum signal radio wave called a C / A (Clear and Acquisition) code is received from the GPS satellite (Navstar) and positioning calculation is performed. Do.
[0005]
The transmission signal called the L1 band and C / A code has a transmission signal speed, that is, a chip rate of 1.023 MHz, and a pseudo-random noise (PN) having a code length of 1023 such as a so-called Gold code. ) Binary phase shift keying (hereinafter referred to as BPSK modulation method) with respect to a carrier having a frequency of 1575.42 MHz (hereinafter referred to as carrier) using a signal obtained by directly spreading 50 bps data with a sequence spreading code. ). In this case, since the code length is 1023, as shown in the first stage in FIG. 19, the C / A code has a spread code of 1023 chips as one period, that is, one period = 1 millisecond (msec). Will be repeated.
[0006]
The spreading code of this C / A code is different for each GPS satellite, but which GPS satellite uses which spreading code can be detected in advance by a GPS receiver. Further, the GPS receiver can grasp which GPS satellite can receive a signal at that point and at that point by a navigation message described later. Therefore, for example, in the case of three-dimensional positioning, a GPS receiver receives radio waves from at least four or more GPS satellites that can be acquired at that point and at that time, performs spectrum despreading, and performs positioning calculation Thus, the position of itself is calculated.
[0007]
One bit of the signal data from the GPS satellite is transmitted for 20 cycles of the spread code, that is, in units of 20 milliseconds, as shown in the second stage in the figure. That is, the data transmission rate is 50 bps as described above. Further, 1023 chips for one cycle of the spread code are inverted when the bit is “1” and when it is “0”.
[0008]
Further, the signal from the GPS satellite forms one word with 30 bits, that is, 600 milliseconds, as shown in the third row in FIG. Furthermore, the signal from the GPS satellite forms one subframe in 10 words, that is, 6 seconds, as shown in the fourth row in FIG. In the signal from the GPS satellite, as shown in the fifth row in the figure, a preamble that always has a prescribed bit pattern is added to the first word of one subframe even when data is updated. Inserted, and data is transmitted following this preamble.
[0009]
Furthermore, signals from GPS satellites form 5 subframes, ie, 1 frame in 30 seconds. And in the signal from a GPS satellite, the navigation message mentioned above is transmitted in the data unit of this 1 frame.
[0010]
The first three subframes of the data of one frame are information specific to GPS satellites called ephemeris information. The ephemeris information includes a parameter for obtaining the orbit of the GPS satellite and a transmission time of the signal from the GPS satellite.
[0011]
All GPS satellites use the common time information by providing an atomic clock, and the transmission time of the signal from the GPS satellite included in the ephemeris information is in units of one second of the atomic clock. Further, the spread codes of GPS satellites are generated in synchronization with the atomic clock.
[0012]
The trajectory information included in the ephemeris information is updated every few hours, but is the same information until the update is performed. Therefore, the GPS receiver can use the same orbit information accurately for several hours by holding the orbit information included in the ephemeris information in the memory. Note that the signal transmission time from the GPS satellite is updated every second.
[0013]
On the other hand, the navigation messages of the remaining two subframes in one frame of data are information transmitted in common from all GPS satellites called almanac information. This almanac information is required for 25 frames in order to acquire all information, and is composed of approximate position information of each GPS satellite, information indicating which GPS satellite can be used, and the like. This almanac information is updated every several months, but is the same information until the update is performed. Therefore, the GPS receiver can use the same information accurately for several months by holding the almanac information in the memory.
[0014]
In order to receive the signal from the GPS satellite and obtain the above-mentioned data, the GPS receiver first removes the carrier and then uses the same spreading code as the C / A code used by the GPS satellite to be received. Using the signal from the GPS satellite, the signal from the GPS satellite is captured by phase-synchronizing the C / A code and the spectrum is despread. When the GPS receiver performs spectrum despreading in phase synchronization with the C / A code, bits are detected, and a navigation message including time information and the like can be acquired based on a signal from a GPS satellite. Become.
[0015]
The GPS receiver captures a signal from a GPS satellite by a phase-locked search of a C / A code. As this phase-locked search, a correlation between a spread code generated by itself and a spread code of a received signal from a GPS satellite is performed. For example, when the correlation value of the correlation detection result is larger than a predetermined value, it is determined that the two are synchronized. If the GPS receiver determines that synchronization is not achieved, it uses some synchronization technique to control the phase of the spreading code generated by itself and synchronize it with the spreading code of the received signal. Yes.
[0016]
By the way, as described above, the signal from the GPS satellite is a signal obtained by modulating the carrier based on the BPSK modulation method with the signal obtained by spreading the data with the spreading code. Therefore, in order to receive a signal from a GPS satellite, the GPS receiver needs to synchronize not only the spreading code but also the carrier and data, but cannot synchronize the spreading code and the carrier independently.
[0017]
The GPS receiver usually converts the received signal into an IF signal by converting the carrier frequency of the received signal into an intermediate frequency (hereinafter referred to as IF) within several MHz, and the IF signal is used to convert the received signal into the IF signal. Perform the synchronization detection process. The carrier in the IF signal (hereinafter referred to as IF carrier) mainly includes a frequency error due to Doppler shift according to the moving speed of the GPS satellite, and an internal part of the GPS receiver when the received signal is converted into an IF signal. The frequency error of the local oscillator generated by
[0018]
Therefore, in the GPS receiver, since the IF carrier frequency is unknown due to these frequency error factors, it is necessary to search for the frequency. In addition, since the synchronization point (synchronization phase) within one cycle of the spread code is unknown due to dependence on the positional relationship between the GPS receiver and the GPS satellite, the GPS receiver described above Thus, some kind of synchronization method is required.
[0019]
A conventional GPS receiver uses a synchronization method that combines a frequency search for a carrier, synchronization acquisition by a sliding correlator, and synchronization maintenance by a DLL (Delay Locked Loop) and a Costas loop. Hereinafter, this synchronization method will be described.
[0020]
As a clock for driving a spread code generator of a GPS receiver, a clock obtained by dividing a reference frequency oscillator prepared in the GPS receiver is generally used. A high-precision crystal oscillator is used as the reference frequency oscillator, and the GPS receiver uses a local oscillation signal used to convert a received signal from a GPS satellite into an IF signal based on the output of the reference frequency oscillator. Generate.
[0021]
Here, FIG. 20 shows the processing contents for the frequency search. The GPS receiver performs a phase synchronization search for a spread code when the frequency of the clock signal that drives the spread code generator is a certain frequency f1. That is, the GPS receiver detects the correlation between the received signal from the GPS satellite and the spreading code at each chip phase by sequentially shifting the phase of the spreading code by one chip, and detects the correlation peak. Thus, a phase that can be synchronized is detected. In addition, when the frequency of the clock signal is f1, the GPS receiver changes the frequency division ratio with respect to the reference frequency oscillator, for example, if there is no phase that is synchronized in all the phase searches for 1023 chips. The frequency of the signal is changed to another frequency f2, and the phase search for 1023 chips is similarly performed. The GPS receiver implements a frequency search by repeating such an operation by changing the frequency of the clock signal stepwise.
[0022]
When the GPS receiver detects the frequency of the clock signal that can be synchronized by performing such a frequency search, the GPS receiver performs phase synchronization of the final spread code at the frequency of the clock signal. As a result, the GPS receiver can capture a signal from a GPS satellite even when there is a deviation in the oscillation frequency of the crystal oscillator.
[0023]
A Costas loop and DLL applied to a spread spectrum signal demodulator such as a GPS receiver are generally configured as shown in FIG. In this circuit, IF carrier synchronization is performed by the Costas loop 201, and spreading code synchronization is performed by the DLL 202.
[0024]
That is, in the Costas loop 201, a phase generated by a later-described spreading code generator (PN Generator; hereinafter referred to as PNG) 228 shown in the second stage in FIG. ) Is multiplied by the multiplier 203 and input. On the other hand, the IF signal is input to the DLL 202.
[0025]
In the Costas loop 201, the input signal is multiplied by a sine component (in-phase component) of a reproduction carrier generated by an NCO (Numeric Controlled Oscillator) 204 by a multiplier 205, while being generated by the NCO 204. The cosine component (orthogonal component) of the reproduced carrier is multiplied by the multiplier 206. In the Costas loop 201, a predetermined frequency band component of the in-phase component signal obtained by the multiplier 205 is passed by the LPF 207, and this signal is passed through the phase detector 210, the binarization circuit 211, and the square sum calculation circuit 212. To be supplied. On the other hand, in the Costas loop 201, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 206 is passed by the LPF 208, and this signal is supplied to the phase detector 210 and the square sum calculation circuit 212. . In the Costas loop 201, the phase information detected by the phase detector 210 based on the signals output from the LPFs 207 and 208 is supplied to the NCO 204 via the loop filter 209. In the Costas loop 201, the signals output from the LPFs 207 and 208 are supplied to the square sum calculation circuit 212, and the calculated square sum (I²+ Q²) Is output as a correlation value (P) for a spreading code whose phase is P. Further, in the Costas loop 201, the signal output from the LPF 207 is supplied to the binarization circuit 211, and information obtained by binarization is output as a navigation message.
[0026]
Thus, in the Costas loop 201, among the three phase spreading codes generated by the PNG 228, a spreading code having a phase P as the second stage in the figure is used. In the Costas loop 201, in order to detect the synchronization of the IF carrier, the sum of squares of the signals output from the LPFs 207 and 208 (I²+ Q²) Is determined as a correlation value (P).
[0027]
On the other hand, in the DLL 202, the multiplier 213 multiplies the input IF signal by the multiplier 213 with the spreading code of E (Early) shown in the first stage in FIG. At the same time, the multiplier 214 multiplies a spreading code of L (Late) shown in the third stage in FIG. In the DLL 202, the signal obtained by the multiplier 213 is multiplied by the sine component of the regenerated carrier generated by the NCO 204 in the Costas loop 201 by the multiplier 215, and the regenerated carrier generated by the NCO 204 is The cosine component is multiplied by the multiplier 216. In the DLL 202, a predetermined frequency band component of the in-phase component signal obtained by the multiplier 215 is passed by the LPF 217, and this signal is supplied to the square sum calculation circuit 219. On the other hand, in the DLL 202, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 216 is passed by the LPF 218, and this signal is supplied to the square sum calculation circuit 219. Further, in the DLL 202, the signal obtained by the multiplier 214 is multiplied by the sine component of the reproduction carrier generated by the NCO 204 in the Costas loop 201 by the multiplier 220, and the reproduction generated by the NCO 204 is also performed. A cosine component of the carrier is multiplied by a multiplier 221. In the DLL 202, a predetermined frequency band component of the in-phase component signal obtained by the multiplier 220 is passed by the LPF 222, and this signal is supplied to the square sum calculation circuit 224. On the other hand, in the DLL 202, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 221 is passed by the LPF 223, and this signal is supplied to the square sum calculation circuit 224.
[0028]
In the DLL 202, signals output from the square sum calculation circuits 219 and 224 are supplied to the phase detector 225, and the phase information detected by the phase detector 225 based on these signals passes through the loop filter 226. Then, based on the signal having a predetermined frequency generated by the NCO 227, the PNG 228 generates a spreading code of each phase E, P, L. Furthermore, in the DLL 202, the sum of squares (I²+ Q²) Is output as a correlation value (E) for a spreading code whose phase is E, while the square sum (I) calculated by the square sum calculation circuit 224 is output.²+ Q²) Is output as a correlation value (L) for a spreading code whose phase is L.
[0029]
As described above, in the DLL 202, among the three phase spreading codes generated by the PNG 228, two phase spreading codes having the phases E and L shown in the first and third stages in the figure are used. It is done. In the DLL 202, the square sum (I) of the signals output from the LPFs 217 and 218 in order to detect the synchronization of the spreading code.²+ Q²) As a correlation value (E) and the square sum (I) of the signals output from the LPFs 222 and 223, respectively.²+ Q²) As a correlation value (L). The correlation value (E) and the correlation value (L) change depending on the integration time of each LPF. However, in the DLL 202, the signal includes a point where the data is inverted. Output fluctuates to a minimum value of zero. Therefore, in the DLL 202, the sum of squares (I²+ Q²) As a correlation value, the integration time of the LPF is not stable until it is one cycle of the spreading code. Here, in the GPS receiver, since the cycle of the spreading code is 1 millisecond, the integration time of the LPF is 1 millisecond, which is about 1 kHz when converted in terms of bandwidth.
[0030]
However, such a conventional synchronization method is not suitable for high-speed synchronization in principle. In the GPS receiver, if it takes time to synchronize the spread code and the IF carrier, the reaction becomes slow and inconvenience occurs in use. Therefore, in an actual GPS receiver, in order to compensate for this disadvantage, the time until synchronization acquisition is shortened by parallel processing by increasing the number of channels.
[0031]
On the other hand, as a technique for performing high-speed acquisition of a spread spectrum signal instead of the above-described technique using sliding correlation, a matched filter is used. The matched filter can be digitally realized by a so-called transversal filter. In addition, as a matched filter, a spread code is obtained by a digital matched filter using a fast Fourier transform (hereinafter referred to as FFT) due to an improvement in hardware capability represented by a recent DSP (Digital Signal Processor). A technique for performing high-speed synchronization is realized. The latter is based on a correlation calculation speed-up method that has been known for a long time.
[0032]
By using these matched filters, the GPS receiver detects a correlation peak, for example, as shown in FIG. 23 for one period of the output waveform when there is a correlation. The position of this peak indicates the beginning of the spread code. By detecting this peak, the GPS receiver can acquire synchronization, that is, detect the phase of the spread code in the received signal. Further, the GPS receiver can detect the IF carrier frequency together with the phase of the spread code by using the above-described digital matched filter using FFT and performing an operation in the frequency domain of the FFT. Then, the GPS receiver converts the phase of the spread code into a pseudorange, and can calculate the position of the GPS receiver when at least four GPS satellites are detected. Based on this, the speed of the GPS receiver can be calculated.
[0033]
[Problems to be solved by the invention]
By the way, in the GPS receiver using the DLL and the Costas loop described above, it is expected that the reception area is expanded by increasing the sensitivity, and on the other hand, resistance to acceleration is also required.
[0034]
In this GPS receiver, in order to achieve high sensitivity, it is necessary to correlate with the spreading code in consideration of bit inversion of the navigation message in order to increase the time length of correlation detection. In a GPS receiver, it is necessary to reduce the signal bandwidth and improve the signal-to-noise ratio (S / N) as much as possible.
[0035]
On the other hand, in a GPS receiver, resistance to acceleration is resistance to a change in carrier frequency due to a change in Doppler frequency due to movement of the GPS receiver, and is to increase a response speed. Therefore, in a GPS receiver, improving the resistance to acceleration basically contradicts the narrowing of the band for high sensitivity.
[0036]
Therefore, in the DLL and the Costas loop, priority is given to either high sensitivity or resistance to acceleration according to the application, or a balance between the two is given, or dynamic control is performed according to the reception situation. It is preferable that it can respond according to the setting.
[0037]
These problems are not limited to GPS receivers, but are common to all mobile communications employing a spread spectrum and direct spread modulation scheme similar to GPS signals.
[0038]
The present invention has been made in view of such circumstances, and provides a spread spectrum signal demodulator capable of improving the reception sensitivity and improving the resistance to acceleration as compared to general DLL and Costas loop. The purpose is to do. Another object of the present invention is to provide a receiving apparatus that can easily perform synchronization acquisition and synchronization synchronization of spreading codes and carriers in signals from GPS satellites by applying this demodulating apparatus.
[0039]
[Means for Solving the Problems]
A demodulating device according to the present invention that achieves the above-described object is a demodulating device that demodulates a spread spectrum signal, and establishes synchronization between a reproduction carrier and a carrier included in an input spread spectrum signal. And a second loop circuit that establishes synchronization between the reproduction code and the spread code included in the input spread spectrum signal, and the first loop circuit and the second loop circuit are respectively a carrier and a spread code. Integrate the signal that has passed through the filter means with a filter unit that passes a predetermined frequency band component of the multiplication value of the input spectrum spread signal and the data 1 bit length or a predetermined length less than or equal to the data 1 bit length as a unit The first correlation value and the unit half length of the input spread spectrum signal out of the signal that has passed through the filter means are inverted. Correlation addition means for adding a second correlation value obtained by integrating the obtained signals, and performing correlation detection and phase control of the second loop circuit based on an output value from the correlation addition means. Yes.
[0040]
Such a demodulator according to the present invention inverts the first correlation value obtained by integrating the signal that has passed through the filter means and the half-length portion of the unit in the input spread spectrum signal among the signals that have passed through the filter means. The second correlation value obtained by integrating the obtained signals is added by the correlation adding means, and correlation detection and phase control of the second loop circuit are performed based on the obtained output value.
[0041]
In addition, a receiving apparatus according to the present invention that achieves the above-described object is a receiving apparatus that receives a signal from a satellite and calculates its position and velocity, and a receiving unit that receives the signal from the satellite; Frequency conversion means for converting the frequency of the received signal received by the reception means to a predetermined intermediate frequency, and synchronization acquisition for detecting the phase of the spread code in the intermediate frequency signal obtained by the frequency conversion means, and carrier frequency in the intermediate frequency signal Synchronization acquisition means for detecting the signal, and the phase of the spread code detected by the synchronization acquisition means and the carrier frequency detected by the synchronization acquisition means for a plurality of channels provided independently for a plurality of satellites. Assigned to each satellite and set for each, spreading code with phase and carrier frequency of the set spreading code as initial values A plurality of channels in the synchronization holding means for demodulating the spread spectrum signal, each of which has been input as a reproduction carrier, and a synchronization holding means for demodulating a message included in the intermediate frequency signal. A first loop circuit that establishes synchronization with the carrier included in the spread spectrum signal, and a second loop circuit that establishes synchronization between the reproduction code and the spread code included in the input spread spectrum signal, Each of the first loop circuit and the second loop circuit includes a filter unit that passes a predetermined frequency band component of a multiplication value of a carrier, a spread code, and an input spread spectrum signal, and a data bit length or data A first correlation value obtained by integrating the signal that has passed through the filter means with a predetermined length of 1 bit or less as a unit, Correlation addition means for adding a second correlation value obtained by integrating a signal obtained by inverting a half length unit of a unit in the input spread spectrum signal among the signals that have passed through the data means, and the plurality of channels are: Each is characterized by performing correlation detection and phase control of the second loop circuit based on the output value from the correlation adding means.
[0042]
Such a receiving apparatus according to the present invention inverts the first correlation value obtained by integrating the signal that has passed through the filter means and the half-length portion of the unit in the input spread spectrum signal among the signals that have passed through the filter means. The second correlation value obtained by integrating the obtained signals is added by the correlation adding means, and the correlation detection and the phase control of the second loop circuit are performed based on the obtained output value, and the synchronization between the spread code and the carrier is maintained. I do.
[0043]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.
[0044]
In this embodiment, a global positioning system (hereinafter referred to as GPS), which is a kind of GNSS (Global Navigation Satellites System) system that measures the position of a moving body on the ground using an artificial satellite. This is a GPS receiver that receives signals from at least four GPS satellites and calculates its position based on the received signals. This GPS receiver receives a spread spectrum signal radio wave called a C1 / A (Clear and Acquisition) code as a reception signal, and is a general demodulator that demodulates a spread spectrum signal. It is possible to improve the reception sensitivity and improve the resistance to acceleration as compared with the DLL (Delay Locked Loop) and the Costas loop.
[0045]
As shown in FIG. 1, the GPS receiver, when demodulating the received signal, spreads a pseudo-random noise (PN) sequence generated by itself and a spreading code in the received signal. By separating the function for capturing synchronization with the function for maintaining the synchronization between the spread code and the carrier wave (hereinafter referred to as carrier), the synchronization acquisition speed can be increased with a small circuit scale. It can be done. In the GPS receiver 10, the DLL and the Costas loop do not need to operate as those that perform synchronization acquisition, as will be described later, and only need to operate as the synchronization holding unit 25 that holds the synchronization between the spread code and the carrier. Instead, the DLL and the Costas loop are expected to expand the reception area due to higher sensitivity and, on the other hand, are also required to withstand acceleration. Therefore, in the GPS receiver 10, an improvement in the reception sensitivity of the DLL and the Costas loop and an improvement in resistance to acceleration are realized.
[0046]
In the following, first, the overall configuration of the GPS receiver 10 in which the synchronization acquisition function and the synchronization holding function are separated will be described, and then the synchronization acquisition unit 24 and the synchronization holding unit 25 will be described in detail. A specific configuration of the holding unit 25 will be described in detail.
[0047]
First, the overall configuration of the GPS receiver will be described.
[0048]
As shown in the figure, the GPS receiver 10 includes a crystal oscillator (X'tal Oscillator; hereinafter referred to as XO) 11 that generates an oscillation signal D1 having a predetermined oscillation frequency, and a predetermined oscillation different from the XO11. Frequency F_OSCA temperature-compensated crystal oscillator (Temperature Compensated X'tal Oscillator; hereinafter referred to as TCXO) 12 that generates an oscillation signal D2 having the following characteristics, and the oscillation signal D2 supplied from the TCXO 12 is multiplied and / or divided ( and a multiplier / divider 13 for dividing.
[0049]
The XO 11 generates an oscillation signal D1 having a predetermined oscillation frequency of about 32.768 kHz, for example. The XO 11 supplies the generated oscillation signal D1 to an RTC (Real Time Clock) 27 described later.
[0050]
The TCXO 12 is different from the XO 11, for example, a predetermined oscillation frequency F of about 18.414 MHz._OSCAn oscillation signal D2 having the following is generated. The TCXO 12 supplies the generated oscillation signal D2 to the multiplier / divider 13 and a frequency synthesizer 18 described later.
[0051]
The multiplier / divider 13 multiplies the oscillation signal D2 supplied from the TCXO 12 at a predetermined multiplication rate and / or a predetermined frequency based on a control signal D3 supplied from a CPU (Central Processing Unit) 26 described later. Divide by the division ratio. The frequency multiplier / frequency divider 13 supplies the multiplied and / or frequency-divided oscillation signal D4 to a synchronization acquisition unit 24 described later, a synchronization holding unit 25 described later, a CPU 26, a timer 28 described later, and a memory 29 described later.
[0052]
The GPS receiver 10 also includes an antenna 14 that receives an RF (Radio Frequency) signal transmitted from a GPS satellite, and a low noise amplifier (Low Noise Amplifier) that amplifies the received RF signal D5 received by the antenna 14. (Hereinafter referred to as “LNA”) 15, a band pass filter (hereinafter referred to as “BPF”) 16 that passes a predetermined frequency band component of the amplified RF signal D 6 amplified by this LNA 15, and a signal that passes through this BPF 16. An amplifier 17 for further amplifying the amplified RF signal D7 and a predetermined frequency F based on the oscillation signal D2 supplied from the TCXO 12_LOA frequency synthesizer 18 that generates a local oscillation signal D10 having a predetermined frequency F amplified by an amplifier 17_RFA mixer 19 that multiplies the amplified RF signal D8 having a local oscillation signal D10 supplied from the frequency synthesizer 18 by the amplified RF signal D8, and a predetermined frequency F that is downconverted by being multiplied by the mixer 19._IFAn amplifier 20 that amplifies an intermediate frequency (hereinafter referred to as IF) signal D11, and a low-pass filter (Low) that passes a predetermined frequency band component of the amplified IF signal D12 amplified by the amplifier 20. Pass Filter (hereinafter referred to as LPF) 21 and an analog / digital converter (Analog / Digital Converter; hereinafter referred to as A) for converting the analog amplified IF signal D13 passed by the LPF 21 into a digital amplified IF signal D14. / D.) 22.
[0053]
The antenna 14 receives an RF signal in which a carrier having a frequency of 1575.42 MHz transmitted from a GPS satellite is spread. The reception RF signal D5 received by the antenna 14 is supplied to the LNA 15.
[0054]
The LNA 15 amplifies the reception RF signal D5 received by the antenna 14. The LNA 15 supplies the amplified RF signal D6 that has been amplified to the BPF 16.
[0055]
The BPF 16 is a so-called SAW (Surface Acoustic Wave) filter, and passes a predetermined frequency band component of the amplified RF signal D6 amplified by the LNA 15. The amplified RF signal D7 passed by the BPF 16 is supplied to the amplifier 17.
[0056]
The amplifier 17 further amplifies the amplified RF signal D7 passed by the BPF 16. The amplifier 17 has an amplified predetermined frequency F_RFThat is, the amplified RF signal D8 of 1575.42 MHz is supplied to the mixer 19.
[0057]
The frequency synthesizer 18 has a predetermined frequency F based on the oscillation signal D2 supplied from the TCXO 12 under the control of the control signal D9 supplied from the CPU 26._LOA local oscillation signal D10 having the following is generated. The frequency synthesizer 18 supplies the generated local oscillation signal D10 to the mixer 19.
[0058]
The mixer 19 has a predetermined frequency F amplified by the amplifier 17._RFIs multiplied by the local oscillation signal D10 supplied from the frequency synthesizer 18 to downconvert the amplified RF signal D8, for example, a predetermined frequency F of about 1.023 MHz._IFIF signal D11 is generated. The IF signal D11 generated by the mixer 19 is supplied to the amplifier 20.
[0059]
The amplifier 20 amplifies the IF signal D11 down-converted by the mixer 19. The amplifier 20 supplies the amplified amplified IF signal D12 to the LPF 21.
[0060]
The LPF 21 passes a band component lower than a predetermined frequency in the amplified IF signal D12 amplified by the amplifier 20. The amplified IF signal D13 passed by the LPF 21 is supplied to the A / D 22.
[0061]
The A / D 22 converts the analog amplified IF signal D13 passed by the LPF 21 into a digital amplified IF signal D14. The amplified IF signal D14 converted by the A / D 22 is supplied to the synchronization acquisition unit 24 and the synchronization holding unit 25.
[0062]
In the GPS receiver 10, among these units, the LNA 15, BPF 16, amplifiers 17 and 20, frequency synthesizer 18, mixer 19, LPF 21, and A / D 22 are as high as 1575.42 MHz received by the antenna 14. The received RF signal D5 having a frequency is set to a low frequency F of, for example, about 1.023 MHz so that digital signal processing can be easily performed._IFIs configured as a frequency conversion unit 23 that down-converts the amplified IF signal D14.
[0063]
Further, the GPS receiver 10 includes a synchronization acquisition unit 24 that performs synchronization acquisition of the spreading code generated by itself and the spreading code in the amplified IF signal D14 supplied from the A / D 22 and detection of the carrier frequency in the amplified IF signal D14; , A synchronization holding unit 25 for holding the synchronization between the spread code and the carrier in the amplified IF signal D14 supplied from the A / D 22 and demodulating the message, a CPU 26 for performing various arithmetic processes by comprehensively controlling each unit, and the XO 11 RTC 27 for measuring time based on the oscillation signal D1 supplied from, a timer 28 as an internal clock of the CPU 26, and a memory 29 such as a RAM (Random Access Memory) and a ROM (Read Only Memory).
[0064]
Although the details will be described later, the synchronization acquisition unit 24 is supplied from the A / D 22 based on the multiplied and / or divided oscillation signal D4 supplied from the multiplier / divider 13 under the control of the CPU 26. The synchronous acquisition of the spread code in the amplified IF signal D14 is performed, and the carrier frequency in the amplified IF signal D14 is detected. At this time, the synchronization acquisition unit 24 performs synchronization acquisition with coarse accuracy, as will be described later. The synchronization acquisition unit 24 supplies the satellite number for identifying the detected GPS satellite, the phase of the spreading code, and the carrier frequency to the synchronization holding unit 25 and the CPU 26.
[0065]
Although the details will be described later, the synchronization holding unit 25 is supplied from the A / D 22 based on the multiplied and / or divided oscillation signal D4 supplied from the multiplier / divider 13 under the control of the CPU 26. In addition to maintaining synchronization between the spread code and the carrier in the amplified IF signal D14, the navigation message included in the amplified IF signal D14 is demodulated. At this time, as will be described later, the synchronization holding unit 25 starts the operation using the satellite number, the phase of the spread code, and the carrier frequency supplied from the synchronization acquisition unit 24 as initial values. The synchronization holding unit 25 performs synchronization holding on the amplified IF signals D14 from a plurality of GPS satellites in parallel, and supplies the detected spreading code phase, carrier frequency, and navigation message to the CPU 26.
[0066]
The CPU 26 acquires the phase of the spread code, the carrier frequency, and the navigation message supplied from the synchronization holding unit 25, calculates the position and speed of the GPS receiver 10 based on these various information, and also uses the navigation message. Based on the accurate time information of the GPS satellites obtained from the above, various GPS-related arithmetic processes such as correcting the time information of the GPS receiver 10 are performed. In addition, the CPU 26 performs overall control related to each part and various peripherals of the GPS receiver 10 and input / output with the outside.
[0067]
The RTC 27 measures time based on the oscillation signal D1 supplied from the XO 11. The time information measured by the RTC 27 is substituted until the accurate time information of the GPS satellite is obtained, and the CPU 26 that has obtained the accurate time information of the GPS satellite controls the XO 11. Corrected as appropriate.
[0068]
The timer 28 functions as an internal clock of the CPU 26, and is used for generation of various timing signals necessary for the operation of each unit and time reference. For example, in the GPS receiver 10, the timer 28 refers to the timing at which the synchronization holding unit 25 starts the operation of a spread code generator, which will be described later, in accordance with the phase of the spread code that is synchronously acquired by the synchronization acquisition unit 24.
[0069]
The memory 29 includes a RAM, a ROM, and the like. In the memory 29, a RAM is used as a work area when performing various processes by the CPU 26 and the like, and when buffering various input data and holding intermediate data and calculation result data generated in the calculation process. Also, a RAM is used. In the memory 29, a ROM is used as means for storing various programs, fixed data, and the like.
[0070]
In the GPS receiver 10, the synchronization acquisition unit 24, the synchronization holding unit 25, the CPU 26, the RTC 27, the timer 28, and the memory 29 are configured as a baseband processing unit.
[0071]
In the GPS receiver 10 including such units, at least each unit excluding the XO 11, the TCXO 12, the antenna 14, the LNA 15, and the BPF 16 can be configured as a demodulating circuit 30 that is an integrated circuit.
[0072]
The GPS receiver 10 receives RF signals from at least four or more GPS satellites, converts the RF signals into IF signals by the frequency converter 23, and then performs synchronization acquisition and carrier of spreading codes by the synchronization acquisition unit 24. The frequency is detected, and the synchronization holding unit 25 holds the synchronization between the spread code and the carrier and demodulates the navigation message. Then, the GPS receiver 10 calculates the position and velocity of the GPS receiver 10 by the CPU 26 based on the phase of the spread code, the carrier frequency, and the navigation message.
[0073]
Now, the synchronization acquisition unit 24 and the synchronization holding unit 25 in the GPS receiver 10 will be described in detail below. As described above, the GPS receiver 10 is obtained by separating the synchronization acquisition function and the synchronization holding function into the synchronization acquisition unit 24 and the synchronization holding unit 25. Here, the reason why the functions are separated in this way will also be described.
[0074]
As described above, the synchronization acquisition unit 24 performs the acquisition of the synchronization of the spread code in the IF signal and the detection of the carrier frequency at high speed. The synchronization acquisition unit 24 uses a matched filter to perform the synchronization acquisition of the spreading code at high speed. Specifically, the synchronization acquisition unit 24 can use a so-called transversal filter 50 as a matched filter, for example, as shown in FIG.
[0075]
Further, the synchronization acquisition unit 24 can also use a digital matched filter 60 using a fast Fourier transform (hereinafter referred to as FFT) as a matched filter, for example, as shown in FIG.
[0076]
Specifically, as shown in the figure, the digital matched filter 60 generates an IF signal corresponding to the amplified IF signal D14 obtained by the antenna 14 and the frequency converter 23 described above, and an oscillation signal generated by the TCXO 12 described above. The input signal is sampled and input by a sampler 61 that samples the input signal at a predetermined sampling frequency based on D2. The digital matched filter 60 includes a memory 62 for buffering the IF signal sampled by the sampler 61, an FFT processing unit 63 for reading the IF signal buffered by the memory 62 and performing FFT, and the FFT processing unit 63. A memory 64 for buffering a frequency domain signal obtained by performing FFT processing, a spreading code generator 65 for generating the same spreading code as the spreading code in the RF signal from the GPS satellite, and the spreading code generator 65 An FFT processing unit 66 that performs FFT processing on the generated spread code, a memory 67 that buffers a frequency domain signal obtained by performing FFT processing by the FFT processing unit 66, and buffered in the memory 64 Frequency domain signal and buffer in memory 67 A multiplier 68 that multiplies the frequency domain signal being multiplied, and an IFFT processing unit that performs an inverse FFT (Inverted Fast Fourier Transform; hereinafter referred to as IFFT) process on the frequency domain signal multiplied by the multiplier 68 69 and the peak of the correlation between the spread code in the RF signal from the GPS satellite and the spread code generated in the spread code generator 65 based on the autocorrelation function obtained by the IFFT processing by the IFFT processing unit 69. And a peak detector 70 for detection.
[0077]
In this digital matched filter 60, each part of the FFT processing units 63 and 66, the spread code generator 65, the multiplier 68, the IFFT processing unit 69, and the peak detector 70 is actually implemented by a DSP (Digital Signal Processor). Implemented as software to be executed. That is, the synchronization acquisition unit 24 to which the digital matched filter 60 is applied includes, for example, as shown in FIG. 4, a sampler 81 corresponding to the sampler 61 described above, a RAM 82 corresponding to the memory 62 described above, and memories 64 and 67 described above. And a RAM / ROM 83 including a DSP program and a work area, and a DSP 84 that executes the processing of the FFT processing units 63 and 66, the spread code generator 65, the multiplier 68, the IFFT processing unit 69, and the peak detector 70 described above. It consists of.
[0078]
In the example shown in the figure, the synchronization acquisition unit 24 samples a 1.023 MHz IF signal by the sampler 81 at 4.096 MHz, and performs an operation equivalent to that of the digital matched filter 60 by the DSP 84, thereby acquiring the synchronization of the spread code. That is, the phase detection of the spread code in the IF signal can be performed with an accuracy of ¼ chip. Further, if the capacity of the RAM 82 is 16 milliseconds, the synchronization capturing unit 24 performs an operation in the FFT frequency domain by the DSP 84, thereby achieving an accuracy of 1/16 kHz (± 1/32 kHz). A carrier frequency (hereinafter referred to as IF carrier) frequency in the IF signal can be detected. Since the IF signal stored in the RAM 82 includes signals from a plurality of GPS satellites, the synchronization acquisition unit 24 detects a plurality of GPS satellites by calculating the correlation with the spreading code of each GPS satellite. can do.
[0079]
The GPS receiver 10 can calculate the position and velocity of the GPS receiver 10 based on the phase of the spreading code and the carrier frequency for at least four or more GPS satellites detected by the synchronization acquisition unit 24. .
[0080]
However, in the GPS receiver 10, the position and speed of the GPS receiver 10 obtained based on the above-described 1/4 chip as the phase detection accuracy of the spread code and 1/16 kHz as the detection accuracy of the carrier frequency. The calculation result of is difficult to say with sufficient accuracy. In the GPS receiver 10, in order to improve accuracy, processing such as increasing the sampling frequency by the sampler 81 and increasing the time length for storing the IF signal is required. It is assumed that the memory capacity increases and the processing time until the phase of the spread code and the carrier frequency are detected becomes long. Further, in the GPS receiver 10, if the synchronization acquisition unit 24 does not receive a navigation message from the outside, it is necessary to demodulate a navigation message from at least four GPS satellites every 20 milliseconds. The DSP 84 must always perform synchronization detection and navigation message demodulation at extremely high speed. These problems cause an increase in cost and an increase in power consumption due to an increase in the size of hardware.
[0081]
Therefore, in the GPS receiver 10, the synchronization acquisition unit 24 performs synchronization acquisition with coarse accuracy, and the synchronization holding unit 25 performs synchronization holding of a plurality of GPS satellites and demodulation of navigation messages.
[0082]
The synchronization acquisition unit 24 supplies the detected satellite number, the phase of the spread code, and the carrier frequency to the synchronization holding unit 25. On the other hand, the synchronization holding unit 25 starts the operation using the various information supplied from the synchronization capturing unit 24 as initial values. Based on the phase of the spreading code, the synchronization holding unit 25 matches the start timing of the spreading code generated by the DLL circuit described later. In addition, the GPS receiver 10 sets what corresponds to the satellite number of the detected GPS satellite as a spreading code to generate. At this time, the GPS receiver 10 is affected by an error in the oscillation frequency of an oscillation signal generated by an oscillator such as a Doppler shift or TCXO 12, but basically the spreading code is repeated at a cycle of 1 millisecond. For this reason, the start timing of the spread code generated by the DLL circuit may be shifted by an integral multiple of 1 millisecond.
[0083]
The IF carrier frequency includes an error of the TCXO 12 that generates the sampling clock for taking the IF signal into the memory such as the above-described RAM 82. Therefore, even if the resolution problem is removed, That is, it is not the sum of the carrier frequency and the Doppler shift amount. However, in the GPS receiver 10, when the synchronization acquisition unit 24 and the synchronization holding unit 25 operate with the same oscillator, that is, with a clock having the TCXO 12 as an oscillation source, both have the same frequency error. Therefore, there is no problem for the synchronization holding unit 25 to start the operation using the IF carrier frequency detected by the synchronization acquisition unit 24 as an initial value.
[0084]
Since the synchronization holding unit 25 performs synchronization holding of a plurality of GPS satellites in parallel, for example, as shown in FIG.₁, 91₂, ..., 91_NHave Channel circuit 91₁, 91₂, ..., 91_NAre respectively assigned to the individual detection results by the synchronization acquisition unit 24 according to the setting of the control register 92.
[0085]
Channel circuit 91₁, 91₂, ..., 91_NAs will be described in detail later, each of these is constituted by a circuit combining a Costas loop for IF carrier synchronization and a DLL for spreading code synchronization.
[0086]
A channel circuit 91 constituted by a circuit combining a Costas loop for IF carrier synchronization and a DLL for spreading code synchronization.₁, 91₂, ..., 91_NIn the synchronization holding unit 25 having the above, the satellite number of the GPS satellite, the phase of the spread code, and the carrier frequency are set as initial values before the operation starts. The initial value is set by communicating directly with the synchronization acquisition unit 24 or via the CPU 26 that controls the synchronization acquisition unit 24 and the synchronization holding unit 25.
[0087]
Such a synchronization holding unit 25 synchronizes with the spread code as follows. That is, as shown in FIG. 6, the synchronization acquisition unit 24 starts a timer at the timing when the IF signal is taken into a memory such as the RAM 82, and the phase of the spread code with respect to the IF signal stored in the memory by the synchronization acquisition unit 24 When h is detected, the synchronization holding unit 25 receives the value of the phase h, and then starts reception of the spreading code generated by the DLL at the time when the same timer is shifted from the integral multiple of 1 millisecond by h. Match the phase to the spreading code of the signal. Note that “PN” in the figure indicates a PN sequence code, that is, a spreading code.
[0088]
Here, in the circuit combining the conventional Costas loop and the DLL, since the phase of the spreading code in the received signal is unknown, the IF carrier frequency generated by the DLL and the period of the spreading code are slightly shifted, and the IF signal In the process of sliding the phase with respect to the spread code, a phase having a significant intensity correlation was detected. Therefore, in the conventional circuit, in the worst case, the detection is performed for the carrier frequency in the range of several kHz and all the phases in the spreading code having a code length of 1023. It took quite a while to establish.
[0089]
On the other hand, in the GPS receiver 10, since the initial value of the phase of the spreading code received by the synchronization holding unit 25 and the IF carrier frequency is slightly deviated from the true value, there is a significant intensity correlation. A certain phase always exists in the vicinity of the initial value even if an error is included. Accordingly, as in the conventional circuit, the synchronization holding unit 25 first stops the control of the loop filter in the Costas loop and the DLL, and changes the signal generated by the NCO (Numeric Controlled Oscillator) around the initial value. However, after searching for a significant intensity correlation, and detecting the correlation, the control is switched to the loop filter. Thereby, the synchronization holding unit 25 can establish the synchronization of the phase of the spread code by the DLL and the synchronization of the phase of the carrier by the Costas loop in a very short time, and can continue to maintain the synchronization thereafter. In the synchronization holding unit 25, since the initial value can be set with an accuracy of IF carrier frequency of several tens of Hz, the bandwidth of each LPF and each loop filter can be narrowed from the beginning, and the S / N (Signal to Noise ratio) ) Can be established in a high state.
[0090]
In the GPS receiver 10, if the synchronization holding unit 25 is operated with a clock of, for example, 1.023 MHz × 16 = 16.668 MHz and the phase of the spread code is detected with a time resolution of 1 / 1.368 MHz in the DLL, 1 / The pseudo-range from the phase of the spread code to the GPS satellite can be calculated with an accuracy of 16 chips, and if the NCO in the Costas loop can be controlled in units of 1 Hz, the resolution of the IF carrier frequency is 1 Hz, and the DLL And the Costas loop can maintain synchronization with these accuracies.
[0091]
As described above, in the GPS receiver 10, when synchronization is held by the synchronization holding unit 25, the position of the GPS receiver 10 is continuously calculated based on the phase of the spreading code generated by the DLL. In addition to being able to output, the speed of the GPS receiver 10 can be continuously calculated and output based on the IF carrier frequency obtained by the Costas loop.
[0092]
As described above, the synchronization holding unit 25 uses the phase of the spread code and the IF carrier frequency passed from the synchronization acquisition unit 24 as initial values, thereby obtaining a significant intensity correlation in the vicinity of these initial values. Search for the phase to be generated. This is one reason that the clock source oscillator mounted on the GPS receiver 10, ie, the TCXO 12, has an error with respect to the nominal frequency. In the GPS receiver 10, when the synchronization acquisition unit 24 is configured using the digital matched filter 60 using the FFT shown in FIG. 3, the IF signal is stored in the memory, and then the processing time of the DSP Since the detection result is supplied to the synchronization holding unit 25 later, the nominal frequency F of the oscillator_OSCThe error with ΔF_OSCAssuming that the processing time of the DSP is T seconds, when the detection result is supplied to the synchronization holding unit 25, T × ΔF_OSC/ F_OSCError occurs. For example, in the GPS receiver 10, T = 3 seconds and ΔF_OSC/ F_OSCIs within the range of ± 3 ppm, an error within ± 9 microseconds = about ± 9 chips occurs. As described above, in the GPS receiver 10, when the DSP processing time is increased, the error increases accordingly.
[0093]
In the GPS receiver 10, the carrier frequency Doppler shift caused by the movement of the GPS satellite and the GPS receiver 10 also causes an error. In the GPS receiver 10, the carrier frequency, that is, 1575.42 MHz is set to F._RFAnd the Doppler shift of the received signal is ΔF_DThen, the period of the spread code, that is, 1 millisecond is approximately (1-ΔF) by Doppler shift._D/ F_RFFor example, when a Doppler shift in the range of +5 to -5 kHz occurs, an error of about -9.5 to 9.5 microseconds = about -9.5 to 9.5 chips in 3 seconds. Occurs.
[0094]
These two examples are values that are relatively close to reality. In the GPS receiver 10, when both the error of the oscillator and the Doppler shift are combined, an error occurs within a range of about ± 20 chips. From this, only this range is searched to detect the correlation. For example, the synchronization holding unit 25 starts the spreading code generated by the DLL by 20 chips earlier than the phase of the spreading code supplied from the synchronization capturing unit 24, and sets the frequency of the NCO as the cycle of the spreading code at that time. Is set to be longer than (1 + 5 / 1575.420) milliseconds, it starts when the slide with respect to the spread code of the signal from the GPS satellite included in the IF signal is shifted by +20 chips, In the meantime, it is possible to search for the presence or absence of correlation while the phases of the spreading codes are sliding.
[0095]
Thus, in the past, correlation detection was performed using a DLL and a Costas loop while changing the IF carrier frequency in the range of the error of the oscillator and the amount of Doppler shift. In contrast, in the GPS receiver 10, the initial carrier frequency has only a slight error, and the correlation detection range is only a few tenths. The time required for establishment can be made extremely short.
[0096]
As described above, the GPS receiver 10 is configured by separating the synchronization acquisition function and the synchronization holding function, so that the phase of the spread code of the signal from the GPS satellite included in the IF signal by the synchronization acquisition unit 24. In addition, the IF carrier frequency can be detected at high speed, and the synchronization holding unit 25 can quickly shift to the synchronization holding operation based on the detection result. However, in the GPS receiver 10, when the processing sequence increases in order to detect a weak GPS satellite signal included in the IF signal, and the synchronization acquisition unit 24 is operated with a low-speed clock to reduce power consumption. In such a case, the processing time in the synchronization acquisition unit 24 becomes long, and accordingly, the search range until the synchronization establishment by the synchronization holding unit 25 is widened, which is not preferable.
[0097]
In general, in a GPS receiver, a common crystal oscillator is used as a source oscillator that generates a clock for signal processing in a local oscillator and a baseband processing unit in a frequency conversion unit. As previously shown in FIG. 1, the source oscillator of the local oscillator in the frequency conversion unit 23 and the source oscillator of the operation clock of the synchronization acquisition unit 24 and the synchronization holding unit 25 are shared by the TCXO 12. Then, the synchronization holding unit 25 is, for example, an intermediate frequency F of 1.023 MHz based on the IF carrier frequency detected by the synchronization acquisition unit 24 and the nominal value of the TCXO 12._IFΔF_IFAnd the carrier frequency of a signal from a GPS satellite of 1575.42 MHz is F_RFIf the time required for the synchronization acquisition process after the synchronization acquisition unit 24 captures the IF signal in the memory is T seconds and the phase of the spread code is h, the phase h of the spread code is h + Δh as shown in FIG. (Δh = −T × ΔF_IF/ Δ_RFCorrect as follows. For example, ΔF_IFWhen +3 kHz and T = 10 seconds, Δh = −19 microseconds = about −19 chips. The synchronization holding unit 25 can correct the spread code phase shift caused by the oscillation frequency error and the Doppler shift caused by the TCXO 12 by performing such correction. Even when the processing takes several tens of seconds, synchronization can be established by searching in a range of about one chip.
[0098]
The reason why such correction is possible is as follows.
[0099]
In the GPS receiver 10, a carrier frequency F that is a known signal from a GPS satellite by the frequency converter 23._RFIs known intermediate frequency F_IFTo convert to a nominal oscillation frequency F_OSCOscillating frequency F by frequency synthesizer 18 based on TCXO12_LO= NxF_OSC(N is a constant number, N >> 1) and F_IF= F_RF-F_LOTo be. Here, the signal from the GPS satellite that is actually received has an intermediate frequency F_IFOn the other hand, the error ΔF caused by the error of the oscillation frequency by the TCXO 12 and the Doppler shift_IFIs added. That is, in the GPS receiver 10, the Doppler shift amount is set to ΔF._DAnd the error from the nominal oscillation frequency by TCXO12 is ΔF_OSCThen,
F_IF+ ΔF_IF= F_RF+ ΔF_D-F_LO= F_RF+ ΔF_D-N × (F_OSC+ ΔF_OSC)
It becomes. Therefore, in the GPS receiver 10, the IF carrier frequency detected by the synchronization capturing unit 24 is
F_IF+ ΔF_IF, ΔF_IF= ΔF_D-N × ΔF_OSC
It becomes. What is important here is that what the synchronization capturing unit 24 can detect is ΔF._IFΔF_D, ΔF_OSCIs unknown at the initial acquisition stage.
[0100]
Here, if the timer counts 1 millisecond, which is one cycle length of the spread code, at the nominal oscillation frequency by the TCXO 12, the error ΔF_OSCIn fact, 1 millisecond x F_OSC/ (F_OSC+ ΔF_OSC) ≒ (1-ΔF_OSC/ F_OSC) Milliseconds. On the other hand, the one-cycle length of the spread code in the received signal is the Doppler shift amount ΔF._D1 ms x F_RF/ (F_RF+ ΔF_D) ≒ (1-ΔF_D/ F_RF) Milliseconds. Therefore, the ratio between the 1-cycle length of the spread code in the received signal and 1 millisecond counted at the nominal oscillation frequency by the TCXO 12 is:
(1-ΔF_D/ F_RF) / (1-ΔF_OSC/ F_OSC) ≒ 1-ΔF_D/ F_RF+ ΔF_OSC/ F_OSC
It becomes. Furthermore, if the right side of this equation is transformed,
1-ΔF_IF/ F_RF+ (ΔF_OSC/ F_OSC) X (F_IF/ (N × F_OSC)) ≒ 1-ΔF_IF/ F_RF
It becomes. As described above, in the GPS receiver 10, ΔF that is an unknown parameter for the synchronization acquisition unit 24._D, ΔF_OSCA fairly good approximation can be made without including.
[0101]
As a result, in the GPS receiver 10, the time from when the synchronization capturing unit 24 captures the IF signal to the memory performs the synchronization capturing process and the phase h of the detected spread code is supplied to the synchronization holding unit 25. When T seconds are required, the phase of the spread code detected by the synchronization acquisition unit 24 during this T seconds is −T × ΔF_IF/ F_RFWill be shifted. Therefore, as shown in FIG. 7, the synchronization holding unit 25 adds the correction value Δh = −T × ΔF to the phase h of the spreading code supplied from the synchronization acquisition unit 24._IF/ F_RFBy adjusting the start timing of the spreading code generated by the DLL by adding h + Δh, the phase shift of the spreading code generated during the synchronization acquisition processing time can be corrected. Can be detected, and synchronization can be established in a very short time. In the GPS receiver 10, for example, the CPU 26 calculates the correction value, supplies the calculation result to the synchronization holding unit 25, corrects the phase by the synchronization holding unit 25, and then starts the synchronization acquisition processing by the synchronization acquisition unit 24. That's fine.
[0102]
Information necessary for such a method of correcting the phase of the spread code is only the IF carrier frequency detected by the synchronization acquisition unit 24. In the GPS receiver 10, both the oscillation frequency error caused by the TCXO 12 and the Doppler shift amount are included. It is unnecessary as information. Further, in the GPS receiver 10, F is not dependent on the IF carrier frequency._IF= F_RO-F_LOSo that the local oscillation frequency F_LOEven when setting_IFIt is only necessary to change the sign of.
[0103]
Now, a specific configuration of the synchronization holding unit 25 as described above will be described.
[0104]
Channel circuit 91 in the synchronization holding unit 25₁, 91₂, ..., 91_NAs described above, can be configured by a circuit that combines a Costas loop for IF carrier synchronization applied as a demodulator for demodulating a spread spectrum signal and a DLL for spreading code synchronization.
[0105]
Here, in the conventional Costas loop and DLL, the synchronization determination is performed using the square sum of the output from the LPF on the in-phase component (I) side and the output from the LPF on the quadrature component (Q) side as a correlation value. .
[0106]
On the other hand, in the GPS receiver 10, in order to improve the reception sensitivity and to improve the resistance against acceleration, as shown in FIG. In addition, the DLL 102 is newly provided with correlation adders 121, 122, 128, and 129, and the synchronization determination is performed using the sum of squares of the outputs of these correlation adders as a correlation value.
[0107]
That is, the channel circuit 91₁, 91₂, ..., 91_NAs shown in the figure, the Costas loop 101 has a spreading code generator (described later) for the IF signal corresponding to the amplified IF signal D14 obtained by the antenna 14 and the frequency converter 23 described above. (PN Generator; hereinafter referred to as PNG)) A signal obtained by multiplying the multiplier 103 by a spreading code whose phase generated by P is P (Prompt) is input. On the other hand, the channel circuit 91₁, 91₂, ..., 91_N, The DLL 102 receives an IF signal corresponding to the amplified IF signal D14 obtained by the antenna 14 and the frequency converter 23 described above.
[0108]
In the Costas loop 101, the input signal is multiplied by a sine component (in-phase component) of the regenerated carrier generated by the NCO 104 by the multiplier 105, while of the regenerated carriers generated by the NCO 104, The cosine component (orthogonal component) is multiplied by the multiplier 106. In the Costas loop 101, a predetermined frequency band component of the in-phase component signal obtained by the multiplier 105 is passed by the LPF 107, and this signal is supplied to the phase detector 110, the binarization circuit 111 and the correlation adder 112. Is done. On the other hand, in the Costas loop 101, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 106 is passed by the LPF 108, and this signal is supplied to the phase detector 110 and the correlation adder 113. In the Costas loop 101, phase information detected by the phase detector 110 based on signals output from the LPFs 107 and 108 is supplied to the NCO 104 via the loop filter 109.
[0109]
In the Costas loop 101, the signals output from the LPFs 107 and 108 are supplied to the correlation adders 112 and 113, respectively. As shown in FIG. 9, each of these correlation adders 112 and 113 inverts the first half of the data, that is, the correlation value obtained by integrating the signal A of 20 milliseconds in the GPS receiver 10 and the latter half. The absolute value addition value with the correlation value obtained by integrating the signal B is output. In the Costas loop 101, the signals output from the correlation adders 112 and 113 are supplied to the square sum calculation circuit 114, and the square sum (I) calculated by the square sum calculation circuit 114 is supplied.²+ Q²) Is output as a correlation value (P) for a spreading code whose phase is P. Further, in the Costas loop 101, the signal output from the LPF 107 is supplied to the binarization circuit 111, and information obtained by binarization is output as a navigation message.
[0110]
On the other hand, in the DLL 102, the multiplier 115 multiplies the input IF signal by E (Early) whose phase generated by the PNG 134 is ahead of P and is generated by the PNG 134. The multiplier 116 multiplies a spreading code whose L (Late) phase is later than P. In the DLL 102, the signal obtained by the multiplier 115 is multiplied by a sine component of the reproduced carrier generated by the NCO 104 in the Costas loop 101 by the multiplier 117, and the reproduced carrier generated by the NCO 104 is The cosine component is multiplied by the multiplier 118. In the DLL 102, a predetermined frequency band component of the in-phase component signal obtained by the multiplier 117 is passed by the LPF 119, and this signal is supplied to the correlation adder 121. On the other hand, in the DLL 102, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 118 is passed by the LPF 120, and this signal is supplied to the correlation adder 122. In the DLL 102, the signal obtained by the multiplier 116 is multiplied by the sine component of the reproduction carrier generated by the NCO 104 in the Costas loop 101 by the multiplier 124, and the reproduction generated by the NCO 104 is also performed. The cosine component of the carrier is multiplied by the multiplier 125. In the DLL 102, a predetermined frequency band component of the in-phase component signal obtained by the multiplier 124 is passed by the LPF 126, and this signal is supplied to the correlation adder 128. On the other hand, in the DLL 102, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 125 is passed by the LPF 127, and this signal is supplied to the correlation adder 129.
[0111]
The correlation adders 121, 122, 128, and 129 in the DLL 102 perform the same processing as the processing shown in FIG. 9 and add absolute values of the correlation value obtained by integrating the signal A and the correlation value obtained by integrating the signal B, respectively. Is output. In the DLL 102, signals output from the correlation adders 121 and 122 are supplied to the square sum calculation circuit 123, and the square sum (I) calculated by the square sum calculation circuit 123 is supplied.²+ Q²) Is output as a correlation value (E) for a spreading code whose phase is E. Further, in the DLL 102, the signals output from the correlation adders 128 and 129 are supplied to the square sum calculation circuit 130, and the square sum (I) calculated by the square sum calculation circuit 130 is supplied.²+ Q²) Is output as a correlation value (L) for a spreading code whose phase is L.
[0112]
In the DLL 102, the signals output from the square sum calculation circuits 123 and 130 are supplied to the phase detector 131, and the phase information detected by the phase detector 131 based on these signals is the loop filter 132. Further, based on a signal having a predetermined frequency that is supplied to the NCO 133 via the NCO 133 and generated by the NCO 133, the spreading code of each phase E, P, and L is generated by the PNG 134.
[0113]
Thus, in the channel circuit 91 having the Costas loop 101 and the DLL 102, the sum of the squares of the absolute value addition values of the correlation values of the two signals is obtained by the correlation adders 112, 113, 121, 122, 128, and 129, respectively. Since the integration time length can be increased by using the correlation value, the S / N can be improved and the reception sensitivity can be improved. In the channel circuit 91, the bandwidth of the LPFs 107, 108, 119, 120, 126, and 127 can be narrowed to remove noise before addition. The outputs from each of the correlation adders 112, 113, 121, 122, 128, and 129 are constant regardless of the position where the data is inverted when there is no noise.
[0114]
In the channel circuit 91, as described in Japanese Patent Application No. 2001-190658 filed earlier by the present applicant, the integration time may be a predetermined length equal to or less than 1 bit length of data. Further, in the channel circuit 91, for example, the absolute value addition value of the correlation value is calculated in the 1-bit length cycle of the data by each of the correlation adders 112, 113, 121, 122, 128, and 129, and output for each cycle. May be updated. In this case, the phase control of the DLL 102 is performed in a 1-bit long cycle of data.
[0115]
Now, in the channel circuit 91 shown in FIG. 8 including the demodulator constituted by the conventional Costas loop and DLL, the sum of squares of the in-phase component side output and the quadrature component side output is used as the correlation value. In a state where synchronization is maintained, the output on the orthogonal component side is almost close to noise. Therefore, in the Costas loop and the DLL, in the synchronization holding state, the use of only the output on the in-phase component side is not affected by the noise of the output on the quadrature component side, so that the S / N is improved. In the Costas loop and DLL, in the state where the frequency shift is small but the carrier is not yet synchronized, that is, in the state where there is no phase, the absolute value of the output on the in-phase component side and the output on the quadrature component side is absolute. For the larger value, the square of the absolute value is 1/2 (minimum when the phase error is 45 °) compared to the sum of squares, but the output on the in-phase component side and the quadrature component side Therefore, the sum of squares and S / N are the same even at the minimum.
[0116]
Therefore, in the GPS receiver 10, instead of the sum of squares of the output on the in-phase component side and the output on the quadrature component side, the absolute value of the output on the in-phase component side and the output on the quadrature component side is used as a correlation value to determine synchronization. Perform DLL phase control. Specifically, in the GPS receiver 10, the channel circuit 91₁, 91₂, ..., 91_NAs shown in FIG. 10, a channel circuit 91 ′ shown in FIG. 10 is used.
[0117]
That is, the channel circuit 91 ′, as shown in the figure, outputs the outputs from the correlation adders 112 and 113 to the circuit including the IF carrier synchronization Costas loop 101 in place of the square sum calculation circuit 114 described above. A maximum value selection circuit 141 that outputs a larger value (Max (I, Q)) is provided. In addition, the channel circuit 91 ′ is provided with a selector 142 that selects one of the outputs from the correlation adders 121 and 122 in place of the above-described square sum calculation circuit 123 in the DLL 102 ′ for spreading code synchronization. In addition, a selector 143 that selects one of the outputs from the correlation adders 128 and 129 is provided instead of the square sum calculation circuit 130 described above. Here, when the output from the correlation adder 112 on the in-phase component side is selected by the maximum value selection circuit 141, the selectors 142 and 143 respectively output the outputs from the correlation adders 121 and 128 on the in-phase component side. When the output from the orthogonal component side correlation adder 113 is selected by the maximum value selection circuit 141, the output from the orthogonal component side correlation adders 122 and 129 is selected.
[0118]
In this way, in the channel circuit 91 ′, the output of the in-phase component side and the quadrature component side are used by using a circuit that compares the magnitudes of the two values, not the sum of squares of the output of the in-phase component side and the output of the quadrature component side. Even if the synchronization determination and DLL phase control are performed using the absolute value of the output as a correlation value, the S / N does not deteriorate. In the channel circuit 91 ′, the processing load is also reduced by using the absolute value of the in-phase component side output or the quadrature component side output as the correlation value.
[0119]
In the GPS receiver 10, instead of the channel circuit 91 ′, as shown in FIG. 11, both the spread codes having the phases E and L have the LPF and the correlation adder having a large scale in terms of hardware. Alternatively, a channel circuit 91 ″ having the DLL 102 ″ combined into one unit may be used.
[0120]
That is, in the channel circuit 91 ″, the above-described multipliers 117 and 118 are configured as one multiplier 151, the above-described LPFs 119 and 120 are configured as one LPF 152, and the above-described correlation is provided. The adders 121 and 122 are set as one correlation adder 153. Further, in the channel circuit 91 ″, the above-described multipliers 124 and 125 are configured as one multiplier 154, and the above-described LPFs 126 and 127 are configured as one LPF 155 as the configuration on the spreading code side with the phase L, and the above-described correlation. The adders 128 and 129 are set as one correlation adder 156. Further, the channel circuit 91 ″ is provided with a selector 157 for selecting one of the sine component and the cosine component in the reproduction carrier generated by the NCO 104 in the Costas loop 101.
[0121]
In such a channel circuit 91 ″, when the output from the correlation adder 112 on the in-phase component side is selected by the maximum value selection circuit 141, the sine component of the reproduced carrier generated by the NCO 104 is selected by the selector. This signal is selected by 157 and supplied to multipliers 151 and 152 as a carrier. On the other hand, in the channel circuit 91 ″, when the output from the correlation adder 113 on the orthogonal component side is selected by the maximum value selection circuit 141, the cosine component of the reproduced carrier generated by the NCO 104 is selected by the selector 157. This signal is supplied to the multipliers 151 and 152 as a carrier.
[0122]
As described above, the channel circuit 91 ″ can reduce the LPF and the correlation adder by two as compared with the channel circuit 91 ′. Therefore, the synchronization holding unit including the multi-channels shown in FIG. 25, it is very effective for reducing the circuit scale.
[0123]
Further, in the GPS receiver 10, the channel circuit 91 ″ is improved and, as shown in FIG. 12, based on the gate signal generated by the gate signal generator 168, the phase of the spread code with phases E and L is obtained. The DLL 102 ″ adopts a taudizer system that obtains the difference between the correlation value (E) and the correlation value (L) by switching the multiplier code multiplier input at a frequency sufficiently higher than the LPF band. It can also be a channel circuit 91 ′ ”.
[0124]
That is, the channel circuit 91 ′ ″ generates a gate signal that repeats high and low at a constant cycle by the gate signal generator 168. The frequency of the gate signal is, for example, several tens of kHz when the cutoff frequency of the LPF 165 is 1 kHz. In the channel circuit 91 ′ ″, when the gate signal generated by the gate signal generator 168 is high, the selector 161 selects the spread code having the phase E, and when the gate signal is low, the selector 161 sets the phase. L spreading codes are selected. In the channel circuit 91 ′ ″, the input IF signal is multiplied by the spread code selected by the selector 161 by the multiplier 162, and the carrier is multiplied by the multiplier 164 for this signal. Further, in the channel circuit 91 ′ ″, when the output from the correlation adder 112 on the in-phase component side is selected by the maximum value selection circuit 141, the sine component of the reproduced carrier generated by the NCO 104 is selected by the selector. This signal is selected by 163 and supplied to the multiplier 164 as a carrier. On the other hand, in the channel circuit 91 ′ ″, when the output from the correlation adder 113 on the orthogonal component side is selected by the maximum value selection circuit 141, the cosine component of the reproduced carrier generated by the NCO 104 is selected by the selector. This signal is selected by 163 and supplied to the multiplier 164 as a carrier.
[0125]
In the channel circuit 91 ′ ″, the signal obtained by the multiplier 164 is supplied to the correlation adder 166 via the LPF 165, and the correlation adder 166 calculates the absolute value addition value of the correlation value. The result is supplied to a multiplier 167. In the channel circuit 91 ′ ″, the output from the correlation adder 166 and the gate signal from the gate signal generator 168 are multiplied by the multiplier 167, and the obtained result is supplied to the loop filter 132. At this time, in the channel circuit 91 ′ ″, when the multiplication by the multiplier 167 is performed, the calculation is performed with “1” when the gate signal from the gate signal generator 168 is high and “0” when the gate signal is low. Is called.
[0126]
In such a channel circuit 91 ′ ″, since the LPF and the correlation adder for the spreading codes having the phases E and L are shared, the circuit scale is further reduced as compared with the channel circuit 91 ″. Can be achieved. However, in the channel circuit 91 ′ ″, the S / N is deteriorated by about 3 dB as compared with the channel circuit 91 ″ by adopting the taud dither system. The channel circuit 91 ′ ″ outputs a difference between the correlation value (E) and the correlation value (L). Since this difference can be used for phase control as a phase comparison result, the channel circuit 91 ′ ″ The phase detector provided in the circuits 91, 91 ′, 91 ″ is not necessary.
[0127]
Hereinafter, characteristics of the LPF, the phase detector, the loop filter, and the correlation adder in the above-described channel circuits 91, 91 ′, 91 ″, 91 ′ ″ will be described.
[0128]
First, the LPF will be described.
[0129]
The LPF in the above-described channel circuits 91, 91 ′, 91 ″, 91 ′ ″ removes unnecessary data other than the data band after multiplying the input signal by the spread code and the reproduction carrier. In the GPS receiver 10, there are both cases where it is desired to increase the S / N by narrowing the LPF band as much as possible, and when there is a case where priority is given to the response speed even if the sensitivity slightly deteriorates. The width is preferably variable.
[0130]
Therefore, in the GPS receiver 10, an LPF is configured as shown in FIG. 13 in order to make the bandwidth variable. In the figure, the input signal is assumed to be 1 bit, but it may be multi-bit. In the GPS receiver 10, since the received signal is at a level considerably lower than the thermal noise, even if the analog / digital conversion is performed by binarization, the degradation of S / N is slight.
[0131]
The LPF shown in FIG. 6A is an Infinite Impulse Response (IIR) filter that approximates the transfer function of the RC filter shown in FIG. This LPF is composed of a multiplier 171 that multiplies a 1-bit or multi-bit input signal X [n] by a power of 2 k, and signals Y [n−1] and 2 supplied from a register 175 described later. A multiplier 172 that multiplies the power k, a differencer 173 that takes a difference between the signal Y [n−1] supplied from the register 175 and the signal kY [n−1] obtained by the multiplier 172, and multiplication An adder 174 for adding the signal kX [n] obtained by the adder 171 and the signal (1-k) Y [n-1] obtained by the subtractor 173, and an RC filter obtained by the adder 174 And a register 175 for holding a signal represented by the difference approximation formula of a predetermined bit length. Note that “n” in the input signal X [n] and the output signal Y [n] represents discrete time.
[0132]
In such an LPF, the relationship between the input signal X [n] and the multi-bit output signal Y [n] is
Y [n] = (1-k) Y [n-1] + kX [n]
Thus, the signal output from the adder 174 satisfies this relationship. In this LPF, the sampling frequency is f_sThen, the time constant t_c, Cutoff frequency f_cRespectively
t_c= RC = 1 / (kf_s),
f_c= 1 / (2πRC) = kf_s/ (2π),
k = 1 / (RCf_s)
It becomes. Therefore, in LPF, k = 2^-16And the sampling frequency is f_s= 18.414 MHz, time constant t_cIs 3.56 milliseconds, cutoff frequency f_cBecomes 44.7 Hz.
[0133]
In such an LPF, the input signal X [n] is 1 bit or multi-bit, and the value is “1” or “−1”, but the input signal X [n] and the output signal Y [n] , The register 175 is M bits long, “1” is regarded as “100... 0”, “−1” is regarded as “000.^-LIf (L is an integer), the multiplier 171 that performs an operation of kX [n] can be realized by a barrel shifter that performs a left shift of (ML) bits, and a multiplier that performs an operation of kY [n]. The device 172 can be realized by a barrel shifter that performs L-bit right shift. For example, register 175 is 22 bits long and k = 2^-16Then, the multiplier 171 can be realized by a barrel shifter that performs a 6-bit left shift, and the multiplier 172 can be realized by a barrel shifter that performs a 16-bit right shift. Therefore, in the LPF, when L can be set from the outside, the cutoff frequency f_cCan be made variable in octave units. In the LPF, “0” is regarded as “010... 0”, and the sign of the output signal Y [n] can be determined by comparing the value with this value. Further, in the LPF, the most significant bit of the remaining bit string excluding the most significant bit of the bit string held in the register 175 is inverted and output, so that the value of the output signal Y [n] is 2's complement. Become.
[0134]
Next, the phase detector will be described.
[0135]
The channel circuits 91, 91 ′, 91 ″, 91 ′ ″ are provided with a phase detector 110 in the Costas loop 101. The input to the phase detector 110 may be, for example, a required dynamic range of 10 bits. For example, the upper 10 bits of the signal from the LPF. Here, the most common phase comparison result output that is an output from the phase detector 110 in the Costas loop is a value I × Q obtained by multiplying the output on the in-phase component side and the output on the quadrature component side, Since this value depends on the signal strength and is not preferable, there is a modified Costas loop in which the phase comparison result output is a value Q / I obtained by dividing the output on the quadrature component side and the output on the in-phase component side. This value Q / I is a tangent of the phase difference between the reproduced carrier generated by the NCO 104 and the carrier included in the input signal.
[0136]
Since the calculation of the value Q / I includes division, it is difficult to perform hardware processing and is generally calculated by a CPU. However, processing in a multi-channel Costas loop is performed by one CPU. There is a heavy load.
[0137]
Therefore, in the GPS receiver 10, when the value Q / I is calculated by applying the modified Costas loop, the calculation is approximated as follows to facilitate the configuration by hardware.
[0138]
First, in the GPS receiver 10, the output I on the in-phase component side and the output Q on the quadrature component side are respectively two's complements, and positive / negative is identified from the most significant bit of both, and the absolute value is obtained from the other bits. Is detected. Subsequently, the GPS receiver 10 checks the most significant bit position S where “1” is given as an absolute value. For example, in the GPS receiver 10, when the output I on the in-phase component side is “0001011001”, the seventh bit from the least significant bit is the most significant bit with an absolute value of “1”. The position of the least significant bit is “0” and S = 6. In the GPS receiver 10, the result of right shifting the absolute value of the output Q on the quadrature component side by S bits is added to the result of adding the sign relationship between the output I on the in-phase component side and the output Q on the quadrature component side. The result is converted to a phase comparison result output.
[0139]
Thus, in the GPS receiver 10, the output I on the in-phase component side is 2^SSince the Q / I operation can be replaced with a shift operation, a hardware configuration can be easily realized. Note that the absolute error between the accurate Q / I and the approximate Q / I is small near the phase where the Costas loop with Q / I = 0 is phase-locked. The error can be made sufficiently small.
[0140]
However, when the phase error is close to 90 °, the value of the output Q on the quadrature component side increases and the value of the output I on the in-phase component side decreases, so the value Q / I becomes a large value, and phase detection It is not preferable as a vessel. Therefore, in the GPS receiver 10, when the result of right shifting the absolute value of the output Q on the quadrature component side by S bits is larger than a predetermined value, for example, “2”, the absolute value of the phase comparison result output is set. Set the limiter to "2". In the GPS receiver 10, when the limiter set value is “1”, the range is within ± 45 ° within the range of ± 90 °, and when the limiter set value is “2”, the range is ± 90 °. The phase comparison characteristic has a slope within ± 63.4 °. The phase comparison characteristic when the limiter set value is “2” is as shown in FIG. In the figure, the horizontal axis indicates the angle, and the vertical axis indicates the phase comparison result output. In the GPS receiver 10, the phase comparison result output is a value near the equilibrium point indicated by the black circle in the figure at the time when the carrier reproduced by the NCO 104 and the carrier included in the received signal are synchronized.
[0141]
On the other hand, the phase detector 131 is provided in each of the DLLs 102, 102 ′, and 102 ″ in the channel circuits 91, 91 ′, and 91 ″. The input to the phase detector 131 has, for example, a necessary dynamic range. If it is 10 bits, the upper 10 bits of the signal from the LPF are used. Here, the most common phase comparison result output, which is an output from the phase detector 131 in the DLL, is an output for a spreading code whose phase is E and an output for a spreading code whose phase is L. However, since this value is not preferable because it depends on the signal strength, the output of the phase comparison result should be (E−L) / (E + L).
[0142]
In the GPS receiver 10, the phase detector 131 that calculates the value (E−L) / (E + L) is configured similarly to the phase detector 110 that calculates the Q / I in the Costas loop described above. Can do. In the GPS receiver 10, when the calculation of the value (E−L) / (E + L) is performed, the calculation is approximated as follows to facilitate the configuration by hardware.
[0143]
First, in the GPS receiver 10, the calculation of (EL) and the calculation of (E + L) are performed. Subsequently, the GPS receiver 10 checks the most significant bit position S with “1” in the value (E + L). For example, in the GPS receiver 10, when the value (E + L) is “0001011001”, since the seventh bit from the least significant bit is the most significant bit, the position of the least significant bit is Is "0" and S = 6. Then, in the GPS receiver 10, the result of right shifting the value (E-L) by S bits is sign-extended when the value (E-L) is a negative value, and converted to a two's complement, This value is used as the phase comparison result output.
[0144]
Thus, in the GPS receiver 10, the value (E + L) is 2^SSince the calculation of (E−L) / (E + L) can be replaced with a shift calculation, a hardware configuration can be easily realized. The absolute error between the exact (E−L) / (E + L) and the approximated (E−L) / (E + L) is in the vicinity of the phase lock of the DLL where (E−L) / (E + L) = 0. Therefore, this method can reduce the phase error at the time of synchronization sufficiently though it is an approximation. FIG. 15 shows the phase comparison characteristics when the shift amount of the spreading code with the phase being E and the spreading code with the phase being L is ± 0.5 chips with respect to the spreading code with the phase being P. Become. In the figure, the horizontal axis indicates the phase difference of the spread codes with the unit as a chip, and the vertical axis indicates the phase comparison result output. In the GPS receiver 10, when the reproduction code by the PNG 134 and the spread code included in the received signal are synchronized, the phase comparison result output is a value near the equilibrium point indicated by a black circle in FIG.
[0145]
Next, the loop filter will be described.
[0146]
In the channel circuits 91, 91 ′, 91 ″, 91 ′ ″, the loop filter 109 in the Costas loop 101 and the loop filter 132 in the DLLs 102, 102 ′, 102 ″, 102 ′ ″ are output by the phase detector. The phase error is integrated and the phase of the NCO is controlled by the output. In the GPS receiver 10, the phase comparison is realized by a perfect integration type loop filter that is an optimum filter when there is a frequency offset and a random phase offset.
[0147]
FIG. 16B shows an equivalent circuit of the complete integration type loop filter shown in FIG. The transfer function F (s) in this loop filter is
F (s) = (1−sτ₂) / (Sτ₁), Τ₁= R₁C, τ₂= R₂C
It is. When this is approximated by a difference, the relationship between the input signal X [n] and the output signal Y [n] is
Y [n] = Y [n−1] + a (X [n] −X [n−1]) + bX [n],
a = τ₂/ Τ₁, B = T / τ₁
It becomes. Here, T is a sampling period, and the sampling frequency is sufficiently higher than the cutoff frequency of the LPF. From the above equation, two parameters a and b are set by the loop filter. These parameters a and b are respectively set to a = 2.^A, B = 2^B(A and B are integers), aX [n], aX [n−1], and bX [n] in the above equation can be calculated by left-shifting by A or B bits, The calculation shown in the above equation can be realized by the loop filter shown in FIG.
[0148]
Therefore, in the loop filter, when the values of A and B can be set from the outside, the bandwidth and response speed of the loop filter can be made variable according to the reception situation.
[0149]
In the GPS receiver 10, the frequency of the NCO is controlled by the output from the loop filter, and when the phase error is positive, that is, when the phase is advanced, the frequency is lowered and the phase is delayed, and vice versa. The phase is advanced by increasing the frequency. In the GPS receiver 10, in order to increase the resistance to acceleration, the values of A and B should be set larger and the response speed of the channel circuit should be increased. When the error of the result output becomes large, the control amount for the NCO of the loop filter becomes too large, and the synchronization may be lost.
[0150]
Therefore, in order to avoid such a loss of synchronization, the GPS receiver 10 can set an upper limit value and a lower limit value for the change of the output value from the loop filter with respect to the previous output value, and the calculation change When a (X [n] −X [n−1]) + bX [n] exceeds the set upper limit value or lower limit value, the upper limit value or lower limit value is output by the loop filter. In the GPS receiver 10, the upper limit value and the lower limit value are set, the fluctuation range of the chip rate of the spread code determined from the Doppler shift amount and the accuracy of the TCXO 12 for the DLL, and the NCO control time at the maximum acceleration for the Costas loop. It is determined based on the change amount of the carrier frequency within the period.
[0151]
In the GPS receiver 10, by setting such a limiter, the response speed is fast within the range where there is a phase error or phase change, but the phase does not change suddenly for fluctuations more than expected. When the received signal is recovered, the control can be returned to normal.
[0152]
Next, the correlation adder will be described.
[0153]
In the GPS receiver 10, when the demand for sensitivity is stronger than the response speed, the above-described correlation adders 112, 113, 121, 122, 128, 129, and 166 each have a data length of 1 mm. If the output is performed every second, the correlation detection time becomes longer by adding the outputs more than once in succession, and the S / N is improved.
[0154]
Therefore, in the GPS receiver 10, the channel circuit 91₁, 91₂, ..., 91_NAs shown in FIG. 18, the channel circuit 91 ″ ″ shown in FIG.
[0155]
That is, the channel circuit 91 ″ ″ is an improvement on the channel circuit 91 ′ shown in FIG. 10, and, as shown in FIG. 10, the above-described circuit in the circuit including the Costas loop 101 for IF carrier synchronization is used. A multi-time adder 181 is provided after the maximum value selection circuit 141. The channel circuit 91 ″ ″ is provided with a multiple-time adder 182 after the selector 142 in the DLL 102 ″ ″ for spreading code synchronization, and a multiple-time adder 183 after the selector 143. Is provided.
[0156]
As described above, the channel circuit 91 ″ ″ is provided with the multi-time adders 181, 182 and 183 for continuously adding the output value from the correlation adder having the data length of 1 bit or less, a plurality of times. By outputting the value after the addition as a correlation value for the spreading codes of the phases E, P, and L, the correlation detection time can be lengthened, and the phase after the plurality of additions is obtained for the spreading codes of E and L. By controlling the NCP 133 via the phase detector 131 and the loop filter 132 with the correlation value, the S / N can be improved. In the GPS receiver 10, the number of additions in the multiple adders 181, 182 and 183 can be set from the outside. For example, in the GPS receiver 10, when the number of additions is set to four, a sensitivity improvement of about 6 dB can be expected as compared to the case without addition.
[0157]
In the GPS receiver 10, the control time interval of the DLL 102 ″ ″ is increased by performing the addition a plurality of times. For example, in the GPS receiver 10, the control is performed every 20 milliseconds when there is no addition, whereas the control is performed every 80 milliseconds when the addition is performed four times. . Therefore, in the GPS receiver 10, although the S / N can be improved by performing the addition a plurality of times, the response deterioration of the DLL 102 ″ ″ occurs due to the time delay. For example, the past five values may be added a plurality of times and output every 20 milliseconds. Moreover, in the GPS receiver 10, it is also possible to perform a moving average instead of performing addition several times.
[0158]
Here, especially when the GPS receiver is applied to a moving body, the signal intensity and the carrier frequency are likely to change depending on the surrounding environment, and the reception status is affected by external noise even in a stationary state. The S / N changes with time. Therefore, in the GPS receiver, if the setting of the channel circuit remains fixed, it is not possible to cope with a change in the reception situation, and a situation in which synchronization cannot be maintained is caused.
[0159]
On the other hand, in the GPS receiver 10, the LPF cutoff frequency in the channel circuit, the loop filter coefficients and limiter ranges in the Costas loop and DLL, and the number of additions by the multi-time adder can be set from the outside. . Therefore, in the GPS receiver 10, a change in carrier frequency due to signal strength and acceleration is always detected for all channel circuits by the CPU 26 that controls the entire GPS receiver 10, and settings for each channel are set according to the reception status. By changing dynamically, it is possible to appropriately cope with a change in reception status.
[0160]
In general, in a GPS receiver, in order to improve reception sensitivity, it is necessary to lengthen the correlation detection time length and narrow the LPF bandwidth as much as possible, and to blunt the Costas loop and DLL response to noise. On the other hand, in order to improve the resistance to acceleration, on the contrary, it is necessary to speed up the Costas loop and DLL response to noise. Are incompatible with each other.
[0161]
However, if the received signal is weak and the S / N is low with respect to frequency changes when acceleration is large, the GPS receiver 10 cannot follow even if the response of the Costas loop and DLL is fast. The CPU 26 constantly detects the signal strength in the correlation adder or the multiple adder, and when the signal strength is high, increases the cutoff frequency of the LPF and sets the coefficient so that the loop bandwidth of the loop filter is widened. If the signal strength is low, the LPF cutoff frequency is lowered and the coefficient is set so that the loop bandwidth of the loop filter is narrowed. By setting the loop and DLL responses to be highly noise-resistant, the priority can be changed according to the signal strength. It can be.
[0162]
At this time, in the GPS receiver 10, a threshold value may be set and various settings may be changed according to determination of only the magnitude of the signal strength, but a stepwise combination of the signal strength and the various setting values is a table. , The CPU 26 can respond more flexibly to the signal intensity that changes from moment to moment.
[0163]
As described above, the GPS receiver 10 can increase the time length of correlation detection by performing correlation detection and DLL phase control based on the output value from the correlation adder, and narrow the LPF bandwidth. Furthermore, it is possible to improve resistance to noise according to the characteristics of the phase detector and the loop filter. Therefore, the GPS receiver 10 can improve reception sensitivity compared with a general Costas loop and DLL.
[0164]
Further, the GPS receiver 10 can improve S / N by correlating and adding only one of the output on the in-phase component side and the output on the quadrature component side, and the LPF and the correlation adder. The circuit scale can be greatly reduced.
[0165]
Further, the GPS receiver 10 can further reduce the number of correlation adders although the S / N deteriorates by adopting the taud dither system.
[0166]
Furthermore, the GPS receiver 10 can control the reception sensitivity and the response speed according to the reception situation by dynamically changing the bandwidth of the LPF, the loop bandwidth of the loop filter, and the correlation addition time. Can do. The GPS receiver 10 can improve the balance between reception sensitivity and resistance to acceleration by dynamically changing the setting according to the signal strength.
[0167]
The present invention is not limited to the embodiment described above. For example, although the channel circuit in the GPS receiver 10 has been described in the above-described embodiment, the present invention can be applied to any demodulator that demodulates a spread spectrum signal.
[0168]
In the above-described embodiment, the description has been made assuming that the matched filter 50 previously shown in FIG. 2 or the digital matched filter 60 previously shown in FIG. 3 is used as the synchronization capturing unit 24. Any device that can perform an operation equivalent to the synchronization acquisition operation by the acquisition unit 24 can be applied.
[0169]
Further, although the GPS receiver 10 has been described in the above-described embodiment, the present invention is not limited to any positioning system using a satellite, that is, a receiver to which a GNSS system is applied. Can be applied. Examples of the GNSS system include the above-described GPS system in the United States, GLONASS (Global Navigation Satellites System) in the former Soviet Union, and GALILEO being developed mainly in Europe. The system can be applied.
[0170]
Thus, it goes without saying that the present invention can be modified as appropriate without departing from the spirit of the present invention.
[0171]
【The invention's effect】
As described above in detail, the demodulating device according to the present invention is a demodulating device that demodulates a spread spectrum signal, and establishes synchronization between a reproduced carrier and a carrier included in an input spread spectrum signal. A loop circuit, and a second loop circuit that establishes synchronization between the reproduction code and the spread code included in the input spread spectrum signal. The first loop circuit and the second loop circuit are respectively a carrier and Filter means that passes a predetermined frequency band component of the multiplication value of the spread code and the input spread spectrum signal, and a signal that has passed through the filter means in units of a predetermined length of data 1 bit length or data 1 bit length or less The first correlation value obtained by integrating and the half-length portion of the unit in the input spread spectrum signal among the signals that have passed through the filter means. And a correlation adding means for adding the second correlation value obtained by integrating the rolling signal, controls the phase of the correlation detection and the second loop circuit based on the output value from the correlation adding means.
[0172]
Therefore, the demodulating device according to the present invention inverts the first correlation value obtained by integrating the signal that has passed through the filter means and the half-length portion of the unit in the input spread spectrum signal among the signals that have passed through the filter means. The second correlation value obtained by integrating the signal is added by the correlation adding means, and the correlation detection and the phase control of the second loop circuit are performed based on the obtained output value, thereby improving the reception sensitivity and resistance to acceleration. It is possible to achieve both improvement.
[0173]
The receiving apparatus according to the present invention is a receiving apparatus that receives a signal from a satellite and calculates its own position and velocity, a receiving means for receiving a signal from the satellite, and a reception received by the receiving means. Frequency conversion means for converting the frequency of the signal to a predetermined intermediate frequency, and synchronization acquisition for detecting the phase of the spread code in the intermediate frequency signal obtained by the frequency conversion means and detecting the carrier frequency in the intermediate frequency signal The acquisition means, the phase of the spread code detected by the synchronization acquisition means, and the carrier frequency detected by the synchronization acquisition means for each of a plurality of channels provided independently corresponding to the plurality of satellites. Assigning and setting the phase and carrier frequency of the set spreading code as initial values, and maintaining synchronization between the spreading code and the carrier And a synchronization holding means for demodulating the message included in the intermediate frequency signal, and each of the plurality of channels in the synchronization holding means for demodulating the spread spectrum signal is included in the spread spectrum signal input to the reproduction carrier. A first loop circuit that establishes synchronization with the carrier, and a second loop circuit that establishes synchronization between the reproduction code and the spread code included in the input spread spectrum signal, Each of the second loop circuits includes a filter unit that passes a predetermined frequency band component of a multiplication value of a carrier, a spread code, and an input spread spectrum signal, and a predetermined data having a data 1 bit length or a data 1 bit length or less. The first correlation value obtained by integrating the signal that has passed through the filter means in units of length, and the signal that has passed through the filter means A correlation addition means for adding a second correlation value obtained by integrating a signal obtained by inverting the half length of the unit in the input spread spectrum signal, and each of the plurality of channels is supplied from the correlation addition means. Based on the output value, correlation detection and phase control of the second loop circuit are performed.
[0174]
Therefore, the receiving apparatus according to the present invention inverts the first correlation value obtained by integrating the signal that has passed through the filter means and the half-length portion of the unit in the input spread spectrum signal among the signals that have passed through the filter means. The second correlation value obtained by integrating the signal is added by the correlation adding means, and the correlation detection and the phase control of the second loop circuit are performed based on the obtained output value, and the synchronization between the spread code and the carrier is maintained. By doing so, it is possible to easily acquire and maintain synchronization of spreading codes and carriers in a signal from a satellite, while improving both reception sensitivity and resistance to acceleration.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a GPS receiver shown as an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a matched filter using a transversal filter that can be applied as a synchronization acquisition unit included in the GPS receiver.
FIG. 3 is a block diagram illustrating a configuration of a digital matched filter using FFT that can be applied as a synchronization acquisition unit included in the GPS receiver.
4 is a block diagram for explaining an actual implementation example when the digital matched filter shown in FIG. 3 is applied as a synchronization acquisition unit provided in the GPS receiver. FIG.
FIG. 5 is a block diagram illustrating a configuration of a synchronization holding unit included in the GPS receiver.
FIG. 6 is a diagram for explaining phase alignment of spread codes in a synchronization holding unit provided in the GPS receiver.
FIG. 7 is a diagram for explaining spread code phase correction in a synchronization holding unit included in the GPS receiver;
FIG. 8 is a block diagram illustrating a configuration of a channel circuit included in a synchronization holding unit included in the GPS receiver, and a block diagram illustrating a configuration of a channel circuit provided with a correlation adder.
FIG. 9 is a diagram illustrating processing in a correlation adder.
FIG. 10 is a block diagram illustrating a configuration of another channel circuit included in a synchronization holding unit included in the GPS receiver, and a block diagram illustrating a configuration of a channel circuit that compares the sizes of outputs from a correlation adder. It is.
FIG. 11 is a block diagram for explaining a configuration of still another channel circuit included in the synchronization holding unit included in the GPS receiver, and a configuration of a channel circuit having a DLL in which the LPF and the correlation adder are combined into one; It is a block diagram to explain.
FIG. 12 is a block diagram illustrating the configuration of still another channel circuit included in the synchronization holding unit included in the GPS receiver, and is a block diagram illustrating the configuration of a channel circuit adopting a taudizer system.
13A and 13B are diagrams illustrating the configuration of an LPF, where FIG. 13A shows the configuration of an IIR filter, and FIG. 13B shows the configuration of an RC filter.
FIG. 14 is a diagram illustrating phase comparison characteristics in a Costas loop.
FIG. 15 is a diagram illustrating phase comparison characteristics in DLL.
16A and 16B are diagrams for explaining the configuration of an equivalent circuit of a complete integration type loop filter, in which FIG. 16A shows the configuration of the loop filter, and FIG. 16B shows the equivalent circuit of the loop filter shown in FIG. FIG.
FIG. 17 is a diagram illustrating a configuration of a complete integration type loop filter.
FIG. 18 is a block diagram illustrating the configuration of still another channel circuit included in the synchronization holding unit included in the GPS receiver, and is a block diagram illustrating the configuration of a channel circuit with a long correlation detection time.
FIG. 19 is a diagram illustrating a configuration of a signal from a GPS satellite.
FIG. 20 is a diagram for explaining a conventional spreading code and carrier synchronization process, and a diagram for explaining a frequency search;
FIG. 21 is a block diagram illustrating a general Costas loop and DLL configuration applied to a spread spectrum signal demodulator.
FIG. 22 is a diagram for explaining three phase spread codes generated by a spread code generator;
FIG. 23 is a diagram illustrating an example of an output waveform showing a temporal change in a correlation value detected using a digital matched filter.
[Explanation of symbols]
10 GPS receiver, 11 XO, 12 TCXO, 13 multiplier / divider, 14 antenna, 15 LNA, 16 BPF, 17, 20 amplifier, 18 frequency synthesizer, 19 mixer, 21, 107, 108, 119, 120, 126 , 127, 152, 155, 165 LPF, 22 A / D, 23 Frequency converter, 24 Synchronization acquisition unit, 25 Synchronization holding unit, 26 CPU, 27 RTC, 28 Timer, 29, 62, 64, 67 Memory, 30 Demodulation Circuit, 50 matched filter, 60 digital matched filter, 61, 81 sampler, 63, 66 FFT processing unit, 65, 134 spreading code generator, 68, 103, 105, 106, 115, 116, 117, 118, 124, 125 , 151,154,1 62,164,167,171,172 multiplier, 69 IFFT processing unit, 70 peak detector, 82 RAM, 83 RAM / ROM, 84 DSP, 91, 91₁, 91₂, ..., 91_N, 91 ′, 91 ″, 91 ′ ″, 91 ″ ″ channel circuit, 92 control register, 101 Costas loop, 102, 102 ′, 102 ″, 102 ′ ″, 102 ″ ″ DLL 104, 133 NCO, 109, 132 loop filter, 110, 131 phase detector, 111 binarization circuit, 112, 113, 121, 122, 128, 129, 153, 156, 166 correlation adder, 114, 123, 130 square sum calculation circuit, 141 maximum value selection circuit, 142, 143, 157, 161, 163 selector, 168 gate signal generator, 173 differentiator, 174 adder, 175 register, 181, 182, 183 multiple adders

Claims (22)

A demodulator that demodulates a spread spectrum signal,
A first loop circuit for establishing synchronization between the regenerative carrier and the carrier included in the input spread spectrum signal;
A second loop circuit for establishing synchronization between the reproduction code and the spread code included in the input spread spectrum signal;
Each of the first loop circuit and the second loop circuit includes a filter unit that passes a predetermined frequency band component of a multiplication value of a carrier, a spread code, and the input spread spectrum signal, and
The first correlation value obtained by integrating the signal that has passed through the filter means, with the unit of the data 1 bit length or a predetermined length less than the data 1 bit length, and the spread spectrum signal that has been input among the signals that have passed through the filter means Correlation addition means for adding absolute values to a second correlation value obtained by integrating a signal obtained by inverting the half length part of the unit in
A demodulator that performs correlation detection and phase control of the second loop circuit based on an output value from the correlation adding means.  Each of the first loop circuit and the second loop circuit calculates a sum of squares of the output value on the in-phase component side and the output value on the quadrature component side output from the correlation adding means, and 2. The demodulator according to claim 1, further comprising a square sum calculation means for outputting as a correlation value. The first loop circuit compares the output value on the in-phase component side and the output value on the quadrature component side output from the correlation adding means for the spreading code having the first phase, and determines the larger one. Having a maximum value selection means for output,
The second loop circuit includes an output value on the in-phase component side and an output value on the quadrature component side that are output from the correlation adding means for a spreading code that is a second phase advanced from the first phase. And the output value on the in-phase component side and the quadrature component side output from the correlation adding means for each of the spreading codes that are the third phase delayed from the first phase. Selection means for selecting one of the output values of
The selection means selects the second phase when the output value on the in-phase component side outputted from the correlation addition means for the spreading code having the first phase is selected by the maximum value selection means. And the output value on the in-phase component side output from the correlation adding means for the spreading code and the output value on the in-phase component side output from the correlation adding means for the spreading code on the third phase. On the other hand, when the output value on the orthogonal component side outputted from the correlation adding means for the spreading code to be the first phase is selected by the maximum value selecting means, the second phase and The output value on the orthogonal component side output from the correlation addition means for the spread code to be output, and the output on the orthogonal component side output from the correlation addition means for the spread code to be the third phase Demodulator of claim 1, wherein the selecting. The first loop circuit compares the output value on the in-phase component side and the output value on the quadrature component side output from the correlation adding means for the spreading code having the first phase, and determines the larger one. Having a maximum value selection means for output,
When the output value on the in-phase component side output from the correlation adding unit is selected by the maximum value selecting unit, the second loop circuit outputs the in-phase component of the carriers in the first loop circuit. On the other hand, when the output value on the orthogonal component side output from the correlation adding means is selected by the maximum value selecting means, the carrier of the orthogonal component among the carriers in the first loop circuit is selected. A selection means to select;
For the carrier code selected by the selection means for each of a spreading code that is a second phase advanced from the first phase and a spreading code that is a third phase delayed from the first phase 2. A demodulating device according to claim 1, further comprising multiplying means for multiplying.  The second loop circuit includes gate signal generating means for generating a predetermined gate signal, and based on the gate signal generated by the gate signal generating means, the spreading code to be the second phase and A dither scheme is employed in which the multiplier code multiplier input is switched at a frequency slower than the rate of the spreading code as the third phase and sufficiently higher than the bandwidth of the filter means. The demodulator according to claim 4.  When the input spread spectrum signal is a binary signal, the filter means in the first loop circuit has a 1-bit or multi-bit input, a multi-bit output, and a transfer function of an RC filter. The demodulator according to claim 1, wherein the demodulator is a digital filter that approximates the difference between the two.  The filter means in the first loop circuit makes the coefficient a power of 2 by performing multiplication only by a shift operation, and makes the cutoff frequency variable in octave units by making the setting of the coefficient variable. The demodulator according to claim 6.  The first loop circuit converts the output of the filter means that passes the signal on the in-phase component side into an exponent N when approximated by a power of 2, and the output from the filter means that passes the signal on the quadrature component side 2. The demodulator according to claim 1, wherein a value obtained by shifting the value to the right by the exponent N bits is used as a phase comparison result output.  The first loop circuit is provided with a limiter for limiting an output value when a value obtained by right shifting an output value from the filter means that passes a signal on an orthogonal component side by the exponent N bits exceeds a predetermined value. The demodulator according to claim 8.  The second loop circuit includes an output value output from the correlation adding means for a spreading code having a second phase advanced from the first phase, and a third delayed from the first phase. The sum of the output value output from the correlation adding means for the spreading code set as the phase is converted to an exponent M when approximated by a power of 2, and the spreading code set as the second phase is set as described above. A phase comparison result obtained by shifting the difference value between the output value output from the correlation adding means and the output value output from the correlation adding means for the spreading code having the third phase to the right by the exponent M bits 9. The demodulator according to claim 8, wherein the demodulator is an output. The first loop circuit and the second loop circuit each have loop filter means for controlling the phase of the reproduction carrier or the reproduction code by integrating a phase error,
2. A demodulator according to claim 1, wherein said loop filter means is a digital filter obtained by approximating a transfer function of an active filter by a difference.  The loop filter means performs the multiplication only by a shift operation, so that the two coefficients are 2A and 2B using the integers A and B, and the loop bandwidth and the setting of the integers A and B are variable. 12. The demodulator according to claim 11, wherein the response speed is variable in units of octaves.  Each of the first loop circuit and the second loop circuit is provided with a limiter for an output value from the loop filter means, and an upper limit value and a lower limit value of the limiter are variable. Item 13. A demodulator according to item 12. Each of the first loop circuit and the second loop circuit has a plurality of addition means for adding the output value from the correlation addition means having a data length of 1 bit or less continuously over a plurality of times,
2. The demodulator according to claim 1, wherein correlation detection and phase control of the second loop circuit are performed based on an output value from the multiple addition means. Each of the first loop circuit and the second loop circuit has moving average means for moving and averaging the output values from the correlation adding means having a data length of 1 bit or less,
2. The demodulator according to claim 1, wherein correlation detection and phase control of the second loop circuit are performed based on an output value from the moving average means.  2. The first loop circuit and the second loop circuit each dynamically change a cutoff frequency of the filter means in accordance with a reception state of the spread spectrum signal. Demodulator.  Each of the first loop circuit and the second loop circuit increases the cutoff frequency of the filter means when the signal strength is high, and cuts off the cutoff frequency of the filter means when the signal strength is low. 17. The demodulator according to claim 16, wherein the demodulator is lowered. The first loop circuit and the second loop circuit each have loop filter means for controlling the phase of the reproduction carrier or the reproduction code by integrating a phase error,
Each of the first loop circuit and the second loop circuit includes a range of a limiter provided in a coefficient of the loop filter unit and an output value from the loop filter unit according to the reception status of the spread spectrum signal, respectively. The demodulator according to claim 1, wherein is dynamically variable.  The first loop circuit and the second loop circuit each set a coefficient so that the loop bandwidth of the loop filter means is wide when the signal strength is large, and when the signal strength is small. 19. The demodulator according to claim 18, wherein the coefficient is set so that the loop bandwidth of the loop filter means is narrowed. Each of the first loop circuit and the second loop circuit has a plurality of addition means for adding the output value from the correlation addition means having a data length of 1 bit or less continuously over a plurality of times,
The first loop circuit and the second loop circuit each dynamically change the number of additions of the plurality of addition means according to the reception status of the spread spectrum signal. The demodulator described. The first loop circuit is a Costas loop circuit,
2. The demodulator according to claim 1, wherein the second loop circuit is a delay lock loop circuit. A receiving device that receives a signal from a satellite and calculates its position and velocity,
Receiving means for receiving a signal from the satellite;
Frequency converting means for converting the frequency of the received signal received by the receiving means to a predetermined intermediate frequency;
Synchronization acquisition means for detecting the phase of a spread code in the intermediate frequency signal obtained by the frequency conversion means and detecting the carrier frequency in the intermediate frequency signal;
The satellite of the phase of the spreading code detected by the synchronization acquisition means and the carrier frequency detected by the synchronization acquisition means for each of a plurality of channels independently provided corresponding to the plurality of satellites Synchronous holding is performed by allocating and setting each of the spreading codes and the carrier frequency as initial values, and maintaining the synchronization between the spreading code and the carrier and demodulating the message included in the intermediate frequency signal. Means and
The plurality of channels in the synchronization holding means for demodulating the spread spectrum signal are respectively
A first loop circuit for establishing synchronization between the regenerative carrier and the carrier included in the input spread spectrum signal;
A second loop circuit that establishes synchronization between the reproduction code and the spread code included in the input spread spectrum signal;
Each of the first loop circuit and the second loop circuit includes a filter unit that passes a predetermined frequency band component of a multiplication value of a carrier, a spread code, and the input spread spectrum signal, and
The first correlation value obtained by integrating the signal that has passed through the filter means, with the data 1 bit length or a predetermined length less than the data 1 bit length as a unit, and the spread spectrum signal that has been input among the signals that have passed through the filter means Correlation addition means for adding absolute values to a second correlation value obtained by integrating a signal obtained by inverting the half-length portion of the unit in each of the plurality of channels, wherein each of the plurality of channels is an output value from the correlation addition means. And a phase control of the second loop circuit.

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