JP2003244024A - Demodulator and receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain the compatibility between improvement of reception sensitivity and immunity to acceleration. <P>SOLUTION: A synchronization holding section in a GPS receiver has a plurality of channel circuits 91 assigned to each satellite. A carrier synchronization Costas loop 101 and a spread code synchronization DLL 102 in each channel circuit 91 individually have: low pass filters (LPFs) for passing a prescribed frequency band component of a product of a carrier, a spread code and a received spread spectrum signal; and correlation adders each summing a first correlation value resulting from integrating a signal passing through the LPF in the unit of data 1-bit length or a prescribed length being the data 1-bit length or below and a second correlation value obtained by integrating the signal resulting from inverting the part of a half of the length of the unit in the received spread spectrum signal among the signals passing through the LPF. Each channel circuit 91 performs correlation detection and applies phase control of the DLL 102 on the basis of the output from each correlation adder. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation device for demodulating a spread spectrum signal and a receiving device to which the demodulation device is applied, which is a so-called GNSS (Global Navigatio).
n Satellites System) for receiving a signal from a satellite and calculating its own position and velocity.

[0002]

2. Description of the Related Art In recent years, a GNSS system for measuring the position of a moving body on the ground by using an artificial satellite has become popular. As this GNSS system, for example, Global Positioning System (hereinafter, GP)
It is called S. ). In this GPS system, G
A GPS receiver that receives signals from PS satellites receives signals from at least four or more GPS satellites, calculates the position of the GPS receiver based on the received signals,
Notifying the user is a basic function.

That is, the GPS receiver demodulates the signal from each GPS satellite to obtain the orbit information of each GPS satellite, and based on the orbit and time information of each GPS satellite and the delay time of the received signal, The three-dimensional position of the GPS receiver is derived by simultaneous equations. In the GPS system, it is necessary to have at least four GPS satellites to obtain a reception signal because there is an error between the internal time set by the clock of the GPS receiver and the time set by the atomic clock of the GPS satellite. This is because the pseudo distances from at least four GPS satellites are required to calculate the four unknown parameters of the three-dimensional position from which the influence of 1 is removed and the accurate time.

In the GPS system, a GP for consumer use
When the S receiver is used, positioning calculation is performed by receiving a spread spectrum signal radio wave called the C / A (Clear and Acquisition) code in the L1 band from the GPS satellite (Navstar).

The transmission signal called the C / A code in the L1 band has a transmission signal speed, that is, a chip rate of 1.
023 MHz, for example, a so-called Gold code or the like having a code length of 1023 is pseudo-random noise (Pseudo-rando).
m Noise; PN) sequence spreading code, the frequency of which is 1575.42 due to a signal obtained by directly spreading data of 50 bps.
2 for MHz carrier (hereinafter referred to as carrier)
Binary Phase Shift Keying;
This is a signal that has been modulated based on the BPSK modulation method.
In this case, since the code length is 1023, the C / A code has a spread code of 10 as shown in the first row in FIG.
23 chips are set as one cycle, that is, one cycle = 1 millisecond (msec) and repeated.

The spread code of the C / A code is different for each GPS satellite, but which GPS satellite uses which spread code can be detected in advance by a GPS receiver. In addition, the GPS receiver can recognize which GPS satellite from which signal can be received at that point and at that point in time by a navigation message described later. Therefore, the GPS receiver
For example, in the case of three-dimensional positioning, by receiving radio waves from at least four or more GPS satellites that can be acquired at that point and at that point, despreading the spectrum and performing positioning calculation, the position of one's own can be determined. calculate.

Further, one bit of the signal data from the GPS satellite is transmitted in units of 20 cycles of the spread code, that is, in units of 20 milliseconds, as shown in the second row in FIG. That is, the data transmission rate is 50b as described above.
ps. Further, 1023 chips for one cycle of the spread code are inverted when the bit is "1" and "0".

Further, the signal from the GPS satellite forms one word in 30 bits, that is, 600 milliseconds, as shown in the third row in FIG. Furthermore, the signal from the GPS satellite is, as shown in the fourth row in the figure, 10 words,
That is, one subframe is formed in 6 seconds. And
In the signal from the GPS satellite, as shown in the fifth row in the figure, the preamble that is always the specified bit pattern is inserted in the first word of one subframe even when the data is updated. Data is transmitted following this preamble.

Further, the signal from the GPS satellite is 5
A subframe, that is, one frame is formed in 30 seconds. Then, in the signal from the GPS satellite, the navigation message described above is transmitted in the data unit of this one frame.

The first 3 of the 1 frame data
Each subframe is information unique to the GPS satellite called Ephemeris information. This ephemeris information includes a parameter for determining the orbit of the GPS satellite and the time at which the signal from the GPS satellite is transmitted.

Since all GPS satellites are equipped with atomic clocks, they use common time information, and the time at which the signals from the GPS satellites contained in the ephemeris information are sent out is in units of 1 second of the atomic clocks. The spread code of the GPS satellite is generated as being synchronized with the atomic clock.

The orbit information included in the ephemeris information is
The information is updated every few hours, but the same information remains until the update is performed. Therefore, the GPS receiver can accurately use the same orbit information for several hours by holding the orbit information included in the ephemeris information in the memory. The signal transmission time from the GPS satellite is updated every second.

On the other hand, the navigation messages of the remaining two subframes of the data of one frame are information called Almanac information commonly transmitted from all GPS satellites. This almanac information requires 25 frames to acquire all the information, and the approximate position information of each GPS satellite and which GP
It is composed of information and the like indicating whether the S satellite can be used. This almanac information is updated every few months, but remains the same until the update. Therefore, the GPS receiver can accurately use the same information for several months by holding the almanac information in the memory.

The GPS receiver receives a signal from a GPS satellite and obtains the above-described data. First, after removing the carrier, the same C / A code as that used by the GPS satellite to be received is used. Using the spreading code, the GP
With respect to the signal from the S satellite, the signal from the GPS satellite is captured by performing the phase synchronization of the C / A code, and the spectrum inverse spread is performed. When the GPS receiver performs spectrum despreading in phase synchronization with the C / A code, bits are detected and it is possible to acquire a navigation message including time information based on the signal from the GPS satellite. Become.

The GPS receiver captures signals from GPS satellites by phase synchronization search of C / A code. As the phase synchronization search, the spread code and GP generated by itself are used.
The correlation between the received signal from the S satellite and the spread code is detected. For example, when the correlation value of the correlation detection result is larger than a predetermined value, it is determined that the two are synchronized. When the GPS receiver determines that the synchronization is not achieved, it uses some synchronization method to control the phase of the spreading code generated by itself and synchronize with the spreading code of the received signal. There is.

By the way, the signal from the GPS satellite is a signal obtained by modulating the carrier based on the BPSK modulation method by the signal obtained by spreading the data with the spreading code as described above. Therefore, the GPS receiver needs to synchronize not only the spread code but also the carrier and the data in order to receive the signal from the GPS satellite, but the spread code and the carrier cannot be synchronized independently.

In addition, the GPS receiver usually has an intermediate frequency (Intermed) within a few MHz of the carrier frequency of the received signal.
iate Frequency; hereinafter referred to as IF. ) To convert the received signal into an IF signal, and the above-described synchronization detection processing is performed with this IF signal. The carrier in this IF signal (hereinafter referred to as the IF carrier) is mainly G
Frequency error due to Doppler shift according to the moving speed of the PS satellite and GPS when converting the received signal to an IF signal
The frequency error component of the local oscillator generated inside the receiver is included.

Therefore, in the GPS receiver, since the IF carrier frequency is unknown due to these frequency error factors, it is necessary to search for that frequency.
Further, the synchronization point (synchronization phase) within one cycle of the spread code is
Since it is unknown because it depends on the positional relationship between the GPS receiver and the GPS satellites, the GPS receiver needs some synchronization method as described above.

The conventional GPS receiver uses a synchronization method that combines frequency search for carriers, synchronization acquisition by a sliding correlator, and synchronization holding by a DLL (Delay Locked Loop) and Costas loop. Hereinafter, this synchronization method will be described.

As a clock for driving a spread code generator of a GPS receiver, a clock obtained by dividing a reference frequency oscillator prepared in the GPS receiver is generally used. A high-precision crystal oscillator is used as the reference frequency oscillator, and the GPS receiver uses a local oscillation signal used to convert a reception signal from a GPS satellite into an IF signal based on the output of the reference frequency oscillator. To generate.

FIG. 20 shows the processing contents of the frequency search. The GPS receiver performs a phase synchronization search for the spread code when the frequency of the clock signal that drives the spread code generator is a certain frequency f1. That is, the GPS receiver sequentially shifts the phase of the spread code by one chip to obtain G at each chip phase.
Detects the correlation between the received signal from the PS satellite and the spread code,
By detecting the peak of correlation, the phase in which synchronization can be achieved is detected. Further, when the frequency of the clock signal is f1, the GPS receiver changes, for example, the frequency division ratio for the reference frequency oscillator when there is no synchronized phase in all of the 1023 chip phase searches. Change the frequency of the signal to another frequency f2
A phase search for 023 chips is performed. The GPS receiver realizes a frequency search by changing the frequency of the clock signal stepwise and repeating such an operation.

When the GPS receiver detects the frequency of the clock signal that can be synchronized by performing such frequency search, the GPS receiver performs final phase synchronization of the spread code with the frequency of the clock signal. This makes G
The PS receiver can capture the signal from the GPS satellite even if the oscillation frequency of the crystal oscillator has a deviation.

Costas loop and DL applied to a spread spectrum signal demodulator including a GPS receiver
L is generally configured as shown in FIG. In this circuit, the Costas loop 201 synchronizes the IF carrier, and the DLL 202 synchronizes the spreading code.

That is, in the Costas loop 201, the phase generated by a spreading code generator (PN Generator; hereafter referred to as PNG) 228, which will be described later in the second stage in FIG. 22, is applied to the input IF signal. A signal obtained by multiplying the spreading code of P (Prompt) by the multiplier 203 is input. On the other hand, the DLL 202 receives the IF signal.

In the Costas loop 201, an NCO (Numeric Controlled Oscillator) is applied to the input signal.
The sine component (in-phase component) of the regenerated carrier generated by the NCO 204 is multiplied by the multiplier 205, while the cosine component (quadrature component) of the regenerated carrier generated by the NCO 204 is multiplied by the multiplier 206.
Is multiplied by. In the Costas loop 201, a predetermined frequency band component of the in-phase component signal obtained by the multiplier 205 is passed by the LPF 207, and this signal is detected by the phase detector 210, the binarization circuit 211, and the sum of squares calculation circuit 212. Is supplied to. On the other hand, in the Costas loop 201, the predetermined frequency band component of the quadrature component signal obtained by the multiplier 206 is the LPF.
This signal is passed by 208 and this signal is detected by the phase detector 210.
And the sum of squares calculation circuit 212. In the Costas loop 201, the phase information detected by the phase detector 210 based on the signals output from the LPFs 207 and 208 is supplied to the NCO 204 via the loop filter 209. Also, Costas Loop 20
In No. 1, the signals output from the LPFs 207 and 208 are supplied to the sum of squares calculation circuit 212, and the calculated sum of squares (I ² + Q ² ) is the correlation for the spread code whose phase is P. It is output as a value (P). Further, in the Costas loop 201, the signal output from the LPF 207 is supplied to the binarization circuit 211, and the information obtained by binarization is output as a navigation message.

In this way, the Costas Loop 201 smells
The spread of the three phases generated by the PNG228.
Of the spread codes, the phase shown in the second row in the figure is P
The scattered code is used. At Costas Loop 201
LPF 20 in order to detect the synchronization of the IF carrier.
Sum of squares (I
^Two+ Q^Two) Is used as a correlation value (P) to determine synchronization.

On the other hand, in the DLL 202, E (Early) shown in the first stage in the figure in which the phase generated by the PNG 228 is ahead of P with respect to the input IF signal.
Is multiplied by the multiplier 213, and the spreading code of L (Late) shown in the third stage in the figure in which the phase generated by the PNG 228 is delayed by P is multiplied by the multiplier 214. To be done. In the DLL 202, the signal obtained by the multiplier 213 is multiplied by the sine component of the reproduced carrier generated by the NCO 204 in the Costas loop 201 by the multiplier 215 and the reproduced carrier generated by the NCO 204 is multiplied. The cosine component is multiplied by the multiplier 216. And DLL202
In, the predetermined frequency band component of the in-phase component signal obtained by the multiplier 215 is passed by the LPF 217, and this signal is supplied to the sum of squares calculation circuit 219. On the other hand, in the DLL 202, a predetermined frequency band component of the quadrature component signal obtained by the multiplier 216 is passed by the LPF 218, and this signal is supplied to the square sum calculation circuit 219. Further, in the DLL 202, the signal obtained by the multiplier 214 is multiplied by the sine component of the reproduced carrier generated by the NCO 204 in the Costas loop 201 by the multiplier 220, and the reproduced signal generated by the NCO 204 is also multiplied. The cosine component of the carrier is multiplied by the multiplier 221. And DLL202
In, the predetermined frequency band component of the signal of the in-phase component obtained by the multiplier 220 is passed by the LPF 222, and this signal is supplied to the sum of squares calculation circuit 224. On the other hand, in the DLL 202, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 221 is passed by the LPF 223, and this signal is supplied to the sum of squares calculation circuit 224.

In DLL 202, the signals output from each of the square sum calculation circuits 219 and 224 are supplied to the phase detector 225, and the phase information detected by the phase detector 225 based on these signals is loop filtered. Is supplied to the NCO 227 via 226, and further N
Based on the signal having a predetermined frequency generated by CO 227, each phase E, P, L is generated by PNG 228.
Spreading codes are generated. Further, in the DLL 202, the sum of squares (I ² + Q ² ) calculated by the sum of squares calculation circuit 219 is output as the correlation value (E) for the spreading code whose phase is E, while the square is calculated. The sum of squares (I ² + Q ² ) calculated by the sum calculation circuit 224 is output as the correlation value (L) for the spreading code whose phase is L.

As described above, in the DLL 202, P
Of the three-phase spreading codes generated by the NG 228, the two-phase spreading codes whose phases are E and L shown in the first and third stages in the figure are used. DLL202
In order to detect the spread code synchronization,
The sum of squares (I ² + Q ² ) of the signals output from each of 217 and 218 is used as the correlation value (E), and the LPF
Synchronization determination is performed using the sum of squares (I ² + Q ² ) of the signals output from 222 and 223 as the correlation value (L).
The values of the correlation value (E) and the correlation value (L) change depending on the integration time of each LPF, but in the DLL 202, the signal includes a point where the data is inverted, and when the point where the data is inverted is sandwiched, the LPF is sandwiched. Output fluctuates to a minimum value of 0. Therefore, in the DLL 202, the sum of squares (I ² + Q ² )
In the case of using as a correlation value, the LPF integration time is not stable unless the integration time is one cycle of the spreading code. Where GPS
In the receiver, the period of the spread code is 1 millisecond, so the integration time of the LPF is 1 millisecond, which is up to about 1 kHz when converted by the bandwidth.

However, such a conventional synchronization method is not suitable for high-speed synchronization in principle. In the GPS receiver, if it takes time to synchronize the spread code and the IF carrier, the reaction becomes slow, which causes inconvenience in use. Therefore, in an actual GPS receiver, in order to compensate for this drawback, the number of channels is increased and parallel processing is performed to shorten the time until synchronization acquisition.

On the other hand, a matched filter is used as a method for performing synchronous acquisition of a spread spectrum signal at high speed in place of the method using the sliding correlation described above. The matched filter can be realized digitally by a so-called transversal filter. Also,
As a matched filter, recent DSP (Digital Si
Fast Fourier Transform (Fast Fourier Transfor
m; hereinafter referred to as FFT. ) Has been used to implement a method for synchronizing spread codes at high speed with a digital matched filter. The latter is based on a long-known method for speeding up correlation calculation.

By using these matched filters, the GPS receiver detects a correlation peak when there is a correlation, for example, as shown in FIG. 23 for one cycle of the output waveform. The position of this peak indicates the beginning of the spread code. By detecting this peak, the GPS receiver can capture synchronization, that is, detect the phase of the spread code in the received signal. Also, GPS
The receiver can detect the IF carrier frequency together with the phase of the spread code by operating the FFT in the frequency domain using, for example, the above-described digital matched filter using the FFT. Then, the GPS receiver can convert the phase of the spread code into a pseudorange, calculate the position of the GPS receiver when at least four GPS satellites are detected, and calculate the IF carrier frequency. Based on this, the speed of the GPS receiver can be calculated.

[0033]

By the way, the above-mentioned D
In a GPS receiver using the LL and Costas loop, it is expected that the reception area will be expanded by increasing the sensitivity, and at the same time, resistance to acceleration will be required.

In this GPS receiver, in order to realize high sensitivity, it is necessary to take the bit inversion of the navigation message into consideration and make a correlation with the spread code in order to increase the time length of the correlation detection. Further, in the GPS receiver, the bandwidth of the signal is narrowed so that the S / N (Signal to Nois
e ratio) needs to be improved.

On the other hand, in the GPS receiver, the tolerance to acceleration is the tolerance to the change of the carrier frequency due to the change of the Doppler frequency due to the movement of the GPS receiver, and is to increase the response speed. . Therefore, in the GPS receiver, improving the resistance to acceleration is basically contrary to narrowing the band in high sensitivity.

Therefore, in the DLL and Costas loop, one of the sensitivity enhancement and the acceleration resistance is prioritized depending on the application, or both are balanced, or dynamically controlled according to the reception condition. It is preferable that the above can be dealt with according to the setting.

These problems are not limited to GPS receivers, but are common to all mobile communications that employ a direct spread modulation method with the same spread spectrum as GPS signals.

The present invention has been made in view of the above circumstances, and demodulates a spread spectrum signal capable of improving the reception sensitivity and improving the resistance to acceleration as compared with a general DLL and Costas loop. The purpose is to provide a device. It is another object of the present invention to provide a receiving device to which this demodulation device is applied and which can easily perform synchronization acquisition and synchronization holding of a spread code and a carrier in a signal from a GPS satellite.

[0039]

A demodulator according to the present invention that achieves the above-mentioned object is a demodulator for demodulating a spread spectrum signal, which is composed of a reproduction carrier and a carrier included in the input spread spectrum signal. A first loop circuit that establishes synchronization and a second loop circuit that establishes synchronization between the reproduction code and the spread code included in the input spread spectrum signal are provided, and the first loop circuit and the second loop circuit are provided.
The loop circuit of (1) has a filter means for passing a predetermined frequency band component of the multiplication value of the carrier, the spread code, and the input spread spectrum signal, and a 1-bit data length or a predetermined length equal to or shorter than the 1-bit data length. A unit, a first correlation value obtained by integrating the signal that has passed through the filter means,
Correlation adding means for adding a second correlation value obtained by integrating a signal obtained by inverting a half length unit of the input spread spectrum signal of the signals that have passed through the filter means. Correlation detection and phase control of the second loop circuit are performed based on the output value of the.

Such a demodulator according to the present invention has a first correlation value obtained by integrating the signal passed through the filter means,
A second correlation value obtained by integrating a signal obtained by inverting a half length unit of the input spread spectrum signal of the signal that has passed through the filter means is added by the correlation adding means, and based on the obtained output value. Correlation detection and phase control of the second loop circuit are performed.

Further, the receiving device according to the present invention which achieves the above-mentioned object is a receiving device for receiving a signal from a satellite to calculate its own position and velocity, and a receiving means for receiving a signal from the satellite. A frequency conversion means for converting the frequency of the reception signal received by the reception means into a predetermined intermediate frequency, and a synchronous acquisition and intermediate frequency signal for detecting the phase of the spread code in the intermediate frequency signal obtained by the frequency conversion means. And a carrier frequency detected by the synchronization acquisition means, the phase of the spread code detected by the synchronization acquisition means, and the carrier frequency detected by the synchronization acquisition means It is set by allocating to each satellite for each of the channels, and the phase and carrier frequency of the set spreading code are set as initial values. , A synchronization holding means for holding the synchronization between the spread code and the carrier and for demodulating the message included in the intermediate frequency signal. And a second loop circuit that establishes synchronization with a carrier included in the input spread spectrum signal, and a second loop circuit that establishes synchronization between the reproduced code and the spread code included in the input spread spectrum signal. The first loop circuit and the second loop circuit respectively include a filter unit that passes a predetermined frequency band component of the multiplication value of the carrier, the spread code, and the input spread spectrum signal, and the data 1 A first phase obtained by integrating a signal that has passed through the filter means in a unit of a bit length or a predetermined length equal to or less than one bit length of data. A plurality of correlation adding means for adding a value and a second correlation value obtained by integrating a signal obtained by inverting a half length unit of the input spread spectrum signal of the signal that has passed through the filter means; Each channel is characterized by performing correlation detection and phase control of the second loop circuit based on the output value from the correlation adding means.

Such a receiving apparatus according to the present invention has a first correlation value obtained by integrating the signal passed through the filter means,
A second correlation value obtained by integrating a signal obtained by inverting a half length unit of the input spread spectrum signal of the signals that have passed through the filter means is added by the correlation adding means, and based on the obtained output value. While the correlation detection and the phase control of the second loop circuit are performed, the spread code and the carrier are held in synchronism.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments to which the present invention is applied will be described in detail below with reference to the drawings.

This embodiment is a so-called GNSS in which the position of a moving body on the ground is measured using an artificial satellite.
(Global Navigation Satellites System) Global Positioning System
ystem; hereinafter referred to as GPS. ) Is applied, and signals from at least four or more GPS satellites are received, and the position of itself is calculated based on the received signals.
It is a PS receiver. This GPS receiver is L1 band, C /
A spread-spectrum signal radio wave called A (Clear and Acquisition) code is received as a reception signal, and is more common than a general DLL (Delay Locked Loop) and Costas loop applied as a demodulator for demodulating a spread-spectrum signal. It is possible to improve the reception sensitivity and the resistance to acceleration.

As shown in FIG. 1, this GPS receiver itself generates pseudo-random noise (PN) when demodulating a received signal.
By separating the function of capturing the synchronization between the spreading code of the sequence and the spreading code in the received signal and the function of maintaining the synchronization between the spreading code and the carrier (hereinafter referred to as carrier), a small circuit scale can be obtained. In addition, it is possible to speed up the synchronization acquisition. In the GPS receiver 10, the DLL and Costas loop do not need to operate as those for performing synchronization acquisition, as will be described later, as long as they can operate as the synchronization holding unit 25 that holds the synchronization between the spreading code and the carrier. Instead, DLLs and Costas loops are expected to expand the reception area due to higher sensitivity, and on the other hand, are required to have resistance to acceleration. Therefore, in the GPS receiver 10, improvement of the reception sensitivity of DLL and Costas loop and improvement of resistance to acceleration are realized.

In the following, first, the overall structure of the GPS receiver 10 in which the synchronization acquisition function and the synchronization holding function are separated will be described, and then the synchronization acquisition unit 24 and the synchronization holding unit 2 will be described.
5 will be described in detail, and thereafter, a specific configuration of the synchronization holding unit 25 will be described in detail.

First, the overall structure of the GPS receiver will be described.

The GPS receiver 10 is, as shown in FIG.
A crystal oscillator (X'tal Oscillator; hereinafter referred to as XO) 11 that generates an oscillation signal D1 having a predetermined oscillation frequency.
And a predetermined oscillation frequency F _OSC different from this XO11
Compensated X'tal Oscillator (Temperature Compensated X'tal Oscillator) for generating an oscillation signal D2 having
It is called TCXO. ) 12 and a multiplier / divider 13 for multiplying and / or dividing the oscillation signal D2 supplied from the TCXO 12.

The XO 11 generates an oscillation signal D1 having a predetermined oscillation frequency of, for example, 32.768 kHz. The XO 11 uses the generated oscillation signal D1 for RT described later.
Supply to C (Real Time Clock) 27.

The TCXO12 is different from the XO11 and has a predetermined oscillation frequency F _OSC of, for example, about 18.414 MHz.
Generate an oscillating signal D2. The TCXO 12 supplies the generated oscillation signal D2 to the multiplier / divider 13 and the frequency synthesizer 18 described later.

The multiplier / divider 13 is a CPU (Ce
The oscillation signal D2 supplied from the TCXO 12 is multiplied by a predetermined multiplication rate and / or divided by a predetermined division ratio based on the control signal D3 supplied from the ntral processing unit 26. The multiplication / frequency divider 13 includes a synchronization acquisition unit 24, which will be described later, a synchronization holding unit 25, which will be described later, a CPU 26, a timer 28, which will be described later, and an oscillation signal D4 that has been multiplied and / or divided.
And to a memory 29 described later.

The GPS receiver 10 further includes an antenna 14 for receiving an RF (Radio Frequency) signal transmitted from a GPS satellite and a low noise amplifier (Low) for amplifying the received RF signal D5 received by the antenna 14. Noise Amplifier; hereinafter referred to as LNA.) 15
And the amplified RF signal D amplified by this LNA 15.
Band pass filter (hereinafter, referred to as BPF) 16 that passes a predetermined frequency band component out of 6
And the amplified RF signal D passed by this BPF 16
7, a frequency synthesizer 18 for generating a local oscillation signal D10 having a predetermined frequency F _LO based on the oscillation signal D2 supplied from the TCXO 12, and a predetermined frequency F _RF amplified by the amplifier 17. A mixer 19 for multiplying the amplified RF signal D8 having the local oscillation signal D10 supplied from the frequency synthesizer 18, and a predetermined frequency F _IF down-converted by being multiplied by the mixer 19.
Intermediate Frequency;
It is called IF. ) An amplifier 20 that amplifies the signal D11, and a low pass filter (hereinafter referred to as LPF) 21 that passes a predetermined frequency band component of the amplified IF signal D12 amplified by the amplifier 20.
The analog-type amplified IF signal D13 passed by the LPF 21 is converted to the digital-type amplified IF signal D14.
Analog / digital converter (Analog / Digit)
al Converter; hereinafter referred to as A / D. ) 22 and.

The antenna 14 receives the RF signal transmitted from the GPS satellite, in which the carrier having the frequency of 1575.42 MHz is spread. The received RF signal D5 received by the antenna 14 is supplied to the LNA 15.

The LNA 15 amplifies the received RF signal D5 received by the antenna 14. The LNA 15 supplies the amplified amplified RF signal D6 to the BPF 16.

The BPF 16 is a so-called SAW (Surface).
Acoustic wave) filter, and passes a predetermined frequency band component of the amplified RF signal D6 amplified by the LNA 15. The amplified RF signal D7 passed by the BPF 16 is supplied to the amplifier 17.

The amplifier 17 further amplifies the amplified RF signal D7 passed by the BPF 16. Amplifier 17
Is the amplified predetermined frequency F _RF , that is, 157
The amplified RF signal D8 of 5.42 MHz is supplied to the mixer 19.

Under the control of the control signal D9 supplied from the CPU 26, the frequency synthesizer 18 is controlled by the TCX.
A local oscillation signal D10 having a predetermined frequency F _LO is generated based on the oscillation signal D2 supplied from O12. The frequency synthesizer 18 uses the generated local oscillation signal D10.
Is supplied to the mixer 19.

The mixer 19 down-converts the amplified RF signal D8 by multiplying the amplified RF signal D8 having a predetermined frequency F _RF amplified by the amplifier 17 by the local oscillation signal D10 supplied from the frequency synthesizer 18. Then, the IF signal D11 having a predetermined frequency F _IF of, for example, about 1.023 MHz is generated. The IF signal D11 generated by the mixer 19 is supplied to the amplifier 20.

The amplifier 20 amplifies the IF signal D11 down-converted by the mixer 19. Amplifier 2
0 supplies the amplified amplified IF signal D12 to the LPF 21.

The LPF 21 passes a lower band component than the predetermined frequency of the amplified IF signal D12 amplified by the amplifier 20. The amplified IF signal D13 passed by the LPF 21 is supplied to the A / D 22.

The A / D 22 converts the analog amplified IF signal D13 passed by the LPF 21 into a digital amplified IF signal D14. The amplified IF signal D14 converted by the A / D 22 is supplied to the synchronization acquisition unit 2
4 and the synchronization holding unit 25.

In the GPS receiver 10, among these components, the LNA 15, the BPF 16, the amplifier 1
7, 20, frequency synthesizer 18, mixer 19, LP
The F21 and the A / D 22 amplify the received RF signal D5 having a high frequency of 1575.42 MHz received by the antenna 14 and having a low frequency F _IF of, for example, about 1.023 MHz so as to facilitate digital signal processing. The frequency conversion unit 23 down-converts the IF signal D14.

Further, the GPS receiver 10 performs synchronous acquisition of the spread code generated by itself and the expanded code in the amplified IF signal D14 supplied from the A / D 22 and synchronous acquisition for detecting the carrier frequency in the amplified IF signal D14. The unit 24 and the amplified IF signal D14 supplied from the A / D 22
The synchronization holding unit 25 that holds the synchronization between the spreading code and the carrier and demodulates the message, the CPU 26 that collectively controls each unit to perform various arithmetic processes, and the time based on the oscillation signal D1 supplied from XO11. RTC to measure
27, a timer 28 as an internal clock of the CPU 26,
RAM (Random Access Memory) and ROM (Read Only M)
a memory 29 including an emory) and the like.

The synchronization acquisition unit 24, which will be described in detail later, is C
Under the control of the PU 26, based on the frequency-multiplied and / or frequency-divided oscillation signal D4 supplied from the frequency multiplier / frequency divider 13, synchronization acquisition of the spread code in the amplified IF signal D14 supplied from the A / D 22 is performed. And the carrier frequency in the amplified IF signal D14 is detected. At this time, the synchronization acquisition unit 24 performs synchronization acquisition with coarse accuracy, as will be described later. The synchronization acquisition unit 24 supplies the satellite number for identifying the detected GPS satellite, the phase of the spread code, and the carrier frequency to the synchronization holding unit 25 and the CPU 26.

The synchronization holding unit 25, which will be described in detail later, is C
Under the control of the PU 26, based on the multiplied and / or divided oscillation signal D4 supplied from the multiplier / divider 13, the spread code and carrier in the amplified IF signal D14 supplied from the A / D 22 While keeping the synchronization of
The navigation message included in the amplified IF signal D14 is demodulated. At this time, the synchronization holding unit 25, as described later,
The operation is started with the satellite number, the phase of the spread code, and the carrier frequency supplied from the synchronization acquisition unit 24 as initial values. The synchronization holding unit 25 uses the amplification I from a plurality of GPS satellites.
The F signal D14 is held in synchronism in parallel, and the detected spread code phase, carrier frequency, and navigation message are supplied to the CPU 26.

The CPU 26 acquires the phase of the spread code, the carrier frequency, and the navigation message supplied from the synchronization holding unit 25, and based on these various information, the GP concerned.
The position and speed of the S receiver 10 are calculated, and various arithmetic processing related to GPS, such as correcting the time information of the GPS receiver 10 based on accurate time information of GPS satellites obtained from the navigation message, is performed. Also, C
The PU 26 centrally controls each unit of the GPS receiver 10, various peripherals, and input / output with the outside.

The RTC 27 measures time based on the oscillation signal D1 supplied from the XO 11. This RTC2
The time information measured by 7 is used until the accurate time information of the GPS satellite is obtained.
It is appropriately corrected by controlling O11.

The timer 28 functions as an internal clock of the CPU 26, and is used for generating various timing signals necessary for the operation of each section and for time reference. For example, in the GPS receiver 10, the timer 28 refers to the timing at which the synchronization holding unit 25 starts the operation of the spreading code generator described later in synchronization with the phase of the spreading code acquired by the synchronization acquisition unit 24.

The memory 29 is composed of RAM, ROM and the like. In the memory 29, a RAM is used as a work area when various processes are performed by the CPU 26 and the like, when buffering various input data, and when storing intermediate data and calculation result data generated in the calculation process. Also RAM is used. Further, in the memory 29, a ROM is used as a means for storing various programs and fixed data.

In the GPS receiver 10, these synchronization acquisition unit 24, synchronization holding unit 25, CPU 26, R
The TC 27, the timer 28, and the memory 29 are configured as a baseband processing unit.

A GPS receiver 10 including each of the above components
In the above, at least each of the units except the XO 11, the TCXO 12, the antenna 14, the LNA 15, and the BPF 16 can be configured as a demodulation circuit 30 that is formed of one integrated chip.

The GPS receiver 10 receives RF signals from at least four or more GPS satellites, converts the RF signals into IF signals by the frequency conversion unit 23, and then synchronizes the spread codes by the synchronization acquisition unit 24. The acquisition and the detection of the carrier frequency are performed, and the synchronization holding unit 25 holds the synchronization between the spreading code and the carrier and demodulates the navigation message. Then, the GPS receiver 10 determines the CPU based on the phase of the spread code, the carrier frequency, and the navigation message.
The position and speed of the GPS receiver 10 are calculated by 26.

Now, the synchronization acquisition unit 24 and the synchronization holding unit 25 in such a GPS receiver 10 will be described in detail below. As described above, the GPS receiver 10 has the synchronization acquisition function and the synchronization holding function separated into the synchronization acquisition unit 24 and the synchronization holding unit 25. Here, the reason why the functions are separated in this way will also be described.

The synchronization acquisition unit 24, as described above,
The synchronization of the spread code in the signal and the detection of the carrier frequency are performed at high speed. The synchronization acquisition unit 24 uses a matched filter in order to perform synchronization acquisition of the spread code at high speed. Specifically, the synchronization acquisition unit 24 can use a so-called transversal filter 50 as the matched filter, as shown in FIG. 2, for example.

As the matched filter, the synchronization acquisition section 24 can also use a digital matched filter 60 utilizing a fast Fourier transform (hereinafter referred to as FFT), as shown in FIG. 3, for example.

Specifically, the digital matched filter 60, as shown in the figure, has an amplified IF signal D14 obtained by the antenna 14 and the frequency conversion unit 23 described above.
The IF signal corresponding to is sampled by the sampler 61 that samples the input signal at a predetermined sampling frequency based on the oscillation signal D2 generated by the TCXO 12 described above, and then input. The digital matched filter 60 includes a memory 62 that buffers the IF signal sampled by the sampler 61, an FFT processing unit 63 that reads the IF signal buffered by the memory 62 and performs FFT, and the FFT.
A memory 64 for buffering a frequency domain signal obtained by the FFT processing by the processing unit 63;
Spreading code generator 65 that generates the same spreading code as the spreading code in the RF signal from the satellite, and this spreading code generator 6
5, an FFT processing unit 66 that performs an FFT process on the spread code generated by the signal 5, a memory 67 that buffers the frequency domain signal obtained by the FFT processing performed by the FFT processing unit 66, and a buffer in the memory 64. Multiplier 68 for multiplying the frequency domain signal being ringed and the frequency domain signal being buffered in memory 67
And an inverse FFT (Inversed Fast Fourier Transfor) for the frequency domain signal multiplied by the multiplier 68.
m; hereinafter referred to as IFFT. ) The IFFT processing unit 69 that performs the processing, and the spreading code and the spreading code generator 6 in the RF signal from the GPS satellite based on the autocorrelation function obtained by the IFFT processing unit 69 performing the IFFT processing.
5 has a peak detector 70 for detecting the peak of the correlation with the spreading code.

Such a digital matched filter 6
0 is actually a DSP (Digital Signal Process) for each unit of the FFT processing units 63 and 66, the spreading code generator 65, the multiplier 68, the IFFT processing unit 69, and the peak detector 70.
or) is implemented as software executed by. That is, the synchronization acquisition unit 24 to which the digital matched filter 60 is applied has a sampler 81 corresponding to the above-mentioned sampler 61, a RAM 82 corresponding to the above-mentioned memory 62, and the above-mentioned memory 6 as shown in FIG.
4, 67, a RAM / ROM 83 including a DSP program and a work area, the above-mentioned FFT processing unit 63,
DSP for executing the processing of 66, spreading code generator 65, multiplier 68, IFFT processing section 69, and peak detector 70
And 84.

In the example shown in FIG.
An IF signal of 1.023 MHz is sampled by the sampler 81 at 4.096 MHz, and the DSP 84 performs an operation equivalent to that of the digital matched filter 60 to perform synchronous acquisition of the spread code, that is, phase detection of the spread code in the IF signal. It can be performed with a precision of / 4 chip. Further, the synchronization acquisition unit 24 is a RAM
If the capacity of 82 is 16 milliseconds, DSP
By operating the FFT in the frequency domain by 84, with an accuracy of 1/16 kHz (± 1/32 kHz),
The carrier frequency in the IF signal (hereinafter referred to as the IF carrier) can be detected. Synchronization acquisition unit 24
Since the IF signal stored in the RAM 82 includes signals from a plurality of GPS satellites, a plurality of GPS signals are calculated by calculating the correlation with the spread code of each GPS satellite.
Satellites can be detected.

The GPS receiver 10 has the synchronization acquisition unit 24.
The position and speed of the GPS receiver 10 can be calculated based on the phase of the spread code and the carrier frequency for at least four GPS satellites detected by.

However, in the GPS receiver 10, the above-mentioned ¼ chip as the phase detection accuracy of the spread code,
And 1/16 kHz as detection accuracy of carrier frequency
It is hard to say that the calculation result of the position and speed of the GPS receiver 10 obtained based on the above is sufficiently accurate. GP
In the S receiver 10, in order to improve accuracy,
Increase the sampling frequency by the sampler 81, I
Processing such as lengthening the time length for storing the F signal is required, but with this, the capacity of the memory such as the RAM 82 increases and the processing time until the phase and carrier frequency of the spread code are detected. It is assumed that it will be long. Further, in the GPS receiver 10, the synchronization acquisition unit 2
If 4 does not receive navigation messages from the outside, it is necessary to demodulate navigation messages from at least 4 or more GPS satellites every 20 milliseconds.
The SP 84 always needs to detect synchronization and demodulate navigation messages very quickly. These problems bring about an increase in cost and power consumption due to the enormous size of hardware.

Therefore, in the GPS receiver 10, the synchronization acquisition unit 24 performs the synchronization acquisition with coarse accuracy, and the synchronization holding unit 25 holds the synchronization of a plurality of GPS satellites and demodulates the navigation message.

The synchronization acquisition unit 24 supplies the detected satellite number of the GPS satellite, the phase of the spread code, and the carrier frequency to the synchronization holding unit 25. On the other hand, the synchronization holding unit 25
The operation is started with these various kinds of information supplied from the synchronization acquisition unit 24 as initial values. The synchronization holding unit 25 adjusts the start timing of the spreading code generated by the DLL circuit described later based on the phase of the spreading code. The GPS receiver 10 sets the spreading code corresponding to the satellite number of the detected GPS satellite as the spreading code to be generated. At this time, G
In the PS receiver 10, Doppler shift, TCXO
Although it is affected by the error in the oscillation frequency of the oscillation signal generated by the oscillator such as 12, the spreading code is basically repeated in a cycle of 1 millisecond, so that the spreading code generated by the DLL circuit is The start timing may be shifted by an integral multiple of 1 millisecond.

Since the IF carrier frequency includes the error of the TCXO 12 which generates the sampling clock for fetching the IF signal into the memory such as the RAM 82 described above, it is accurate even if the above problem of resolution is eliminated. Value, that is, the sum of the carrier frequency and the Doppler shift amount. However, the GPS receiver 1
At 0, when the synchronization acquisition unit 24 and the synchronization holding unit 25 operate with the same oscillator, that is, the clock having the TCXO 12 as an oscillation source, both have exactly the same frequency error. 25 is a synchronization acquisition unit 24
There is no problem in starting the operation using the IF carrier frequency detected by the initial value.

[0084] synchronization holding unit 25 from performing the synchronization holding of a plurality of GPS satellites in parallel, for example, as shown in FIG. 5, a plurality of independent channels circuit ₉₁ 1, ₉₁ 2,
..., 91 _N. Channel circuits 91 ₁ , 91
₂ , ..., 91 _N are respectively assigned to the individual detection results by the synchronization acquisition unit 24 by the setting of the control register 92.

Channel circuits 91 ₁ , 91 ₂ , ...,
Each of the 91 _N is configured by a circuit in which a Costas loop for IF carrier synchronization and a DLL for spreading code synchronization are combined, which will be described in detail later.

Channel circuits 91 ₁ , 91 ₂ , ..., 91 which are constituted by a circuit in which a Costas loop for IF carrier synchronization and a DLL for spreading code synchronization are combined.
_{In the} synchronization holding unit 25 having _N , before the operation starts,
The satellite number of the GPS satellite, the phase of the spread code, and the carrier frequency are set as initial values. This initial value is set by directly communicating with the synchronization acquisition unit 24 or via the CPU 26 which controls the synchronization acquisition unit 24 and the synchronization holding unit 25.

The synchronization holding unit 25 as described above synchronizes the spread code with the synchronization as follows. That is, as shown in FIG. 6, the synchronization acquisition unit 24 starts a timer at the timing at which the IF signal is taken into the memory such as the RAM 82, and the phase of the spread code with respect to the IF signal stored in the memory by the synchronization acquisition unit 24. When h is detected, the synchronization holding unit 25 receives the value of this phase h, and then starts the spreading code generated by the DLL at the time point shifted by h from the integer multiple of 1 millisecond by the same timer. Match the phase with the spreading code of the signal. In addition, "
“PN” indicates a PN sequence code, that is, a spreading code.

Here, in the conventional circuit combining the Costas loop and the DLL, since the phase of the spread code in the received signal is unknown, the IF carrier frequency generated by the DLL and the cycle of the spread code are slightly shifted. , In the process of sliding the phase with respect to the spread code of the IF signal, a phase having a significant strength correlation was detected. Therefore, in the conventional circuit, in the case of detecting the phase, in the worst case, the carrier frequency in the range of several kHz and all the phases in the spread code having the code length of 1023 are detected. It took a long time to establish.

On the other hand, in the GPS receiver 10, the phase of the spreading code received by the synchronization holding unit 25 and the IF
Since the initial value with respect to the carrier frequency deviates only slightly from the true value, the phase having a significant intensity correlation is always present near the initial value even if an error is included. Therefore,
As with the conventional circuit, the synchronization holding unit 25 first sets the NCO (Numeric Controlled Oscillato) to a state in which the control of the loop filter in the Costas loop and the DLL is stopped.
The signal generated by r) is changed near the initial value to search for a correlation of significant intensity, and after detecting the correlation, the control is switched to the loop filter. As a result, the synchronization holding unit 25 can establish synchronization of the phase of the spread code by the DLL and establishment of the synchronization of the phase of the carrier by the Costas loop in an extremely short time, and thereafter can keep the synchronization. In the synchronization holding unit 25, since the IF carrier frequency can be set to an initial value with an accuracy of several tens Hz, the bandwidth of each LPF and each loop filter can be narrowed from the beginning, and the S / N (Signal t
o Synchronization can be established with a high Noise ratio).

In the GPS receiver 10, the synchronization holding unit 25 is, for example, 1.023 MHz × 16 = 16.368 M.
When the phase of the spread code is detected with a time resolution of 1 / 16.368 MHz in the DLL by operating with a clock of Hz, the GPS is calculated from the phase of the spread code with an accuracy of 1/16 chip.
If the pseudo-range to the satellite can be calculated and the NCO in the Costas loop can be controlled in units of 1 Hz, the IF carrier frequency resolution will be 1 Hz, and the DLL and Costas loop will synchronize with these precisions. Can be held.

As described above, in the GPS receiver 10, when the synchronization holding unit 25 holds the synchronization, D
The position of the GPS receiver 10 can be continuously calculated and output based on the phase of the spreading code generated by LL, and the GPS receiver 10 can be calculated based on the IF carrier frequency obtained by the Costas loop.
The speed of can be continuously calculated and output.

As described above, the synchronization holding unit 25 sets the phase of the spreading code and the IF carrier frequency passed from the synchronization acquisition unit 24 as initial values, so that significant strength is obtained in the vicinity of these initial values. Search for the phase at which the correlation is obtained. This is due in part to the fact that the clock source oscillator on board the GPS receiver 10, the TCXO 12, has an error with respect to the nominal frequency. In the GPS receiver 10, when the synchronization acquisition unit 24 is configured using the digital matched filter 60 using the FFT shown in FIG. 3, the IF signal is stored in the memory and then the DSP processing time Since the detection result is supplied to the synchronization holding unit 25 with a delay, the nominal frequency F _{OSC of the} oscillator is
Assuming that the error between and is ΔF _OSC and the processing time of the DSP is T seconds, an error of T × ΔF _OSC / F _OSC occurs when the detection result is supplied to the synchronization holding unit 25. For example, in the GPS receiver 10, T = 3 seconds and ΔF
_{If OSC} / F _OSC is within ± 3 ppm, ± 9
An error occurs within microseconds of about ± 9 chips. As described above, in the GPS receiver 10, the longer the DSP processing time, the larger the error.

Further, in the GPS receiver 10, the GP
The Doppler shift of the carrier frequency caused by the movement of the S satellite and the GPS receiver 10 also causes an error. In the GPS receiver 10, assuming that the frequency of the carrier, that is, 1575.42 MHz is F _RF, and the Doppler shift of the received signal is ΔF _D , the period of the spreading code due to the Doppler shift, that is, 1 ms is
It is almost (1-ΔF _D / F _{R F} ) times, for example, +5 to +5.
When the Doppler shift in the range of -5 kHz occurs, about -9.5 to 9.5 microseconds in about 3 seconds = about -9.
An error of 5 to 9.5 chips occurs.

These two examples are values that are relatively close to reality, and in the GPS receiver 10, when factors of both the error of the oscillator and the Doppler shift are combined, the error is within a range of about ± 20 chips. Therefore, the correlation may be detected by searching only this range. For example, the synchronization holding unit 25 starts the spreading code generated by the DLL by 20 chips earlier than the phase of the spreading code supplied from the synchronization capturing unit 24, and as the cycle of the spreading code at that time,
If the NCO frequency setting is set to be longer than (1 + 5 / 1575.420) milliseconds, the sliding of the spread code of the signal from the GPS satellite included in the IF signal will be +.
It is possible to search for the presence / absence of a correlation in a state where the phases of the spread codes are sliding for a suitable time, starting from a time point shifted by 20 chips.

As described above, conventionally, the correlation detection is performed by using the DLL and the Costas loop within the range of 1023 chips and the IF carrier frequency within the range of the error of the oscillator and the Doppler shift amount. Compared to what was done, in the GPS receiver 10,
Since the carrier frequency of the initial value has only a slight error and the range for detecting the correlation is only about several tens of minutes, the time required for establishing synchronization by the synchronization holding unit 25 can be made extremely short. .

As described above, the GPS receiver 10 is configured so that the synchronization acquisition function and the synchronization holding function are separated, so that the G signal included in the IF signal by the synchronization acquisition unit 24.
The phase of the spread code of the signal from the PS satellite and the IF carrier frequency can be detected at high speed, and the synchronization holding unit 25 can quickly shift to the synchronization holding operation based on the detection result. However, in the GPS receiver 10, when the processing sequence increases in order to detect a weak GPS satellite signal included in the IF signal, and the synchronization acquisition unit 24 is operated with a low-speed clock in order to suppress power consumption. In the case where it is set, the processing time in the synchronization acquisition unit 24 becomes long, and accordingly, the range to be searched until the synchronization is established by the synchronization holding unit 25 becomes wide, which is not preferable.

Generally, in a GPS receiver, the frequency
In the local oscillator in the converter and the baseband processor
Common as a source oscillator that generates a clock for signal processing
Using the crystal oscillator of
Similarly, as shown in FIG.
The source oscillator of the local oscillator in the conversion unit 23 and the synchronization acquisition unit 2
4 and the source oscillator of the operation clock of the synchronization holding unit 25,
Common to TCXO12. Then, the synchronization holding unit 25
Is the IF carrier frequency detected by the synchronization acquisition unit 24.
Based on the number and the nominal value of TCXO12, eg 1.023M
Intermediate frequency F of Hz _IFAnd the difference is ΔF_IFAnd 15
Carry of signals from GPS satellites at 75.42 MHz
A frequency is F_RFThen, the synchronization acquisition unit 24 outputs the IF signal.
The time required for the synchronization acquisition processing after being loaded into memory is T seconds
And the phase of the spreading code is h, as shown in FIG.
, The phase h of the spreading code is h + Δh (Δh = −T × ΔF
_IF/ Δ_{R F}) Is corrected. For example, ΔF_IF=
When +3 kHz and T = 10 seconds, Δh = −19 My
Crosecond = about -19 chips. The synchronization holding unit 25 is
With the correction like
Diffusion caused by vibration frequency error and Doppler shift
It is possible to correct the phase shift of the code extremely accurately,
It takes several tens of seconds for the synchronization acquisition processing by the synchronization acquisition unit 24.
Even if it is, even if you search in the range of about 1 chip
Synchronization can be established.

The reason why such a correction is possible is as follows.

In the GPS receiver 10, frequency conversion
By the unit 23, the known signal of the GPS satellite is known.
Rear frequency F_RFKnown intermediate frequency F_IFConversion to
In order to_OSCOn the TCXO12
Based on the local oscillator frequency by the frequency synthesizer 18.
Number F_LO= N × F_OSC(N is a constant number, N >> 1)
Made, F_IF= F_RF-F_LOSo that here
Therefore, the signal from the GPS satellite actually received is
Wave number F_IFAgainst TCXO12 erroneous oscillation frequency
Error ΔF caused by difference and Doppler shift_IFAdded
It has been crossed. That is, the GPS receiver 10
The Doppler shift amount by ΔF_DAnd to TCXO12
Error from the nominal oscillation frequency by ΔF_OSCThen, F_IF+ ΔF_IF= F_RF+ ΔF_D-F_LO= F_RF+
ΔF_D-Nx (F_{OS C}+ ΔF_OSC) Becomes Therefore, in the GPS receiver 10,
The IF carrier frequency detected by the period acquisition unit 24 is F_IF+ ΔF_IF, ΔF_IF= ΔF_D−N × ΔF_OSC Becomes What is important here is that the synchronization acquisition unit 24 detects
Can be ΔF_IFAnd only ΔF_D, Δ
F_OSCIs unknown at the initial acquisition stage
That is.

[0100] Here, the spreading code of the TCXO12
The timer operates at the nominal oscillation frequency for 1 millisecond, which is one cycle length.
If it does, the error ΔF_OSCTo be real
In case of 1 millisecond x F_OSC/ (F_OSC+ Δ
F_OSC) ≈ (1-ΔF_OSC/ F_{O SC}) Milliseconds
It On the other hand, one cycle length of the spread code in the received signal is
Doppler shift amount ΔF_D1 ms × F_RF/
(F_RF+ ΔF_D) ≈ (1-ΔF _D/ F_RF) With milliseconds
Become. Therefore, one cycle of the spread code in the received signal
Counted by length and nominal oscillation frequency by TCXO12
The ratio to 1 millisecond is (1-ΔF_D/ F_RF) / (1-ΔF_OSC/
F_OSC) ≈1-ΔF_D/ F_{R F}+ ΔF_OSC/ F
_OSC Becomes Furthermore, if the right side of this equation is transformed, 1-ΔF_IF/ F_RF+ (ΔF_OSC/ F_OSC) ×
(F_IF/ (N × F_{OS C})) ≈ 1-ΔF_IF/ F_RF Becomes Thus, in the GPS receiver 10, the same
ΔF which is an unknown parameter for the period capturing unit 24_D，
ΔF_OSCMake a fairly good approximation without
You can

As a result, in the GPS receiver 10, the synchronization acquisition processing is performed from the time when the synchronization acquisition unit 24 acquires the IF signal into the memory, and the detected phase h of the spread code is supplied to the synchronization holding unit 25. If it takes T seconds to reach, the phase of the spread code detected by the synchronization acquisition unit 24 during this T seconds is shifted by −T × ΔF _IF / F _RF . Therefore, as shown in FIG. 7, the synchronization holding unit 25 generates the DLL by h + Δh obtained by adding the correction value Δh = −T × ΔF _IF / F _RF to the phase h of the spread code supplied from the synchronization acquisition unit 24. By adjusting the start timing of the spreading code to be used, it is possible to correct the phase shift of the spreading code that occurred during the synchronization acquisition processing time.
As a result, the correlation can be detected within a range of about 1 chip, and the synchronization can be established in an extremely short time. In the GPS receiver 10, for example, the CPU 26 calculates a correction value, supplies the calculation result to the synchronization holding unit 25, corrects the phase by the synchronization holding unit 25, and then starts the synchronization acquisition process by the synchronization acquisition unit 24. Good.

The information necessary for such a method of correcting the phase of the spread code is only the IF carrier frequency detected by the synchronization acquisition unit 24. In the GPS receiver 10, the error of the oscillation frequency due to the TCXO 12 is also Doppler. The shift amount is also unnecessary as information. Further, in the GPS receiver 10, it does not depend on the IF carrier frequency,
Local oscillation frequency F such that F _IF = F _RO −F _{LO
Even when LO} is set, it is only necessary to change the sign of ΔF _IF .

Now, a specific configuration of the synchronization holding unit 25 as described above will be described below.

Channel circuit 9 in synchronization holding unit 25
_{1 1, 91 2, ···,} 91 N , as described above, the circuit that combines the DLL for Costas loop and the diffusion code synchronization for IF carrier synchronization applied as a demodulator for demodulating a spread spectrum signal Can be configured by.

Here, the conventional Costas loop and DLL are used.
In the above, the synchronization determination is performed using the sum of squares of the output from the LPF on the in-phase component (I) side and the output from the LPF on the quadrature component (Q) side as a correlation value.

On the other hand, in the GPS receiver 10, as shown in FIG. 8, the Costas loop 101 is newly provided with a correlation adder 112 in order to improve the reception sensitivity and the resistance to acceleration. , 113, and the DLL 102 is newly provided with a correlation adder 1
21, 122, 128, and 129 are provided, and synchronization determination is performed using the sum of squares of the outputs of these correlation adders as a correlation value.

That is, the channel circuits 91 ₁ , 9
1 _2, ..., 91 in the _N, respectively, as shown in the figure, the Costas loop 101, amplified IF obtained by the antenna 14 and the frequency converter 23 described above
With respect to the IF signal corresponding to the signal D14, a spread code generator (PN Generator; hereinafter referred to as PNG) 1 described later.
The signal generated by multiplying the spread code generated by 34 with the phase of P (Prompt) by the multiplier 103 is input. Meanwhile, the channel circuit _{91 1,} 91 2, ...,
In 91 _N , the IF signal corresponding to the amplified IF signal D14 obtained by the antenna 14 and the frequency conversion unit 23 described above is input to the DLL 102, respectively.

In the Costas loop 101, the sine component (in-phase component) of the reproduced carrier generated by the NCO 104 is multiplied by the multiplier 1 with respect to the input signal.
While being multiplied by 05, the cosine component (orthogonal component) of the reproduced carrier generated by the NCO 104 is multiplied by the multiplier 106. In the Costas loop 101, the predetermined frequency band component of the signal of the in-phase component obtained by the multiplier 105 is the LPF 10
7 and this signal is detected by the phase detectors 110, 2
It is supplied to the binarization circuit 111 and the correlation adder 112. On the other hand, in the Costas loop 101, a predetermined frequency band component of the quadrature component signal obtained by the multiplier 106 is passed by the LPF 108, and this signal is supplied to the phase detector 110 and the correlation adder 113. In the Costas loop 101, the phase detector 11 is based on the signals output from the LPFs 107 and 108, respectively.
The phase information detected by 0 is the loop filter 109
Is supplied to the NCO 104 via.

In the Costas loop 101,
The signals output from the LPFs 107 and 108 are supplied to the correlation adders 112 and 113, respectively. These correlation adders 112 and 113 respectively have a 1-bit length of data, that is, the GPS receiver 1 as shown in FIG.
At 0, the correlation value obtained by integrating the signal A of 20 milliseconds,
The absolute value addition value with the correlation value obtained by integrating the signal B inverted in the latter half is output. In the Costas loop 101, the signals output from the correlation adders 112 and 113 are supplied to the square sum calculation circuit 114, and the square sum (I ² + Q ²⁾ calculated by the square sum calculation circuit 114 is calculated. )
Is the correlation value (P) for the spreading code whose phase is P
Is output as. Further, in the Costas loop 101, the signal output from the LPF 107 is supplied to the binarization circuit 111, and the information obtained by binarization is output as a navigation message.

On the other hand, in the DLL 102, the input IF signal is multiplied by the spreading code, which is E (Early), in which the phase generated by the PNG 134 leads P, and is also multiplied by the PNG 13.
The phase generated by 4 is later than P (L)
The spread code that is defined as is multiplied by the multiplier 116.
In the DLL 102, the NCO in the Costas loop 101 is applied to the signal obtained by the multiplier 115.
The sine component of the reproduced carrier generated by 104 is multiplied by the multiplier 117, and NC
A multiplier 118 multiplies the cosine component of the reproduced carrier generated by O104. And
In the DLL 102, a predetermined frequency band component of the in-phase component signal obtained by the multiplier 117 is the LPF.
119, and this signal is passed through the correlation adder 121.
Is supplied to. On the other hand, in the DLL 102, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 118 is passed by the LPF 120, and this signal is supplied to the correlation adder 122. Also, DLL10
2, the signal obtained by the multiplier 116 is multiplied by the sine component of the reproduced carrier generated by the NCO 104 in the Costas loop 101 by the multiplier 124, and the reproduced carrier generated by the NCO 104 is multiplied. The cosine component is multiplied by the multiplier 125. And DLL10
In 2, the predetermined frequency band component of the in-phase component signal obtained by the multiplier 124 is passed by the LPF 126, and this signal is supplied to the correlation adder 128. On the other hand, in the DLL 102, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 125 is passed by the LPF 127, and this signal is supplied to the correlation adder 129.

The correlation adder 121 in the DLL 102,
Each of 122, 128, and 129 performs the same processing as that shown in FIG. 9, and outputs the absolute value addition value of the correlation value obtained by integrating the signal A and the correlation value obtained by integrating the signal B. DL
In L102, the signals output from the correlation adders 121 and 122 are supplied to the square sum calculation circuit 123, and the square sum (I
² + Q ² ) is output as the correlation value (E) for the spreading code whose phase is E. Further, in the DLL 102, the signals output from the correlation adders 128 and 129 are supplied to the square sum calculation circuit 130, and the square sum (I ² + Q ² ) calculated by the square sum calculation circuit 130.
Is the correlation value (L) for the spreading code whose phase is L
Is output as.

In the DLL 102, the signals output from the square sum calculation circuits 123 and 130 are supplied to the phase detector 131, and the phase information detected by the phase detector 131 based on these signals is output. The spread code of each phase E, P, L is generated by the PNG 134 based on the signal supplied to the NCO 133 via the loop filter 132 and having the predetermined frequency generated by the NCO 133.

As described above, the Costas loops 101 and D
In the channel circuit 91 having the LL 102, the correlation adders 112, 113, 121, 122, 128, 1
Since the sum of squares of the absolute value addition values of the correlation values of the two signals is used as the correlation value for each of 29, the integration time length can be lengthened, so that the S / N can be improved and the reception sensitivity can be improved. Can be improved. Also,
In the channel circuit 91, the LPFs 107, 10
It is also possible to reduce the bandwidth of 8, 119, 120, 126, 127 and remove noise before addition. Correlation adders 112, 113, 121, 122, 128, 12
When there is no noise, the output from each of 9 is constant regardless of the position where the data is inverted.

In the channel circuit 91, Japanese Patent Application No. 2001-19065 previously filed by the applicant of the present application.
As described in No. 8, the integration time may be a predetermined length that is 1 bit or less of the data. Also, the channel circuit 9
1, the correlation adders 112, 113, 121, 1
For example, the absolute value addition value of the correlation value may be calculated in each of 22, 128, and 129 in a 1-bit length cycle of the data, and the output may be updated in each cycle. In that case, the phase control of the DLL 102 is performed in a 1-bit length cycle of data.

In the channel circuit 91 shown in FIG. 8 including the demodulator formed by the conventional Costas loop and DLL, the sum of squares of the output on the in-phase component side and the output on the quadrature component side is a correlation value. However, when the synchronization is maintained, the output on the quadrature component side is almost noise. Therefore, Costas Loop and DLL
In S, in the synchronous holding state, using only the output on the in-phase component side is not affected by the noise on the output on the quadrature component side, so that the S / N is improved. Further, in the Costas loop and the DLL, when the frequency shift is small but carrier synchronization is not yet achieved, that is, when there is no phase, the absolute value of the output on the in-phase component side and the output on the quadrature component side is absolute. For the larger value, the square of the absolute value is the smallest (phase error is 45 ° compared to the sum of squares.
However, the noise of both the output on the in-phase component side and the output on the quadrature component side is not added and only one side is required. Are the same.

Therefore, in the GPS receiver 10, not the sum of squares of the output on the in-phase component side and the output on the quadrature component side, but the absolute value of the output on the in-phase component side and the output on the quadrature component side as the correlation value. Synchronization determination and DLL phase control are performed. Specifically, in the GPS receiver 10, the channel circuits _{91 1,} 91 2,..., As 91 _N, used channel circuit 91 'shown in FIG. 10.

That is, as shown in the figure, the channel circuit 91 'includes the Costas loop 1 for IF carrier synchronization.
The maximum value selection circuit that outputs the larger value (Max (I, Q)) by comparing the outputs from the correlation adders 112 and 113 in place of the above-described square sum calculation circuit 114 to the circuit including 01. 141 is provided. Also, the channel circuit 91 '
Is a DLL 102 ′ for spreading code synchronization, instead of the above-described square sum calculation circuit 123, correlation adders 121 and 122.
Selector 14 for selecting one of the outputs from
2 is provided, and in place of the above-described square sum calculation circuit 130, a selector 143 that selects one of the outputs from the correlation adders 128 and 129 is provided. Here, when the output from the correlation adder 112 on the in-phase component side is selected by the maximum value selection circuit 141, the selectors 142 and 143 output the outputs from the correlation adders 121 and 128 on the in-phase component side, respectively. Select and maximum value selection circuit 1
When the output from the orthogonal component side correlation adder 113 is selected by 41, the orthogonal component side correlation adder 12
Select the output from 2,129.

As described above, in the channel circuit 91 ', instead of the sum of squares of the output on the in-phase component side and the output on the quadrature component side, a circuit for comparing the magnitude of the two values is used to determine the output on the in-phase component side. Even if synchronization determination and DLL phase control are performed using the absolute value of the output on the quadrature component side as a correlation value, the S / N does not deteriorate. In the channel circuit 91 ', the processing load is also reduced by using the absolute value of the output on the in-phase component side or the output on the quadrature component side as the correlation value.

In the GPS receiver 10, instead of the channel circuit 91 ', as shown in FIG. 11, both of the spread codes having the phases E and L have a large scale in terms of hardware, that is, the LPF and the correlation addition. DLL with a single container
It may be a channel circuit 91 ″ having 102 ″.

That is, in the channel circuit 91 ″, the multipliers 117 and 118 described above are used as one multiplier 151 and the LPFs 119 and 120 described above are used as one LPF 152 as the configuration on the side of the spreading code having the phase E. The above correlation adders 121 and 122 are combined into one correlation adder 15
Set to 3. In the channel circuit 91 ″, the multiplier 12 described above is used as the configuration on the spreading code side having the phase of L.
4,125 as one multiplier 154, and the above-mentioned LPF
126 and 127 are one LPF 155, and the above-described correlation adders 128 and 129 are one correlation adder 156. Further, the channel circuit 91 ″ is provided with a selector 157 for selecting either one of the sine component and the cosine component in the reproduced carrier generated by the NCO 104 in the Costas loop 101.

In such a channel circuit 91 '', when the output from the correlation adder 112 on the in-phase component side is selected by the maximum value selection circuit 141, the NCO1
The sine component of the reproduced carrier generated by 04 is selected by the selector 157, and this signal is supplied to the multipliers 151 and 152 as a carrier. on the other hand,
In the channel circuit 91 ″, the maximum value selection circuit 14
When the output from the correlation adder 113 on the quadrature component side is selected by 1, the cosine component of the reproduced carrier generated by the NCO 104 is selected by the selector 157, and this signal is used as the carrier by the multiplier 15
1,152.

As described above, the channel circuit 91 ″ can reduce two LPFs and two correlation adders each, compared to the channel circuit 91 ′. When applied to the synchronization holding unit 25, it is very effective in reducing the circuit scale.

Further, in the GPS receiver 10, the channel circuit 91 ″ is improved so that, as shown in FIG. 12, based on the gate signal generated by the gate signal generator 168, the spread code having the phases E and L. Slower than
In addition, the DLL 102 ″ ′ adopts the Taudizer method for obtaining the difference between the correlation value (E) and the correlation value (L) by switching the multiplier input of the spreading code at a frequency sufficiently higher than the band of the LPF. The channel circuit 91 ″ ′ can also be used.

That is, the channel circuit 91 '''generates a gate signal which repeats high and low at a constant cycle by the gate signal generator 168. As for the frequency of this gate signal, for example, the cutoff frequency of the LPF 165 is 1 k.
In the case of Hz, it is set to several tens of kHz. In the channel circuit 91 ″ ′, when the gate signal generated by the gate signal generator 168 is high, the selector 1
When the spread code having the phase E is selected by 61 and the gate signal is low, the selector 161 changes the phase to L.
Spreading code is selected. And the channel circuit 9
In 1 ″ ′, the spread code selected by the selector 161 is multiplied by the input IF signal by the multiplier 162, and the carrier is multiplied by this signal by the multiplier 1.
Multiplied by 64. In addition, the channel circuit 9
In 1 ″ ′, when the maximum value selection circuit 141 selects the output from the correlation adder 112 on the in-phase component side, the sine component of the reproduced carrier generated by the NCO 104 is selected by the selector 163. ,
This signal is supplied to the multiplier 164 as a carrier.
On the other hand, in the channel circuit 91 ′ ″, when the output from the correlation adder 113 on the orthogonal component side is selected by the maximum value selection circuit 141, the cosine component of the reproduction carrier generated by the NCO 104 is selected. This signal is selected by 163 and supplied to the multiplier 164 as a carrier.

Then, in the channel circuit 91 ''', the signal obtained by the multiplier 164 is the LPF 165.
Is supplied to the correlation adder 166 via the correlation adder 166, the absolute value addition value of the correlation value is calculated by the correlation adder 166, and the calculation result is supplied to the multiplier 167. Channel circuit 9
In 1 ″ ′, the output from the correlation adder 166 and the gate signal from the gate signal generator 168 are the multiplier 167.
And the obtained result is multiplied by the loop filter 13
2 is supplied. At this time, in the channel circuit 91 ′ ″, when the multiplication by the multiplier 167 is performed, “1” is set when the gate signal from the gate signal generator 168 is high.
When it is low, the operation is performed as "0".

In such a channel circuit 91 ''', since the LPF and the correlation adder for the spread codes having the phases E and L are made common, the channel circuit 9'''
It is possible to further reduce the circuit scale as compared with 1 ''. However, in the channel circuit 91 ′ ″, by adopting the taud dither method, the channel circuit 91 ″
As compared with the above, the S / N is deteriorated by about 3 dB.
The channel circuit 91 ′ ″ outputs the difference between the correlation value (E) and the correlation value (L), but since this difference can be used for phase control as the phase comparison result, the channel The phase detector provided in the circuits 91, 91 ', 91''is unnecessary.

Hereinafter, the above-mentioned channel circuits 91 and 9 will be described.
The features of the LPF, the phase detector, the loop filter, and the correlation adder in 1 ′, 91 ″, and 91 ′ ″ will be described.

First, the LPF will be described.

The above-mentioned channel circuits 91, 91 ', 9
The LPF in 1 ″ and 91 ″ ′ is to remove unnecessary data other than the data band after multiplying the input signal by the spread code and the reproduction carrier. In the GPS receiver 10, there are both cases where it is desired to narrow the LPF band as much as possible to increase the S / N ratio, and where it is desired to prioritize the response speed even if the sensitivity deteriorates a little. The width is preferably variable.

Therefore, in the GPS receiver 10, an LPF is constructed as shown in FIG. 13 in order to make the bandwidth variable. Although the input signal is 1 bit in the figure, it may be multi-bit. G
In the PS receiver 10, since the received signal is at a level much lower than the thermal noise, even if the analog / digital conversion is performed by binarization, the S / N deterioration is slight.

The LPF shown in (A) of the figure is an infinite impulse response (IIR) filter which is a differential approximation of the transfer function of the RC filter shown in (B) of the figure. This LPF is composed of a multiplier 171 that multiplies an input signal X [n] consisting of 1 bit or multiple bits by a power of 2 and a signal Y [n-1] and 2 supplied from a register 175 described later. A multiplier 172 that multiplies a power k and a signal Y [n− supplied from the register 175.
1] and the signal kY [n− obtained by the multiplier 172.
1], and an adder for adding the signal kX [n] obtained by the multiplier 171 and the signal (1-k) Y [n-1] obtained by the difference 173. 174 and a register 175 that holds the signal represented by the differential approximation formula of the RC filter obtained by the adder 174 for a predetermined bit length. The input signal X
"N" in [n] and the output signal Y [n] represents discrete time.

In such an LPF, the input signal X
The relationship between [n] and the multi-bit output signal Y [n] is Y [n] = (1-k) Y [n-1] + kX [n], and the signal output from the adder 174 is This relationship will be satisfied. In this LPF, when the sampling frequency is _{f s,} the time constant _{t c,} the cutoff frequency _{f c, respectively, t c = RC = 1 /} (kf s), f c = 1 / (2πRC) = kf s / (2π), k = 1 / (RCf _s ). Therefore, in the LPF, k = 2 ⁻¹⁶
And the sampling frequency is f _s = 18.414 MHz
Then, the time constant t _c is 3.56 milliseconds, and the cutoff frequency f _c is 44.7 Hz.

In such an LPF, the input signal X
[N] is 1 bit or multi-bit, and the value is "1" or "
-1 ", but the input signal X [n] and the output signal Y
In [n], the register 175 is set to have an M bit length, and "
If 1 "is regarded as" 100 ... 0 "," -1 "is regarded as" 000 ... 0 ", and k is 2- ^L (L is an integer), kX [n]
The multiplier 171 for performing the operation of can be realized by a barrel shifter for performing a left shift of (ML) bits,
The multiplier 172 that calculates kY [n] can be realized by a barrel shifter that shifts right by L bits. For example, the register 175 has a length of 22 bits, and k =
^2-16 , the multiplier 171 can be realized by a barrel shifter that performs a 6-bit left shift, and the multiplier 172 can be realized by a barrel shifter that performs a 16-bit right shift. Therefore, LPF
In the above, in the case where L can be set from the outside, the cutoff frequency f _c can be made variable in octave units. In addition, in the LPF, "0" is changed to "010.
.. can be determined as 0 ", and the sign of the output signal Y [n] can be determined by comparing with this value.
In the PF, by inverting and outputting the most significant bit of the remaining bit string excluding the most significant bit of the bit string held in the register 175, the value of the output signal Y [n] becomes a two's complement.

Next, the phase detector will be described.

Channel circuits 91, 91 ', 91'', 9
1 ″ ′ is provided with a phase detector 110 in the Costas loop 101, and the input to the phase detector 110 is, for example, the upper 10 bits of the signal from the LPF if the required dynamic range is 10 bits. . Here, the most general phase comparison result output which is the output from the phase detector 110 in the Costas loop is a value I × obtained by multiplying the output on the in-phase component side and the output on the quadrature component side.
Q, but this value depends on the signal strength,
Since it is not preferable, there is a modified Costas loop that sets the phase comparison result output to the value Q / I obtained by dividing the output on the quadrature component side and the output on the in-phase component side. This value Q / I is the NCO
The tangent of the phase difference between the reproduced carrier generated by 104 and the carrier included in the input signal.

Since the calculation of this value Q / I includes division, hardware processing is difficult and is generally calculated by a CPU. However, the processing in the Costas loop of a plurality of channels is performed by one CPU. If done by, the load is heavy.

Therefore, in the GPS receiver 10, when the modified Costas loop is applied to calculate the value Q / I, the calculation is approximated as follows to facilitate hardware configuration. .

First, in the GPS receiver 10, the output I on the in-phase component side and the output Q on the quadrature component side are respectively
Two's complement is used, positive and negative are discriminated from the most significant bits of both, and the absolute value is detected from other bits. continue,
The GPS receiver 10 checks the most significant bit position S, which is "1" in absolute value. For example, G
In the PS receiver 10, the output I on the in-phase component side is "0".
In the case of "001011001", since the 7th bit from the least significant bit is the most significant bit with an absolute value of "1", the position of the least significant bit is set to "0" and S = 6.
And Then, in the GPS receiver 10, the result of right-shifting the absolute value of the output Q on the quadrature component side by S bits is taken into consideration in consideration of the sign relation between the output I on the in-phase component side and the output Q on the quadrature component side. Is converted into the complement of and this value is used as the phase comparison result output.

As described above, in the GPS receiver 10, since the output I on the in-phase component side can be approximated by 2 ^S and the Q / I calculation can be replaced with the shift calculation, the hardware configuration can be easily performed. It becomes feasible. The absolute error between the exact Q / I and the approximate Q / I is Q / I =
Since the Costas loop that becomes 0 is small in the vicinity of the phase lock, this method can sufficiently reduce the phase error at the time of synchronization, although it is an approximation.

However, when the phase error is close to 90 °, the value of the output Q on the quadrature component side increases and the value of the output I on the in-phase component side decreases, so the value Q / I becomes a large value. However, it is not preferable as a phase detector. Therefore,
In the GPS receiver 10, when the result obtained by right-shifting the absolute value of the output Q on the quadrature component side by S bits is larger than a predetermined value, for example, "2", the absolute value of the phase comparison result output is set to "2". Set the limiter to ". In the GPS receiver 10, when the limiter set value is "1", it is within ± 45 ° within a range of ± 90 °, and when the limiter set value is "2", within a range of ± 90 °. , The phase comparison characteristic has a slope within ± 63.4 °.
The phase comparison characteristic when the limiter setting value is "2" is as shown in FIG. In the figure, the horizontal axis represents the angle and the vertical axis represents the phase comparison result output. G
In the PS receiver 10, when the reproduced carrier by the NCO 104 and the carrier included in the received signal are synchronized, the phase comparison result output has a value near the equilibrium point shown by the black circle in the figure.

On the other hand, the channel circuits 91, 91 ', 9
1 ″ is provided with a phase detector 131 in each of the DLLs 102, 102 ′, and 102 ″. The input to the phase detector 131 is, for example, a signal from the LPF if the required dynamic range is 10 bits. Upper 10 bits of Here, the most general phase comparison result outputs that are outputs from the phase detector 131 in the DLL are an output for a spreading code having a phase of E and an output for a spreading code having a phase of L. Difference value E
Although it is −L, this value depends on the signal strength and is not preferable. Therefore, the phase comparison result output is (E
-L) / (E + L) is preferable.

In the GPS receiver 10, this value (E
The phase detector 131 that performs the calculation of −L) / (E + L) also
It can be configured similarly to the phase detector 110 that performs the Q / I calculation in the Costas loop described above. GPS
In the receiver 10, when the calculation of the value (E−L) / (E + L) is performed, the calculation can be approximated as follows to facilitate hardware configuration.

First, in the GPS receiver 10, (E
The calculation of −L) and the calculation of (E + L) are performed. Then, G
In the PS receiver 10, the most significant bit position S with "1" in the value (E + L) is checked. For example, in the GPS receiver 10, the value (E + L) is "0.
In the case of "001011001", since the 7th bit from the least significant bit is the most significant bit with "1", the position of the least significant bit is set to "0" and S = 6.
Then, in the GPS receiver 10, when the value (EL) is a negative value, the result of right-shifting the value (EL) by S bits is sign-extended and converted into a two's complement, This value is used as the phase comparison result output.

As described above, in the GPS receiver 10, the value (E + L) is approximated by 2 ^S , and (E−L) / (E +)
Since the calculation of L) can be replaced with the shift calculation, the hardware configuration can be easily realized.
It should be noted that accurate (E−L) / (E + L) and approximation (E
-L) / (E + L) has an absolute error of (E-L) / (E
Since the DLL for which + L) = 0 is small in the vicinity of the phase lock, this method can approximate the phase error at the time of synchronization, although it is an approximation. The spreading code whose phase is P and the spreading code whose phase is E and whose phase is L
The phase comparison characteristics when the shift amount of the spread code is ± 0.5 chips are as shown in FIG.
In the same figure, the horizontal axis shows the phase difference of the spreading code whose unit is a chip, and the vertical axis shows the phase comparison result output.
In the GPS receiver 10, when the reproduction code by the PNG 134 and the spreading code included in the received signal are synchronized, the phase comparison result output has a value near the equilibrium point indicated by the black circle in the figure.

Next, the loop filter will be described.

Channel circuits 91, 91 ', 91'', 9
1 ″ ″, the loop filter 109 in the Costas loop 101 and the DLLs 102, 102 ′, 10
The loop filter 132 in 2 ″ and 102 ″ ′ integrates the phase error output by the phase detector and controls the phase of the NCO by its output. GPS receiver 10
In (1), the phase comparison is realized by a perfect integration type loop filter which becomes an optimum filter when there is a frequency offset or a random phase offset.

The perfect integral loop loop shown in FIG.
The equivalent circuit of the filter is shown in FIG. This loop figure
The transfer function F (s) in F (s) = (1-sτ_Two) / (Sτ₁), Τ₁= R
₁C, τ_Two= R_TwoC Is. When this is subjected to difference approximation, it is output as the input signal X [n].
The relationship with the force signal Y [n] is Y [n] = Y [n-1] + a (X [n] -X [n-
1]) + bX [n], a = τ_Two/ Τ₁, B = T / τ₁ Becomes Where T is the sampling period and
Ring frequency is more than cutoff frequency of LPF
Make it higher From the above formula, the parameters set by the loop filter
There are two data, a and b. These parameters a,
b is a = 2^A, B = 2^B(A and B are integers)
Then, aX [n], aX [n-1] in the above equation,
bX [n] is left by A bit or B bit, respectively.
It can be calculated by shifting and is shown in the above equation.
The calculation is performed by the loop filter shown in FIG.
You can

Therefore, in the loop filter,
When the values of A and B can be set from the outside, the bandwidth and response speed of the loop filter can be made variable according to the reception status.

In the GPS receiver 10, the frequency of the NCO is controlled by the output from the loop filter, and when the phase error is positive, that is, when the phase is advanced, the frequency is lowered to delay the phase and vice versa. If, then the frequency is increased and the phase is advanced. In the GPS receiver 10, in order to increase resistance to acceleration, A, B
If the value of is set to a large value and the response speed of the channel circuit is increased, the received signal becomes weak at a certain moment and the error in the phase comparison result output becomes large, the control amount for the NCO of the loop filter becomes too large, There are cases where synchronization is lost.

Therefore, in the GPS receiver 10, in order to avoid such out-of-synchronization, it is possible to set the upper limit value and the lower limit value of the change of the output value from the loop filter with respect to the previous output value, and Change a (X [n] -X
When [n-1]) + bX [n] exceeds the set upper limit value or lower limit value, the loop filter outputs the upper limit value or the lower limit value. In the GPS receiver 10, the upper limit value and the lower limit value, the DLL, the fluctuation range of the chip rate of the spreading code determined by the Doppler shift amount and the accuracy of the TCXO 12, and the Costas loop, the NCO control time at maximum acceleration. It is determined based on the amount of change in the carrier frequency within the cycle.

In the GPS receiver 10, by setting such a limiter, the response speed is fast within the range where there is a phase error or phase change, but the phase changes abruptly in response to fluctuations beyond the prediction. Control can be returned to normal when the received signal is recovered.

Next, the correlation adder will be described.

In the GPS receiver 10, when the request for sensitivity is stronger than the response speed, the correlation adders 112, 113, 121, 122, 128, 12 described above are used.
9 and 166 each have a data 1-bit length of 20
If the output is performed every millisecond, the correlation detection time becomes longer and the S / N is improved by continuously adding the outputs a plurality of times.

[0154] Therefore, in the GPS receiver 10, the channel circuits _{91 1,} 91 2,..., As 91 _N,
The channel circuit 91 ″ ″ shown in FIG. 18 is used.

That is, the channel circuit 91 '''' is an improved version of the channel circuit 91 'shown in FIG. 10, and as shown in the figure, a circuit including the Costas loop 101 for IF carrier synchronization. In the subsequent stage of the above-described maximum value selection circuit 141 in, the multiple-time adder 181 is provided. In addition, the channel circuit 91 '''' is a DL for spreading code synchronization.
A multiple-time adder 182 is provided in the latter stage of the selector 142 in the L 102 ″ ″, and a multiple-time adder 183 is provided in the subsequent stage of the selector 143.

As described above, in the channel circuit 91 ″ ″, the multiple-time adder 181, which continuously adds the output value from the correlation adder having the data length of 1 bit or less a plurality of times,
182 and 183 are provided, and the value after adding a plurality of times
By outputting as the correlation value for the P and L spreading codes, the correlation detection time can be lengthened, and the phase detector 131 and the loop can be used as the correlation values for the spreading codes whose phases are E and L after addition is performed a plurality of times. NCP through filter 132
By controlling 133, S / N can be improved. In the GPS receiver 10, the number of times of addition in the multiple-time adders 181, 182, 183 can be set externally. For example, GPS receiver 1
At 0, when the number of additions is set to 4, a sensitivity improvement of about 6 dB can be expected as compared with the case without addition.

In the GPS receiver 10, the control time interval of the DLL 102 ″ ″ is lengthened by performing addition a plurality of times. For example, in the GPS receiver 10, the control is performed every 20 milliseconds when there is no addition, whereas the control is performed every 80 milliseconds when the addition is performed four times. . Therefore, the GPS receiver 10
In the above, although S / N can be improved by performing addition a plurality of times, DLL1 due to time delay
Since the response deterioration of 02 ″ ″ occurs, in order to avoid this, for example, the values of the past five times may be added multiple times and output every 20 milliseconds. Further, in the GPS receiver 10, it is possible to perform a moving average instead of performing addition a plurality of times.

Here, regarding the reception status, especially when the GPS receiver is applied to a moving body, the signal strength and the carrier frequency are apt to change according to the surrounding environment, and the external noise is generated even in the stationary state. The S / N changes with time due to the influence of. Therefore, in the GPS receiver, if the setting of the channel circuit remains fixed, it is not possible to cope with the change in the reception status, and it becomes impossible to maintain the synchronization.

On the other hand, in the GPS receiver 10, the cutoff frequency of the LPF in the channel circuit, the coefficient and limiter range of the loop filter in the Costas loop and DLL, and the number of additions by the multiple adder are set from the outside. It is possible. Therefore,
In the GPS receiver 10, the CPU 26 that controls the entire GPS receiver 10 constantly detects changes in the carrier frequency due to signal strength and acceleration in all channel circuits, and dynamically sets the settings for each channel according to the reception status. By changing it, it is possible to respond appropriately to changes in the reception status.

In general, in the GPS receiver, in order to improve the reception sensitivity, the correlation detection time length is increased to
It is necessary to make the bandwidth of the PF as narrow as possible so as to slow down the response of the Costas loop and the DLL to noise, while in order to improve the tolerance to acceleration,
On the contrary, Costas loop and DL for noise
Since it is necessary to speed up the response of L, the reception sensitivity and the resistance to acceleration are essentially incompatible with each other.

However, when the received signal is weak and the S / N is low with respect to the frequency change when the acceleration is large, it is not possible to follow the response of the Costas loop and the DLL. In the machine 10, the CPU 26 constantly detects the signal strength in the correlation adder or the multiple-time adder, and when the signal strength is large, the cutoff frequency of the LPF is increased and the loop bandwidth of the loop filter is widened. The coefficient is set so that the response of Costas loop and DLL becomes faster, while when the signal strength is small, the cutoff frequency of the LPF is lowered and the coefficient is set so that the loop bandwidth of the loop filter is narrowed. Then Costas Loop and DLL
The priority can be changed according to the magnitude of the signal strength by setting the response of 1 to have strong noise resistance.

At this time, in the GPS receiver 10,
Although various thresholds may be set and various settings may be changed according to the determination of only the magnitude of the signal strength, it is possible to hold a stepwise combination of the signal strength and various set values in advance as a table, For the signal strength that changes every moment, C
The PU 26 allows more flexible handling.

As described above, the GPS receiver 10
Is used for correlation detection and DL according to the output value from the correlation adder.
By performing the phase control of L, the time length of the correlation detection can be lengthened, the band of the LPF can be narrowed, and the resistance to noise can be improved according to the characteristics of the phase detector and the loop filter. Can be made. Therefore, the GPS receiver 10 can improve the reception sensitivity as compared with the general Costas loop and DLL.

Further, the GPS receiver 10 can improve S / N by correlating and adding only one of the output on the in-phase component side and the output on the quadrature component side,
Moreover, the number of LPFs and correlation adders can be reduced, and the circuit scale can be significantly reduced.

Further, although the GPS receiver 10 adopts the Taudizer system, the S / N is deteriorated,
Furthermore, the number of correlation adders can be reduced.

Furthermore, the GPS receiver 10 is an LPF.
By dynamically changing the bandwidth, the loop bandwidth of the loop filter, and the correlation addition time, it is possible to control the reception sensitivity and the response speed according to the reception situation. Then, the GPS receiver 10 can improve the balance between the reception sensitivity and the resistance to acceleration by dynamically changing the setting according to the signal strength.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the channel circuit in the GPS receiver 10 has been described, but the present invention can be applied to any demodulator that demodulates a spread spectrum signal.

Further, in the above-mentioned embodiment, the matched filter 50 shown in FIG.
Although it has been described that the digital matched filter 60 shown in FIG. 3 is used, the present invention is not limited to this.
Any operation can be applied as long as it can perform an operation equivalent to the synchronization acquisition operation by 4.

Further, in the above-mentioned embodiment, the GPS
Although the receiver 10 is used for the description, the present invention can be applied to any receiver that uses a positioning system using satellites, that is, a GNSS system. As the GNSS system, in addition to the above-mentioned GPS system in the United States, GL in the former Soviet Union
ONASS (Global Navigation Satellites System)
And GALIL being developed mainly in Europe
Although there are EO, etc., the present invention can apply all of these GNSS systems.

As described above, it goes without saying that the present invention can be appropriately modified without departing from the spirit thereof.

[0171]

As described above in detail, the demodulation device according to the present invention is a demodulation device for demodulating a spread spectrum signal, and synchronizes the reproduced carrier with the carrier included in the input spread spectrum signal. The first loop circuit for establishing and the second loop circuit for establishing synchronization between the reproduction code and the spread code included in the input spread spectrum signal are provided, and the first loop circuit and the second loop circuit are , A filter means for passing a predetermined frequency band component of a multiplication value of a carrier, a spread code, and an input spread spectrum signal, and a unit of a data 1 bit length or a predetermined length of 1 bit or less The first correlation value obtained by integrating the signal that has passed through the means, and the unit of the input spread spectrum signal of the signals that have passed through the filter means. A correlation adding means for adding a second correlation value obtained by integrating a signal obtained by inverting the length division portion, and detecting the correlation and controlling the phase of the second loop circuit based on the output value from the correlation adding means. I do.

Therefore, the demodulator according to the present invention is
A first correlation value obtained by integrating a signal that has passed through the filter means, and a second correlation value obtained by integrating a signal obtained by inverting a half length unit of the input spread spectrum signal of the signal that has passed through the filter means. Are added by the correlation adding means, and the correlation detection and the second detection are performed based on the obtained output value.
By performing the phase control of the loop circuit, the reception sensitivity and the acceleration resistance can both be improved.

The receiving device according to the present invention is a receiving device for receiving a signal from a satellite to calculate its own position and velocity, and a receiving means for receiving a signal from the satellite,
Frequency converting means for converting the frequency of the received signal received by the receiving means into a predetermined intermediate frequency, synchronous acquisition for detecting the phase of the spread code in the intermediate frequency signal obtained by the frequency converting means, and carrier in the intermediate frequency signal A synchronization acquisition means for detecting the frequency, a phase of the spread code detected by the synchronization acquisition means, and a carrier frequency detected by the synchronization acquisition means are provided in a plurality of channels independently corresponding to a plurality of satellites. Each satellite is assigned to each satellite and set, and the spread code and carrier are held in synchronism with the set spread code phase and carrier frequency as initial values, and the message included in the intermediate frequency signal is demodulated. And a plurality of synchronization holding means for demodulating a spread spectrum signal. Each channel establishes synchronization between the reproduction code and the spread code included in the input spread spectrum signal and the first loop circuit that establishes synchronization between the reproduction carrier and the carrier included in the input spread spectrum signal. And a second loop circuit for transmitting a predetermined frequency band component of the multiplication value of the carrier, the spread code, and the input spread spectrum signal, respectively. A filtering unit, a first correlation value obtained by integrating a signal that has passed through the filtering unit in units of a data 1-bit length or a predetermined length that is less than or equal to the data 1-bit length, and an input spectrum of the signals that have passed through the filtering unit. A plurality of correlation adding means for adding a second correlation value obtained by integrating a signal obtained by inverting a half length unit of the spread signal; Yan'neru, respectively, controls the phase of the correlation detection and the second loop circuit based on the output value from the correlation adding means.

Therefore, the receiving apparatus according to the present invention is
A first correlation value obtained by integrating a signal that has passed through the filter means, and a second correlation value obtained by integrating a signal obtained by inverting a half length unit of the input spread spectrum signal of the signal that has passed through the filter means. Are added by the correlation adding means, and the correlation detection and the second detection are performed based on the obtained output value.
By synchronizing the spread code and the carrier while controlling the phase of the loop circuit of, the synchronization of the spread code and the carrier in the signal from the satellite can be achieved while improving both the reception sensitivity and the acceleration resistance. Capturing and synchronization holding can be easily performed.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a GPS receiver shown as an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a matched filter including a transversal filter that can be applied as a synchronization acquisition unit included in the GPS receiver.

FIG. 3 is a block diagram illustrating a configuration of a digital matched filter using an FFT that can be applied as a synchronization acquisition unit included in the GPS receiver.

FIG. 4 shows a synchronization acquisition unit included in the GPS receiver shown in FIG.
FIG. 11 is a block diagram illustrating an actual implementation example when the digital matched filter shown in FIG.

FIG. 5 is a block diagram illustrating a configuration of a synchronization holding unit included in the GPS receiver.

FIG. 6 is a diagram for explaining phase alignment of spreading codes in a synchronization holding unit included in the GPS receiver.

FIG. 7 is a diagram for explaining phase correction of a spread code in a synchronization holding unit included in the GPS receiver.

FIG. 8 is a block diagram illustrating a configuration of a channel circuit included in a synchronization holding unit included in the GPS receiver, which is a block diagram illustrating a configuration of a channel circuit provided with a correlation adder.

FIG. 9 is a diagram illustrating a process in a correlation adder.

FIG. 10 is a block diagram illustrating a configuration of another channel circuit included in the synchronization holding unit included in the GPS receiver, which is a block diagram illustrating a configuration of a channel circuit that compares the magnitudes of outputs from the correlation adder. Is.

FIG. 11 is a block diagram illustrating the configuration of still another channel circuit included in the synchronization holding unit included in the GPS receiver, and is a DL in which an LPF and a correlation adder are combined into one.
It is a block diagram explaining the structure of the channel circuit which has L.

FIG. 12 is a block diagram illustrating a configuration of still another channel circuit included in the synchronization holding unit included in the GPS receiver, which is a block diagram illustrating a configuration of a channel circuit adopting a taud dither system.

FIG. 13 is a diagram illustrating a configuration of an LPF, (A)
[Fig. 3] is a diagram showing a configuration of an IIR filter, and (B) is a diagram showing a configuration of an RC filter.

FIG. 14 is a diagram illustrating a phase comparison characteristic in a Costas loop.

FIG. 15 is a diagram illustrating phase comparison characteristics in DLL.

16A and 16B are diagrams illustrating a configuration of an equivalent circuit of a perfect integration type loop filter, in which FIG. 16A shows a configuration of the loop filter, and FIG. 16B shows an equivalent circuit of the loop filter shown in FIG. It is a figure which shows the structure of.

FIG. 17 is a diagram illustrating a configuration of a perfect integration type loop filter.

FIG. 18 is a block diagram illustrating a configuration of still another channel circuit included in the synchronization holding unit included in the GPS receiver, which is a block diagram illustrating a configuration of a channel circuit in which a correlation detection time is lengthened.

FIG. 19 is a diagram illustrating a configuration of a signal from a GPS satellite.

FIG. 20 is a diagram for explaining a conventional spreading code and carrier synchronization process, and is a diagram for explaining a frequency search.

FIG. 21 is a block diagram illustrating a configuration of a general Costas loop and DLL applied to a spread spectrum signal demodulator.

FIG. 22 is a diagram illustrating spreading codes of three phases generated by a spreading code generator.

FIG. 23 is a diagram illustrating an example of an output waveform showing a temporal change in a correlation value detected using a digital matched filter.

[Explanation of symbols]

10 GPS receiver, 11 XO, 12 TCX
O, 13 multiplier / divider, 14 antenna, 15
LNA, 16 BPF, 17, 20 amplifier,
18 frequency synthesizer, 19 mixer, 21,
107, 108, 119, 120, 126, 127, 1
52,155,165 LPF, 22A / D, 23
Frequency conversion unit, 24 synchronization acquisition unit, 25 synchronization holding unit, 26 CPU, 27 RTC, 28 timer, 29, 62, 64, 67 memory, 30 demodulation circuit, 50 matched filter, 60 digital matched filter, 61, 81 sampler, 63,6
6 FFT processing unit, 65,134 spreading code generator,
68, 103, 105, 106, 115, 116, 1
17,118,124,125,151,154,16
2,164,167,171,172 multiplier, 69
IFFT processing unit, 70 peak detector, 82 R
AM, 83 RAM / ROM, 84 DSP, 9
_{1,91 1, 91 2, ···,} 91 N, 91 ', 9
1 ", 91"', 91 "" channel circuit, 92
Control register, 101 Costas loop,
102, 102 ', 102 ", 102'", 102 ""
DLL, 104,133 NCO, 109,13
2 loop filter, 110, 131 phase detector,
111 binarization circuit, 112, 113, 121, 1
22, 128, 129, 153, 156, 166 Correlation adder, 114, 123, 130 Sum of squares calculation circuit,
141 maximum value selection circuit, 142, 143, 15
7, 161, 163 selector, 168 gate signal generator, 173 differencer, 174 adder, 175
Register, 181, 182, 183 Multi-time adder

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masayuki Takada             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F-term (reference) 5K022 EE02 EE33 EE36                 5K047 AA05 BB01 GG09 GG11 GG34                       HH01 HH12 HH15 MM12 MM29                       MM33 MM38 MM40 MM55

Claims (22)

[Claims] 1. A demodulator for demodulating a spread spectrum signal, comprising: a first loop circuit for establishing synchronization between a reproduced carrier and a carrier included in the inputted spread spectrum signal; A second loop circuit for establishing synchronization with a spread code included in the spread spectrum signal, wherein the first loop circuit and the second loop circuit respectively receive the carrier and the spread code. A filter means for passing a predetermined frequency band component of the multiplication value with the spread spectrum signal, and a first one obtained by integrating the signal passed through the filter means in units of a data 1 bit length or a predetermined length equal to or less than the data 1 bit length. The correlation value of and the half length part of the unit in the input spread spectrum signal of the signal that has passed through the filter means. A correlation adding means for adding a second correlation value obtained by integrating the inverted signal, and performing the correlation detection and the phase control of the second loop circuit based on the output value from the correlation adding means. Characteristic demodulator. 2. The first loop circuit and the second loop circuit respectively calculate the sum of squares of the output value on the in-phase component side and the output value on the quadrature component side output from the correlation adding means. The demodulator according to claim 1, further comprising a sum of squares calculating means for outputting as a correlation value of the spread code. 3. The first loop circuit compares the output value on the in-phase component side and the output value on the quadrature component side output from the correlation adding means for the spreading code of the first phase. The second loop circuit has maximum value selecting means for outputting the one having a larger value, and the second loop circuit outputs from the correlation adding means for the spread code having the second phase advanced from the first phase. In addition to selecting one of the output value on the in-phase component side and the output value on the quadrature component side, the correlation addition is performed for each of the spread codes that are delayed from the first phase and are the third phase. The selecting means has a selecting means for selecting one of the output value on the in-phase component side and the output value on the quadrature component side output from the means, and the selecting means has a function for the spreading code to be the first phase. The same output from the correlation adding means When the output value on the component side is selected by the maximum value selecting means, the output value on the in-phase component side output from the correlation adding means for the spreading code to be the second phase, and the third value. While selecting the output value of the in-phase component side output from the correlation adding means for the spreading code to be the phase, the quadrature component output from the correlation adding means for the spreading code to be the first phase. When the output value on the side is selected by the maximum value selecting means, the output value on the quadrature component side output from the correlation adding means for the spreading code of the second phase, and the third value. 2. The demodulator according to claim 1, wherein an output value on the orthogonal component side output from the correlation adding means for the spread code used as the phase is selected. 4. The first loop circuit compares the output value on the in-phase component side and the output value on the quadrature component side output from the correlation adding means for the spreading code of the first phase. The second loop circuit has maximum value selecting means for outputting the larger value, and when the output value on the in-phase component side outputted from the correlation adding means is selected by the maximum value selecting means, , While selecting the carrier of the in-phase component among the carriers in the first loop circuit, while the output value on the quadrature component side output from the correlation adding means is selected by the maximum value selecting means, Selecting means for selecting a carrier having an orthogonal component among the carriers in the first loop circuit; and a spreading code for setting the carrier selected by the selecting means as a second phase advanced from the first phase. 2. The demodulator according to claim 1, further comprising: a multiplying unit that multiplies each of the spread code that is delayed from the first phase and the third phase that is delayed from the first phase. 5. The second loop circuit has gate signal generating means for generating a predetermined gate signal, and is set to the second phase based on the gate signal generated by the gate signal generating means. The dither method is used to switch the input of the spread code multiplier at a frequency slower than the spread code and the spread code of the third phase and sufficiently higher than the bandwidth of the filter means. The demodulation device according to claim 4, wherein 6. The filter means in the first loop circuit receives the spread spectrum signal of 2
2. The demodulator according to claim 1, wherein when the signal is a value signal, the input is 1-bit or multi-bit, the output is multi-bit, and the transfer function of the RC filter is a digital filter that is differentially approximated. 7. The filter means in the first loop circuit makes a coefficient a power of 2 by performing multiplication only by a shift operation, and makes the setting of the coefficient variable so that the cutoff frequency is in octave units. 7. The demodulator according to claim 6, wherein the demodulator is variable. 8. The first loop circuit converts the output of the filter means for passing a signal on the in-phase component side into an index N when approximated by a power of 2, and passes the signal on the quadrature component side. 2. The demodulator according to claim 1, wherein a value obtained by right-shifting the output value from the filter means by the exponent N bits is used as a phase comparison result output. 9. The first loop circuit outputs an output value when a value obtained by right-shifting the output value from the filter means passing a signal on the quadrature component side by the exponent N bits exceeds a predetermined value. The demodulator according to claim 8, further comprising a limiter for limiting the demodulator. 10. The second loop circuit further includes an output value output from the correlation adding means for the spread code which is advanced to the first phase and is set to a second phase, and the second phase. The value added to the output value output from the correlation adder for the delayed spread phase coded as the third phase is converted into an exponent M when approximated by a power of 2, and is set as the second phase. The difference value between the output value of the spread code output from the correlation adder and the output value of the spread code of the third phase output from the correlation adder is right-shifted by the exponent M bits. The demodulator according to claim 8, wherein the value is output as a phase comparison result. 11. The first loop circuit and the second loop circuit each have loop filter means for integrating a phase error to control the phase of the reproduced carrier or the reproduced code, and the loop filter. 2. The demodulating device according to claim 1, wherein the means is a digital filter which is a differential approximation of a transfer function of the active filter. 12. The loop filter means performs multiplication only by a shift operation so that two coefficients are integers A,
2. B is used as 2 ^A and 2 ^B, and the loop bandwidth and response speed are made variable in octave units by making the setting of the integers A and B variable.
1. The demodulator according to 1. 13. The first loop circuit and the second loop circuit are each provided with a limiter for an output value from the loop filter means, and an upper limit value and a lower limit value of the limiter are variable. 13. The method according to claim 12,
The demodulator described. 14. The first loop circuit and the second loop circuit each include a plurality of addition means for adding output values from the correlation addition means having a data 1 bit length or less to a plurality of consecutive times. 2. The demodulator according to claim 1, further comprising: performing correlation detection and phase control of the second loop circuit based on an output value from the multiple addition means. 15. The first loop circuit and the second loop circuit each have moving averaging means for moving and averaging output values from the correlation adding means having a data length of 1 bit or less, and the moving means. 2. The demodulator according to claim 1, wherein correlation detection and phase control of the second loop circuit are performed based on the output value from the averaging means. 16. The first loop circuit and the second loop circuit each dynamically change a cutoff frequency of the filter means according to a reception situation of the spread spectrum signal. The demodulator according to claim 1. 17. The first loop circuit and the second loop circuit, respectively, when the signal strength is large,
17. The demodulator according to claim 16, wherein the cutoff frequency of the filter means is raised and the cutoff frequency of the filter means is lowered when the signal strength is small. 18. The first loop circuit and the second loop circuit each include loop filter means for integrating a phase error to control the phase of the reproduced carrier or the reproduced code, and the first loop circuit and the second loop circuit respectively. And the second loop circuit dynamically adjust the coefficient of the loop filter means and the range of the limiter provided to the output value from the loop filter means according to the reception status of the spread spectrum signal. The demodulation device according to claim 1, wherein the demodulation device is variable. 19. The first loop circuit and the second loop circuit, respectively, when the signal strength is high,
The coefficient is set so that the loop bandwidth of the loop filter means becomes wide, and when the signal strength is small, the coefficient is set so that the loop bandwidth of the loop filter means becomes narrow. 18. The demodulator according to 18. 20. Each of the first loop circuit and the second loop circuit includes a plurality of addition means for adding the output value from the correlation addition means having a data 1 bit length or less to a plurality of consecutive times. The first loop circuit and the second loop circuit each dynamically change the number of additions of the plurality of addition means according to the reception status of the spread spectrum signal. The demodulation device according to claim 1. 21. The demodulator according to claim 1, wherein the first loop circuit is a Costas loop circuit, and the second loop circuit is a delay lock loop circuit. 22. A receiving device for receiving a signal from a satellite to calculate its own position and velocity, comprising: receiving means for receiving the signal from the satellite; and frequency of a received signal received by the receiving means. Frequency conversion means for converting to a predetermined intermediate frequency; synchronization acquisition means for detecting the phase of the spread code in the intermediate frequency signal obtained by the frequency conversion means and for detecting the carrier frequency in the intermediate frequency signal; , The phase of the spread code detected by the synchronization acquisition means and the carrier frequency detected by the synchronization acquisition means for each of a plurality of channels independently provided corresponding to the plurality of satellites. Set by allocating and setting for each satellite, and using the set spreading code phase and carrier frequency as initial values, the spreading And a carrier for synchronizing the signal and the carrier and for demodulating the message contained in the intermediate frequency signal. The plurality of channels in the synchronization holding unit for demodulating the spread spectrum signal are respectively reproduced. A first loop circuit for establishing synchronization between a carrier and a carrier included in the input spread spectrum signal, and a second loop circuit for establishing synchronization between a reproduction code and a spread code included in the input spread spectrum signal. A loop circuit, wherein the first loop circuit and the second loop circuit respectively pass a predetermined frequency band component of a multiplication value of a carrier, a spread code, and the input spread spectrum signal. The filter means and the above-mentioned filter means in units of a data 1-bit length or a predetermined length equal to or shorter than the data 1-bit length. A first correlation value obtained by integrating the passed signal, and a second correlation value obtained by integrating a signal obtained by inverting a half length unit of the unit in the input spread spectrum signal of the signals passed through the filter means. And a correlation adding means for adding the signal, and the plurality of channels respectively perform correlation detection and phase control of the second loop circuit based on an output value from the correlation adding means. apparatus.