JP2007060358A - Synchronization detection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronization detection device having a wider dynamic range. <P>SOLUTION: A multiplier 204 multiplies a FFT processing result of a received data output from an FFT 201 by an FFT processing result of a scramble code output from a FFT portion 203. A maximum value searcher 208 searches a maximum value for the multiplication result. A gain value determination portion 209 determines a gain value, based on the searched maximum value. A gain control unit 205 performs gain control for the multiplication result using the determined gain value. An IFFT 206 conducts IFFT processing for the multiplication result performed with gain control to return it to a time domain, and calculates a correlation value between the received data and the scramble code to generate a delayed profile by electrifying. A threshold determination 210 determines a threshold used for path detection, based on the maximum value of the multiplication result searched by the maximum searcher 208. A path detection unit 207 detects a path by comparing the delayed profile generated by the IFFT 206 with the threshold determined by the threshold determination 210. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a synchronization detection method in wireless communication using a CDMA system.

Conventionally, it has been proposed to perform despreading processing (correlation detection processing) in software using a DSP (Digital Signal Processor) or the like in a receiving unit of a radio base station apparatus or the like adopting the W-CDMA system. More specifically, for example, a method of performing a despreading process in software using a fast Fourier transform (FFT) and an inverse fast Fourier transform (IFFT) has been proposed.
In a radio base station apparatus to which such a method is applied, a synchronization detection process of a spreading code having a wide dynamic range is required.
JP 2004-32568 A

  An object of the present invention is to provide a synchronization detection device having a wide dynamic range.

  The synchronization detection apparatus according to the present invention is based on means for multiplying a received signal (for example, a preamble signal) and a despreading code in the frequency domain, search means for searching for the maximum value of the multiplication results, Gain value determining means for determining a gain value, gain control means for performing gain control of the multiplication result in the frequency domain using the gain value, and a threshold for determining a threshold used for synchronization detection based on the maximum value Determination means.

  In this case, the gain value determining means may dynamically determine the gain value based on the number of digits of the maximum value. Further, the threshold value determining means may dynamically determine a threshold value used for synchronization detection based on the number of digits of the maximum value.

  ADVANTAGE OF THE INVENTION According to this invention, the synchronous detection apparatus with a wide dynamic range can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In order to perform despreading processing (correlation detection processing) in software using a DSP (Digital Signal Processor) or the like in a receiving unit of a wireless base station apparatus or the like adopting the W-CDMA system, for example, fast Fourier transform ( A method of performing a despreading process in software using FFT) and inverse fast Fourier transform (IFFT) has been proposed.
The spreading code synchronization detection processing in the radio base station apparatus to which such a method is applied is performed, for example, as follows.

  First, the radio base station apparatus performs an FFT process on reception data (preamble) transmitted from a mobile terminal (mobile station). Also, FFT processing is performed on a scrambling code prepared on the radio base station apparatus side.

  Next, a product of the result of converting the received data into the frequency domain by FFT processing and the result of converting the scramble code into the frequency domain by FFT processing is obtained for each frequency component. That is, a correlation value in the frequency domain is obtained.

  Next, the correlation value in the obtained frequency domain is returned to the time domain by performing IFFT processing, and the correlation value between the received data and the scramble code is obtained. Then, gain adjustment is performed on the obtained correlation value using a predetermined gain value, and then a delay profile is created by performing power conversion. Then, a path is detected by comparing the obtained delay profile with a predetermined threshold value, and synchronization is detected.

  FIG. 1 is a diagram illustrating a state of a delay profile.

  As shown in FIG. 6A, when a signal is received, a peak appears in a delay time corresponding to the distance to the mobile terminal that outputs the signal. Compared with a predetermined threshold (Threshold), if the threshold is exceeded, the path And detect synchronization. However, as shown in FIG. 5B, when a signal is received from the mobile terminal at an excessive input level, an overflow occurs in an arithmetic unit such as a DSP, and the relative relationship with the threshold is destroyed, which is not desired. Signals may be misdetected as paths.

  As shown in FIG. 5C, when the signal is small, the smaller threshold value can be expected to improve the synchronization detection performance. However, when the threshold value is reduced, the signal is inputted with a large signal level. As a result, erroneous detection occurs as shown in FIG.

  Normally, gain adjustment is performed for the delay profile.

  FIG. 2 is a diagram illustrating a state of a delay profile after gain adjustment. In the figure, the delay profile before gain adjustment is indicated by a dotted line, and the delay profile after gain adjustment is indicated by a solid line.

  In FIG. 6A, the peak can be detected by adjusting the gain. However, in FIG. 5B, the original input signal is small, so that a peak cannot be detected with the same gain as in FIG. On the other hand, in FIG. 5C, since the input signal is large, by giving a gain, an overflow occurs at a desired peak, and an erroneous detection occurs for an undesired signal.

  In order to prevent this, it is conceivable to change the gain according to the reception situation.

  FIG. 3 is a diagram showing the state of the delay profile when the gain is changed. Also in this figure, the delay profile before gain adjustment is indicated by a dotted line, and the delay profile after gain adjustment is indicated by a solid line. The delay profile when the gain is small is indicated by a thin solid line (dark solid line), and the delay profile when the gain is large is indicated by a thick solid line (thin solid line).

  As shown in FIG. 5A, the peak cannot be detected when the gain is small, but the peak can be detected by increasing the gain. On the other hand, as shown in FIG. 5B, when the power before gain adjustment is larger than that in FIG. 5A, the peak can be detected even when the gain is small. However, if the gain is increased too much, overflow occurs. A false detection will occur.

  Here, the power value of the delay profile in the time domain is used as a criterion for gain adjustment, but this method has a problem. As a countermeasure against excessive input, one condition is to suppress overflow, and the gain may be set small so that the maximum value in the delay profile does not overflow. However, gain control for the maximum value is effective when the peak shows a very large value, but it is synchronized because the gain is small when the peak is not so large or the input signal level is low. Detection performance will be inferior.

  On the other hand, if the gain is set to be large in order to improve the performance when the input signal is lowered due to deterioration of the reception environment or the like, the excessive input countermeasure becomes insufficient and the overflow cannot be suppressed. As described above, when gain control is performed in the time domain, it has been difficult to achieve both over-input countermeasures and sufficient synchronization detection performance.

As described above, with the above-described synchronization detection method, it is difficult to ensure the synchronization detection capability regardless of the magnitude of the input signal, that is, to ensure a wide dynamic range.
Synchronization detection in a radio base station to which the present invention is applied as described below is devised so as to ensure a wide dynamic range so that sufficient synchronization detection capability can be ensured regardless of the magnitude of the input signal.

FIG. 4 is a diagram illustrating a configuration of a radio base station apparatus to which the present invention is applied. In the figure, only the components on the receiving side are shown for simplicity.
As shown in the figure, a radio base station apparatus 100 to which the present invention is applied includes an antenna 110, an RF receiving circuit 120, an A / D converter 130, and a baseband signal processing unit 140.

  The RF receiving circuit 120 converts an RF signal received from the mobile terminal (mobile station) via the antenna 110 into a baseband signal. The A / D converter 130 digitizes the analog baseband signal input from the RF receiving circuit 120.

  The baseband signal processing unit 140 performs despreading processing and other signal processing on the digital baseband signal input from the A / D converter 130.

  FIG. 5 is a diagram illustrating a functional configuration of the baseband signal processing unit 140. For the sake of simplicity, only components related to spreading code synchronization processing are shown here.

  As shown in the figure, the baseband signal processing unit 140 includes an FFT unit 201, a spread code storage unit 202, an FFT unit 203, a multiplication unit 204, a gain adjustment unit 205, an IFFT unit 206, and a path detection. Unit 207, maximum value search unit 208, gain value determination unit 209, and threshold value determination unit 210. Each component is realized by, for example, the DSP executing a program stored in a memory (ROM or the like).

  The FFT unit 201 performs an FFT process on the received data. The spreading code storage unit 202 stores a scramble code that is a despreading code. The FFT unit 203 performs an FFT process on the scramble code stored in the spreading code storage unit 202.

  The multiplication unit 204 multiplies the FFT processing result of the reception data output from the FFT unit 201 and the FFT processing result of the scramble code output from the FFT unit 203.

  The maximum value search unit 208 searches for the maximum value from the multiplication results (a plurality of values) output from the multiplication unit 204. That is, the maximum value of the correlation value between the received data and the scramble code in the frequency domain is obtained.

  The gain value determination unit 209 determines a gain value based on the maximum correlation value obtained by the maximum value search unit 208. For example, the gain value determination unit 209 determines the number of digits of the maximum value and determines the gain value based on the number of digits. Note that the gain value may be determined based on the maximum value itself instead of the number of digits of the maximum value. Based on the maximum value itself, finer gain control is possible.

  The gain adjusting unit 205 performs gain control of the multiplication result output from the multiplying unit 204 using the gain value determined by the gain value determining unit 209. That is, the gain of the correlation value in the frequency domain is adjusted.

The IFFT unit 206 performs IFFT processing on the correlation value in the frequency domain that has been gain-adjusted to return to the time domain, obtains a correlation value between the received data and the scramble code, and generates a delay profile by performing power conversion To do.
The IFFT unit 206 adjusts the gain.

  The threshold determination unit 210 determines a threshold used for path detection based on the maximum correlation value obtained by the maximum value search unit 208. For example, the threshold value determination unit 210 calculates the number of digits of the maximum value obtained by the maximum value search unit 208 and determines a threshold value used for path detection based on the number of digits. Note that the threshold used for path detection may be determined based on the maximum value itself, not the number of digits of the maximum value. Based on the maximum value itself, finer threshold control is possible.

  The path detection unit 207 detects a path by comparing the delay profile generated by the IFFT unit 206 with the threshold value determined by the threshold value determination unit 210.

  Next, synchronization detection processing in the baseband signal processing unit 140 having the above configuration will be described.

  FIG. 6 is a flowchart showing the flow of synchronization detection processing in the baseband signal processing unit 140.

  As shown in the figure, first, the FFT section 201 performs FFT processing on the received data (preamble) received from the mobile terminal (S301). Next, the FFT unit 203 performs FFT processing on the scramble code prepared in the radio base station apparatus 100 (spreading code storage unit 202) (S302).

  Next, the multiplication unit 204 obtains, for each frequency component, a product of the result of converting the received data into the frequency domain by FFT processing and the result of converting the scramble code into the frequency domain by FFT processing (S303). That is, a correlation value in the frequency domain is obtained.

  Next, the maximum value search unit 208 searches for the product of the received signal in the frequency domain and the scramble code, that is, the maximum correlation value in the frequency domain (S304).

  Next, based on the number of digits of the maximum value obtained in S304, the gain value determination unit 209 determines the gain value in the frequency domain (S305). Here, the reason why the gain is determined based on the number of digits of the maximum value is that in many cases, gain control is realized by bit-shifting a register in an arithmetic unit such as a DSP. is there. If the number of digits is known, the gain can be controlled by designating the shift amount so as to match the number of digits.

  FIG. 7 is a diagram illustrating a state of a delay profile in the frequency domain.

  As shown in FIG. 5A, unlike the time domain, a large peak does not appear in the frequency domain regardless of the presence or absence of an input signal. For this reason, each frequency component increases in accordance with the input signal level, but overflow does not easily occur even at the maximum value. Therefore, as shown in FIG. 4B, the gain is increased when the level is small, and when the level is large as shown in FIG. It becomes possible to adjust so that it becomes. In FIGS. 2B and 2C, the delay profile before gain adjustment is indicated by a dotted line, and the delay profile after gain adjustment is indicated by a solid line.

  Next, based on the number of digits of the maximum value obtained in S304, the threshold determination unit 210 determines a threshold used for path detection (S306). In order to increase the signal detection capability, a process for setting an appropriate threshold value may be performed based on the input signal. In synchronization detection processing using FFT, an appropriate threshold value can be set by confirming a level in the frequency domain and determining a threshold value based on the level.

  Next, using the gain value determined in S305, gain control of the correlation value in the frequency domain is performed in gain adjustment section 205, and gain adjustment is also performed in IFFT section 206 (S307). Next, IFFT section 206 returns the time-domain by performing IFFT processing on the gain-adjusted correlation value, obtains the correlation value between the received data and the scramble code, and creates a delay profile by generating power. (S308). Then, the path detection unit 207 detects the path by comparing the delay profile obtained in S308 with the threshold value determined in S306, and detects synchronization (S309).

  As described above, according to the present invention, the signal gain value and the threshold value used for path detection can be dynamically changed in accordance with the input signal level while using the FFT characteristics in synchronization detection. Therefore, synchronization detection can be performed appropriately regardless of the signal level, and a wide dynamic range can be realized.

  Search processing in the CDMA method is usually realized by a large scale integrated circuit (LSI), and fine AGC control is necessary to ensure a wide dynamic range. By executing the diffusion processing, it is possible to realize a wide dynamic range while greatly reducing the hardware portion, and can greatly contribute to downsizing and cost reduction.

It is a figure which shows the mode of a delay profile. It is a figure which shows the mode of the delay profile which performed gain adjustment. It is a figure which shows the mode of the delay profile at the time of changing a gain. It is a figure which shows the structure of the radio base station apparatus (reception side) to which this invention is applied. It is a figure which shows the function structure of a baseband signal processing part. It is a flowchart which shows the flow of the synchronous detection process in a baseband signal process part. It is a figure which shows the mode of the delay profile in a frequency domain.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Radio base station apparatus 110 Antenna 120 RF receiving circuit 130 A / D converter 140 Baseband signal processing part 201 FFT part 202 Spreading code memory | storage part 203 FFT part 204 Multiplication part 205 Gain adjustment part 206 IFFT part 207 Path | line detection part 208 Maximum value Search unit 209 Gain value determination unit 210 Threshold value determination unit

Claims (3)

Means for multiplying the received signal and the despreading code in the frequency domain;
A search means for searching for the maximum value of the multiplication results;
Gain value determining means for determining a gain value based on the maximum value;
Gain control means for performing gain control of the multiplication result in the frequency domain using the gain value;
And a threshold value determining means for determining a threshold value used for synchronization detection based on the maximum value. The synchronization detection apparatus according to claim 1, wherein the gain value determination unit dynamically determines a gain value based on the number of digits of the maximum value. The synchronization detection apparatus according to claim 1, wherein the threshold value determination unit dynamically determines a threshold value used for synchronization detection based on the number of digits of the maximum value.

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