JP3956722B2 - Matched filter device, correlation detection method, and receiver - Google Patents

Description

【０１３８】
なお、上式（２）において、ＰＮ_ｒ（ｋ）は、ＰＮ（ｋ）の実数成分を示し、ＰＮ_ｊ（ｋ）はＰＮ（ｋ）の虚数成分を示すものである。
【０１３９】
ディジタルマッチドフィルタ１００において、補完フィルタ１１１は、上式（２）を用いることにより、負の周波数成分を復元することができる。
【０１４０】
ディジタルマッチドフィルタ１００においては、このような補完フィルタ１１１を介して得られる周波数領域信号を、キャリアをＩＦ信号におけるキャリアと互いに等しくさせるために、シフタ１１２を用いて周波数領域上で例えば１ＭＨｚだけシフトさせ、得られた周波数領域信号を乗算器１１３に供給する。
【０１４１】
一方、ディジタルマッチドフィルタ１００においては、ＩＦ信号については、上述したように、サンプラ１０１によって４．０９６ＭＨｚのサンプリング周波数でサンプリングを行う。
【０１４２】
ここで、ディジタルマッチドフィルタ１００における乗算器１１３に相当する従来のディジタルマッチドフィルタにおける乗算器から出力される周波数領域信号のスペクトル関数を図９に示す。なお、同図における横軸は、図８と同様に、周波数を示すものであるが、値として４０９６点からなるＦＦＴ演算のポイント数を示している。同図から明らかなように、このスペクトル関数は、拡散符号を１ＭＨｚだけシフトしていることから、負の周波数成分をほとんど有しないものとなっている。さらに、このスペクトル関数からなる周波数領域信号に対してＩＦＦＴ処理部１１４に相当する従来のディジタルマッチドフィルタにおけるＩＦＦＴ処理部によってＩＦＦＴ処理を施して得られる時間領域信号である相互相関関数は、図１０に示すようになる。
【０１４３】
これに対して、図１１にスペクトル関数を示すように、乗算器から出力される周波数領域信号のうち負の周波数成分を"０"とした周波数領域信号に対してＩＦＦＴ処理を施して得られる時間領域信号である相互相関関数は、図１２に示すようになる。図１０に示す相互相関関数と図１２に示す相互相関関数とを比較して明らかなように、図１２に示す相互相関関数の方が若干ピークの値が低くなるものの、ピークを検出するのには十分な強度を有するものであり、拡散符号の位相を示すピークの位置については全く同じものとなり、両者は、ほぼ同じ結果ということができる。
【０１４４】
そこで、ディジタルマッチドフィルタ１００においては、ＦＦＴ処理部１０３によって得られた周波数領域信号を負の周波数除去フィルタ１０４に通過させることによって正の周波数成分のみにし、メモリ１０５に記憶させる。
【０１４５】
このように、ディジタルマッチドフィルタ１００においては、負の周波数除去フィルタ１０４を設け、負の周波数成分を除去することにより、メモリ１０５の必要容量を３２ｋバイトから１６ｋバイトへと１／２に削減することができる。
【０１４６】
ディジタルマッチドフィルタ１００においては、このような負の周波数除去フィルタ１０４を介して得られる周波数領域信号を虚数反転フィルタ１０６に通過させて複素共役な信号に変換し、得られた周波数領域信号を乗算器１１３に供給する。
【０１４７】
なお、図６においては、メモリ１０５によってバッファリングされた周波数領域信号を虚数反転フィルタ１０６に通過させ、メモリ１１０によってバッファリングされた周波数領域信号を補完フィルタ１１１を介してシフタ１１２によってシフトしているが、ディジタルマッチドフィルタ１００においては、メモリ１０５によってバッファリングされた周波数領域信号とメモリ１１０によってバッファリングされた周波数領域信号とのうち、いずれか一方を、虚数反転フィルタ１０６に通過させて複素共役な信号に変換するとともに、他方を、シフタ１１２を用いて周波数領域上でシフトさせればよく、虚数反転フィルタ１０６とシフタ１１２とを入れ替えても、同様の効果を得ることができる。また、ディジタルマッチドフィルタ１００においては、シフタ１１２をＩＦ信号側又は拡散符号側のいずれかに設けるのではなく、両方に設けてもよい。
【０１４８】
さらにまた、ディジタルマッチドフィルタ１００においては、ＩＦＦＴ処理部１１４における演算量を削減するとともに、これにともない、このＩＦＦＴ処理部１１４によって得られる相互相関関数をバッファリングするメモリ１１５の必要容量も削減することができる。
【０１４９】
負の周波数成分が"０"とされるデータ数Ｎが"１６"である周波数領域信号に対してＩＦＦＴ処理を施す際の信号の流れを図１３に示す。同図においては、左側がＦＦＴ演算の結果を示す入力信号Ｒ（ｋ）（０≦ｋ＜Ｎ）であり、右側が出力信号ｒ（ｎ）（０≦ｎ＜Ｎ）である。また、同図においては、Ｒ０（ｋ'），Ｒ１（ｋ'）（０≦ｋ'＜Ｎ／２）は、それぞれ、ＩＦＦＴ演算の１段目が終了した時点での中間演算値を示す信号を表し、ｒ０（ｎ'），ｒ１（ｎ'）（０≦ｎ'＜Ｎ／２）は、それぞれ、Ｒ０（ｋ'），Ｒ１（ｋ'）に対するＩＦＦＴ演算の結果を示す信号を表すものである。ＩＦＦＴ処理は、このようなバタフライ演算が繰り返されることによって実現される。
【０１５０】
ここで、負の周波数成分が"０"であることから、次式（３）が成立する。
【０１５１】
【数３】

【０１５２】
なお、上式（３）における係数Ｗは、虚数単位を"ｊ"とすると、Ｗ＝ｅｘｐ（２πｊ／Ｎ）で表される。すなわち、中間演算値を示す信号Ｒ１（ｋ'）は、入力信号Ｒ（ｋ'）に対して係数Ｗ^{ｋ '}が乗算されたものとされる一方で、信号Ｒ０（ｋ'）は、入力信号Ｒ（ｋ'）そのものとされる。具体的には、信号Ｒ０（０）〜Ｒ０（７）は、それぞれ、Ｒ（０）〜Ｒ（７）となり、信号Ｒ１（０）〜Ｒ１（７）は、それぞれ、Ｒ（０）Ｗ^０〜Ｒ（７）Ｗ^７となる。同図から、入力信号Ｒ（ｋ）に対するＩＦＦＴ演算の結果を示す出力信号ｒ（ｎ）のうち、偶数番目のデータをくし形フィルタによって抜き出したものと、中間演算値を示す信号Ｒ０（ｋ'）に対するＩＦＦＴ演算の結果を示す信号ｒ０（ｎ'）とは、同図中矩形Ｃに示すように、等価であることが明らかである。
【０１５３】
そこで、ディジタルマッチドフィルタ１００においては、入力信号Ｒ（ｋ）のうち正の周波数成分に相当する信号Ｒ０（ｋ'）のみに対して、ＩＦＦＴ処理を行うようにする。すなわち、ディジタルマッチドフィルタ１００においては、乗算器１１３によって得られる周波数領域信号のうち正の周波数成分のみに対して、ＩＦＦＴ処理部１１４によってＩＦＦＴ処理を施す。
【０１５４】
これにより、ディジタルマッチドフィルタ１００においては、ＩＦＦＴ処理部１１４におけるＩＦＦＴ演算のポイント数が４０９６点から２０４８点に半減され、演算量を削減することができる。したがって、ディジタルマッチドフィルタ１００においては、メモリ１１５の必要容量を３２ｋバイトから１６ｋバイトへと１／２に削減することができる。
【０１５５】
ただし、ディジタルマッチドフィルタ１００においては、ＩＦＦＴ演算のポイント数を半減することにより、得られる結果である相互相関関数の時間分解能が低下することになる。具体的には、ディジタルマッチドフィルタ１００におけるＩＦＦＴ処理部１１４に相当する従来のディジタルマッチドフィルタにおけるＩＦＦＴ処理部から出力される相互相関関数の一部を図１４に示すとともに、ＩＦＦＴ処理部１１４から出力される相互相関関数の一部を図１５及び図１６に示す。なお、同図における黒丸は、１サンプル点を示している。
【０１５６】
ここで、図１５に示す相互相関関数は、図１４に示す相互相関関数における相関のピークが偶数番目のサンプル点にある場合に、これをくし形フィルタからなるピーク検出器１１６によって抜き出した場合を示している。一方、図１６に示す相互相関関数は、図１４に示す相互相関関数における相関のピークが奇数番目のサンプル点にある場合に、これをくし形フィルタからなるピーク検出器１１６によって抜き出した場合を示している。
【０１５７】
このように、ディジタルマッチドフィルタ１００においては、図１４に示す相互相関関数の時間分解能に比べ、図１５及び図１６に示す相互相関関数の時間分解能が低下する。また、ディジタルマッチドフィルタ１００においては、相関のピークが偶数番目のサンプル点にある場合には、図１５に示すように、相関のピークを正確に検出することができるものの、相関のピークが奇数番目のサンプル点にある場合には、図１６に示すように、ピーク値が３／４倍程度に減少してしまう。
【０１５８】
しかしながら、ディジタルマッチドフィルタ１００においては、図１６に示す例は最悪の場合であり、実際には、ピーク値と同様に、ノイズ成分も減少することになることから、Ｓ／Ｎが大幅に悪化することはなく、時間分解能が低下することによって何らの問題も生じない。
【０１５９】
また、ディジタルマッチドフィルタ１００においては、サイン／コサイン発生器１１７における演算量を削減するとともに、これにともない、このサイン／コサイン発生器１１７によって発生したサイン関数又はコサイン関数を保持するメモリ１１８の必要容量も削減することができる。
【０１６０】
一般に、サイン関数は、三角関数を利用することによってコサイン関数から求めることができる。また、コサイン関数についても、その対称性を利用して、位相が０ラジアン〜π/２ラジアンまでの成分から、全ての位相について求めることができる。すなわち、サイン関数及びコサイン関数においては、次式（４）乃至次式（７）に示す関係が成立する。
【０１６１】
【数４】

【０１６２】
【数５】

【０１６３】
【数６】

【０１６４】
【数７】

【０１６５】
そこで、ディジタルマッチドフィルタ１００においては、サイン／コサイン発生器１１７によって位相が０ラジアン〜π／２ラジアンまでのコサイン関数の成分のみを算出して発生し、これらをメモリ１１８に保持させる。そして、ディジタルマッチドフィルタ１００においては、三角関数を利用する式として、メモリ１１８に保持されたコサイン関数に基づいて上式（４）乃至上式（７）のそれぞれを組み込んだ複数のパターンからなる算出式を図示しない所定の三角関数発生器によって発生して所定のメモリに保持させておき、ＦＦＴ処理部１０３，１０８及び／又はＩＦＦＴ処理部１１４によってメモリ１１８に保持されているコサイン関数を読み出す際に、位相に応じて利用する式を切り替えることにより、メモリ１１８に保持しているコサイン関数のみを用いて全ての位相についてのサイン関数及び／又はコサイン関数を利用することができる。
【０１６６】
具体的には、ディジタルマッチドフィルタ１００においては、図１７に示す一連の処理を経ることにより、サイン／コサイン発生器１１７によって発生されてメモリ１１８に保持されている位相が０ラジアン〜π／２ラジアンまでのコサイン関数の成分を用いて、ＦＦＴ処理部１０３，１０８及び／又はＩＦＦＴ処理部１１４によって任意の位相のサイン関数及び／又はコサイン関数を利用する。
【０１６７】
すなわち、ディジタルマッチドフィルタ１００においては、同図に示すように、ＦＦＴ処理部１０３，１０８及び／又はＩＦＦＴ処理部１１４が信号を入力すると、ステップＳ１において、ＦＦＴ処理部１０３，１０８及び／又はＩＦＦＴ処理部１１４のそれぞれによって必要となる関数の位相が０ラジアン〜π／２ラジアンであるか否かを判定する。
【０１６８】
ここで、必要となる関数の位相が０ラジアン〜π／２ラジアンであるものと判定した場合には、ディジタルマッチドフィルタ１００においては、ステップＳ２において、三角関数発生器によって発生してメモリに保持されている第１のパターンの式Ａを用いて、ＦＦＴ処理部１０３，１０８及び／又はＩＦＦＴ処理部１１４のそれぞれによって位相が０ラジアン〜π／２ラジアンである必要なサイン関数及び／又はコサイン関数を利用する。
【０１６９】
一方、必要となる関数の位相が０ラジアン〜π／２ラジアンでないものと判定した場合には、ディジタルマッチドフィルタ１００においては、ステップＳ３へと処理を移行し、ＦＦＴ処理部１０３，１０８及び／又はＩＦＦＴ処理部１１４のそれぞれによって必要となる関数の位相がπ／２ラジアン〜πラジアンであるか否かを判定する。
【０１７０】
ここで、必要となる関数の位相がπ／２ラジアン〜πラジアンであるものと判定した場合には、ディジタルマッチドフィルタ１００においては、ステップＳ４において、三角関数発生器によって発生してメモリに保持されている第２のパターンの式Ｂを用いて、ＦＦＴ処理部１０３，１０８及び／又はＩＦＦＴ処理部１１４のそれぞれによって位相がπ／２ラジアン〜πラジアンである必要なサイン関数及び／又はコサイン関数を利用する。
【０１７１】
一方、必要となる関数の位相がπ／２ラジアン〜πラジアンでないものと判定した場合には、ディジタルマッチドフィルタ１００においては、ステップＳ５へと処理を移行し、ＦＦＴ処理部１０３，１０８及び／又はＩＦＦＴ処理部１１４のそれぞれによって必要となる関数の位相がπラジアン〜３π／２ラジアンであるか否かを判定する。
【０１７２】
ここで、必要となる関数の位相がπラジアン〜３π／２ラジアンであるものと判定した場合には、ディジタルマッチドフィルタ１００においては、ステップＳ６において、三角関数発生器によって発生してメモリに保持されている第３のパターンの式Ｃを用いて、ＦＦＴ処理部１０３，１０８及び／又はＩＦＦＴ処理部１１４のそれぞれによって位相がπラジアン〜３π／２ラジアンである必要なサイン関数及び／又はコサイン関数を利用する。
【０１７３】
一方、必要となる関数の位相がπラジアン〜３π／２ラジアンでないものと判定した場合には、必要となる関数の位相は３π／２ラジアン〜２πラジアンであることから、ディジタルマッチドフィルタ１００においては、ステップＳ７へと処理を移行し、三角関数発生器によって発生してメモリに保持されている第４のパターンの式Ｄを用いて、ＦＦＴ処理部１０３，１０８及び／又はＩＦＦＴ処理部１１４のそれぞれによって位相が３π／２ラジアン〜２πラジアンである必要なサイン関数及び／又はコサイン関数を利用する。
【０１７４】
ディジタルマッチドフィルタ１００においては、このような一連の処理を経ることにより、サイン／コサイン発生器１１７によって発生されてメモリ１１８に保持されている位相が０ラジアン〜π／２ラジアンまでのコサイン関数の成分を用いて、ＦＦＴ処理部１０３，１０８及び／又はＩＦＦＴ処理部１１４によって任意の位相のサイン関数及び／又はコサイン関数を利用することができる。
【０１７５】
これにより、ディジタルマッチドフィルタ１００においては、サイン／コサイン発生器１１７における演算量を１／８倍に削減することができるとともに、メモリ１１８の必要容量を３２ｋバイトから４ｋバイトへと１／８に削減することができる。
【０１７６】
なお、サイン／コサイン発生器１１７によって発生してメモリ１１８に保持しておく関数は、必ずしも位相が０ラジアン〜π／２ラジアンまでのコサイン関数の成分である必要はなく、ディジタルマッチドフィルタ１００においては、位相が０ラジアン〜π／２ラジアン、π／２ラジアン〜πラジアン、πラジアン〜３π／２ラジアン、又は３π／２ラジアン〜２πラジアンのいかなる成分をメモリ１１８に保持させてもよく、コサイン関数に限らずサイン関数をメモリ１１８に保持させてもよく、これら全ての場合において任意の位相のサイン関数及び／又はコサイン関数を利用することができる。
【０１７７】
このように、ディジタルマッチドフィルタ１００においては、ＩＦ信号に対してＦＦＴ処理を施して得られる周波数領域信号を保持するメモリ１０５の必要容量が１６ｋバイトとなり、拡散符号に対してＦＦＴ処理を施して得られる周波数領域信号を保持するメモリ１１０の必要容量が８ｋバイトとなり、周波数領域信号に対してＩＦＦＴ処理を施して得られる相互相関関数を保持するメモリ１１５の必要容量が１６ｋバイトとなり、サイン／コサイン発生器１１７によって発生したサイン関数又はコサイン関数を保持するメモリ１１８の必要容量が４ｋバイトとなることから、合計で４４ｋバイトの容量のメモリがあればよく、従来の１２８ｋバイトに比べて約１／３程度にメモリの必要容量を削減することができる。
【０１７８】
また、ディジタルマッチドフィルタ１００においては、拡散符号を周波数領域信号に変換する際のデータ数を削減することによってＦＦＴ処理部１０８における演算量を従来に比べ削減することができる。さらに、ディジタルマッチドフィルタ１００においては、周波数領域信号に変換されたＩＦ信号と拡散符号とのそれぞれを乗算する際のデータ数が従来に比べ１／２になることから、乗算器１１３における演算量も従来に比べ１／２に削減することができる。さらにまた、ディジタルマッチドフィルタ１００においては、ＩＦＦＴ処理を施す際のＩＦＦＴ演算のポイント数が従来に比べ１／２になることから、ＩＦＦＴ処理部１１４における演算量を従来に比べ１／２以下に削減することができる。また、ディジタルマッチドフィルタ１００においては、サイン／コサイン発生器１１７における演算量を、従来に比べ１／８に削減することができる。
【０１７９】
以上説明したように、ＧＰＳ受信機１０は、同期捕捉部２４によって拡散符号の位相を探索するための相関値を検出する際に、搭載するメモリの容量を削減し、且つ、各部の演算量も削減するのにかかわらず、従来と同様の結果を得ることができ、相関のピークを正確に且つ容易に検出することができる。したがって、ＧＰＳ受信機１０は、特に集積回路化して構成する場合には、集積度を上げることが可能となることから、小型化及び低コスト化を図りつつ演算時間も削減することができる。
【０１８０】
なお、本発明は、上述した実施の形態に限定されるものではない。例えば、上述した実施の形態では、ＧＰＳ受信機１０を用いて説明したが、本発明は、スペクトラム拡散信号を受信して復調する受信機であれば、いかなるものでも適用することができる。
【０１８１】
また、上述した実施の形態では、ＧＰＳ受信機１０を用いて説明したが、本発明は、衛星を利用した測位システム、すなわち、ＧＮＳＳシステムを適用した受信機の機能が組み込まれた電子機器であれば、いかなるものであっても適用することができる。ＧＮＳＳシステムとしては、米国における上述したＧＰＳシステムの他、旧ソ連邦におけるＧＬＯＮＡＳＳ（Global Navigation Satellites System）や、欧州を中心として開発が進められているＧＡＬＩＬＥＯ等があるが、本発明は、これら全てのＧＮＳＳシステムを適用することができるものである。
【０１８２】
このように、本発明は、その趣旨を逸脱しない範囲で適宜変更が可能であることはいうまでもない。
【０１８３】
【発明の効果】
以上詳細に説明したように、本発明にかかるマッチドフィルタ装置は、入力されたスペクトラム拡散信号における拡散符号の位相を検出するために、拡散符号と自己が発生する拡散符号との相関を検出するマッチドフィルタ装置であって、スペクトラム拡散信号が所定のサンプリング周波数でサンプリングされて入力されたデータに対して高速フーリエ変換処理を施す第１の高速フーリエ変換処理手段と、この第１の高速フーリエ変換処理手段によって高速フーリエ変換処理が施されて得られた周波数領域信号のうち負の周波数成分を除去する負の周波数除去手段と、この負の周波数除去手段によって負の周波数成分が除去された周波数領域信号をバッファリングする第１の記憶手段と、スペクトラム拡散信号における拡散符号と同じ拡散符号を発生する拡散符号発生手段と、この拡散符号発生手段によって発生された拡散符号に対して高速フーリエ変換処理を施す第２の高速フーリエ変換処理手段と、少なくともこの第２の高速フーリエ変換処理手段によって高速フーリエ変換処理が施されて得られた周波数領域信号をバッファリングする第２の記憶手段とを備える。
【０１８４】
したがって、本発明にかかるマッチドフィルタ装置は、第１の高速フーリエ変換処理手段によって高速フーリエ変換処理が施されて得られた周波数領域信号のうち負の周波数成分を負の周波数除去手段によって除去し、得られた周波数領域信号を第1の記憶手段に記憶させるとともに、少なくとも第２の高速フーリエ変換処理手段によって高速フーリエ変換処理が施されて得られた周波数領域信号を第２の記憶手段に記憶させることにより、第1の記憶手段の容量を削減して小型化及び低コスト化を図ることができる。
【０１８５】
また、この本発明にかかるマッチドフィルタ装置において、第２の高速フーリエ変換処理手段には、拡散符号発生手段によって発生された拡散符号が、スペクトラム拡散信号における拡散符号のチップレートの２倍の周波数でサンプリングされて入力される。
【０１８６】
したがって、本発明にかかるマッチドフィルタ装置は、第1の高速フーリエ変換処理手段によって高速フーリエ変換処理が施されるスペクトラム拡散信号のデータ数の１／２のデータ数からなる拡散符号に対して、第２の高速フーリエ変換処理手段によって高速フーリエ変換処理を施すことにより、第２の高速フーリエ変換処理手段における演算量を削減し、演算時間を削減することができる。
【０１８７】
さらに、この本発明にかかるマッチドフィルタ装置は、第２の高速フーリエ変換処理手段によって高速フーリエ変換処理が施されて得られた周波数領域信号のうち負の周波数成分を除去する他の負の周波数除去手段を備え、第２の記憶手段は、他の負の周波数除去手段によって負の周波数成分が除去された周波数領域信号をバッファリングする。
【０１８８】
さらにまた、この本発明にかかるマッチドフィルタ装置は、第２の記憶手段によってバッファリングされた周波数領域信号に対して他の負の周波数除去手段によって除去された負の周波数成分を復元する補完手段を備える。
【０１８９】
したがって、本発明にかかるマッチドフィルタ装置は、第２の高速フーリエ変換処理手段によって高速フーリエ変換処理が施されて得られた周波数領域信号のうち負の周波数成分を他の負の周波数除去手段によって除去し、得られた周波数領域信号を第２の記憶手段に記憶させ、さらに、他の負の周波数除去手段によって負の周波数成分が除去された正の周波数成分のみからなる周波数領域信号から、補完手段によって負の周波数成分を復元することにより、第２の記憶手段の容量を削減して小型化及び低コスト化を図ることができる。
【０１９０】
また、この本発明にかかるマッチドフィルタ装置は、少なくとも第１の記憶手段によってバッファリングされた周波数領域信号と少なくとも第２の記憶手段によってバッファリングされた周波数領域信号とを乗算する乗算手段と、この乗算手段によって乗算された周波数領域信号に対して逆高速フーリエ変換処理を施す逆高速フーリエ変換処理手段と、この逆高速フーリエ変換処理手段によって逆高速フーリエ変換処理が施されて得られた相互相関関数をバッファリングする第３の記憶手段とを備える。
【０１９１】
さらに、この本発明にかかるマッチドフィルタ装置において、逆高速フーリエ変換処理手段は、乗算手段によって得られる周波数領域信号のうち正の周波数成分のみに対して、逆高速フーリエ変換処理を施す。
【０１９２】
したがって、本発明にかかるマッチドフィルタ装置は、乗算手段によって得られる周波数領域信号のうち１／２のデータ数からなる周波数領域信号に対して、逆高速フーリエ変換処理手段によって逆高速フーリエ変換処理を施し、さらに、逆高速フーリエ変換処理手段によって逆高速フーリエ変換処理が施されて得られた相互相関関数を第３の記憶手段に記憶させることにより、逆高速フーリエ変換処理手段における演算量を削減し、演算時間を削減することができるとともに、第３の記憶手段の容量を削減して小型化及び低コスト化を図ることができる。
【０１９３】
さらにまた、この本発明にかかるマッチドフィルタ装置は、サイン関数又はコサイン関数を発生するサイン／コサイン発生手段と、このサイン／コサイン発生手段によって発生されたサイン関数又はコサイン関数を、第１の高速フーリエ変換処理手段、第２の高速フーリエ変換処理手段、及び／又は逆高速フーリエ変換処理手段のそれぞれによって読み出し可能に保持する第４の記憶手段とを備える。
【０１９４】
また、この本発明にかかるマッチドフィルタ装置は、第４の記憶手段に保持されたサイン関数又はコサイン関数に基づいて、三角関数を利用した複数のパターンからなる算出式を発生する三角関数発生手段と、この三角関数発生手段によって発生された複数のパターンからなる算出式を保持する記憶手段とを備え、サイン／コサイン発生手段は、サイン関数又はコサイン関数の一部の成分のみを発生して第４の記憶手段に保持させ、第１の高速フーリエ変換処理手段、第２の高速フーリエ変換処理手段、及び／又は逆高速フーリエ変換処理手段は、それぞれ、必要となる関数の位相に応じて、記憶手段に記憶されている複数のパターンからなる算出式を切り替えることにより、任意の位相のサイン関数及び／又はコサイン関数を利用する。
【０１９５】
したがって、本発明にかかるマッチドフィルタ装置は、サイン／コサイン発生手段によってサイン関数又はコサイン関数の一部の成分のみを発生し、第４の記憶手段に保持させることにより、サイン／コサイン発生手段における演算量を削減し、演算時間を削減することができるとともに、第４の記憶手段の容量を削減して小型化及び低コスト化を図ることができる。
【０１９６】
このように、本発明にかかるマッチドフィルタ装置は、搭載する記憶手段の容量を削減して小型化及び低コスト化を図りつつ演算時間も削減することができる。
【０１９７】
また、本発明にかかる相関検出方法は、入力されたスペクトラム拡散信号における拡散符号の位相を検出するために、拡散符号と自己が発生する拡散符号との相関を検出する相関検出方法であって、スペクトラム拡散信号が所定のサンプリング周波数でサンプリングされて入力されたデータに対して高速フーリエ変換処理を施す工程と、入力されたデータに対する高速フーリエ変換処理が施されて得られた周波数領域信号のうち負の周波数成分を除去する工程と、負の周波数成分が除去された周波数領域信号を第1の記憶手段にバッファリングする工程と、スペクトラム拡散信号における拡散符号と同じ拡散符号を発生する工程と、発生された拡散符号に対して高速フーリエ変換処理を施す工程と、少なくとも発生された拡散符号に対する高速フーリエ変換処理が施されて得られた周波数領域信号を第２の記憶手段にバッファリングする工程とを備える。
【０１９８】
したがって、本発明にかかる相関検出方法は、入力されたデータに対する高速フーリエ変換処理が施されて得られた周波数領域信号のうち負の周波数成分を除去し、得られた周波数領域信号を第1の記憶手段に記憶させるとともに、少なくとも発生された拡散符号に対する高速フーリエ変換処理が施されて得られた周波数領域信号を第２の記憶手段に記憶させることにより、第1の記憶手段の容量を削減して小型化及び低コスト化を図ることが可能となる。
【０１９９】
さらに、本発明にかかる受信装置は、衛星からの信号を受信して自己の位置及び速度を算出する受信装置であって、衛星からの信号を受信する受信手段と、この受信手段によって受信した受信信号の周波数を所定の中間周波数に変換する周波数変換手段と、この周波数変換手段によって得られた中間周波数信号における拡散符号の位相を検出する同期捕捉と中間周波数信号におけるキャリア周波数の検出とを行う同期捕捉手段と、この同期捕捉手段によって検出された拡散符号の位相及び同期捕捉手段によって検出されたキャリア周波数を、複数の衛星に対応して独立に設けられた複数のチャンネルのそれぞれに対して衛星毎に割り当てて設定し、設定した拡散符号の位相及びキャリア周波数を初期値として、拡散符号とキャリアとの同期保持を行うとともに、中間周波数信号に含まれるメッセージの復調を行う同期保持手段とを備え、スペクトラム拡散信号である中間周波数信号における拡散符号の位相を検出するために、拡散符号と自己が発生する拡散符号との相関を検出する同期捕捉手段は、中間周波数信号が所定のサンプリング周波数でサンプリングされて入力されたデータに対して高速フーリエ変換処理を施す第１の高速フーリエ変換処理手段と、この第１の高速フーリエ変換処理手段によって高速フーリエ変換処理が施されて得られた周波数領域信号のうち負の周波数成分を除去する負の周波数除去手段と、この負の周波数除去手段によって負の周波数成分が除去された周波数領域信号をバッファリングする第１の記憶手段と、中間周波数信号における拡散符号と同じ拡散符号を発生する拡散符号発生手段と、この拡散符号発生手段によって発生された拡散符号に対して高速フーリエ変換処理を施す第２の高速フーリエ変換処理手段と、少なくともこの第２の高速フーリエ変換処理手段によって高速フーリエ変換処理が施されて得られた周波数領域信号をバッファリングする第２の記憶手段とを有するマッチドフィルタを用いて構成される。
【０２００】
したがって、本発明にかかる受信装置は、同期捕捉手段における第１の高速フーリエ変換処理手段によって高速フーリエ変換処理が施されて得られた周波数領域信号のうち負の周波数成分を負の周波数除去手段によって除去し、得られた周波数領域信号を第1の記憶手段に記憶させるとともに、少なくとも第２の高速フーリエ変換処理手段によって高速フーリエ変換処理が施されて得られた周波数領域信号を第２の記憶手段に記憶させることにより、第1の記憶手段の容量を削減して小型化及び低コスト化を図ることができる。
【図面の簡単な説明】
【図１】本発明の実施の形態として示すＧＰＳ受信機の構成を説明するブロック図である。
【図２】同ＧＰＳ受信機が備える同期保持部の構成を説明するブロック図である。
【図３】同ＧＰＳ受信機が備える同期保持部が有するチャンネル回路の構成を説明するブロック図である。
【図４】同ＧＰＳ受信機が備える同期保持部における拡散符号の位相合わせについて説明するための図である。
【図５】同ＧＰＳ受信機が備える同期保持部における拡散符号の位相補正について説明するための図である。
【図６】同ＧＰＳ受信機が備える同期捕捉部として適用することができるＦＦＴを利用したディジタルマッチドフィルタの構成を説明するブロック図である。
【図７】同ＧＰＳ受信機が備える同期捕捉部として図６に示すディジタルマッチドフィルタを適用した場合における実際の実装例を説明するブロック図である。
【図８】従来のディジタルマッチドフィルタによって拡散符号に対してＦＦＴ処理を施して得られる周波数領域信号のスペクトル関数の例を説明する図である。
【図９】従来のディジタルマッチドフィルタにおける乗算器から出力される周波数領域信号のスペクトル関数の例を説明する図である。
【図１０】従来のディジタルマッチドフィルタによって図９にスペクトル関数を示す周波数領域信号に対してＩＦＦＴ処理を施して得られる相関値の時間変化を示す出力波形の例を説明する図である。
【図１１】図６に示すディジタルマッチドフィルタにおける乗算器から出力される負の周波数成分を"０"とした周波数領域信号のスペクトル関数の例を説明する図である。
【図１２】図６に示すディジタルマッチドフィルタによって図１１にスペクトル関数を示す周波数領域信号に対してＩＦＦＴ処理を施して得られる相関値の時間変化を示す出力波形の例を説明する図である。
【図１３】負の周波数成分が"０"とされるデータ数Ｎが"１６"である周波数領域信号に対してＩＦＦＴ処理を施す際の信号の流れを説明する図である。
【図１４】従来のディジタルマッチドフィルタによって得られる相互相関関数の一部を説明する図である。
【図１５】図６に示すディジタルマッチドフィルタによって得られる相互相関関数の一部を説明する図であって、相関のピークが偶数番目のサンプル点にある場合に抜き出した相互相関関数の一部を説明する図である。
【図１６】図６に示すディジタルマッチドフィルタによって得られる相互相関関数の一部を説明する図であって、相関のピークが奇数番目のサンプル点にある場合に抜き出した相互相関関数の一部を説明する図である。
【図１７】図６に示すディジタルマッチドフィルタにおけるサイン／コサイン発生器によって発生されてメモリに保持されている位相が０ラジアン〜π／２ラジアンまでのコサイン関数の成分を用いて、任意の位相のサイン関数及び／又はコサイン関数を利用する際の一連の処理を説明するフローチャートである。
【図１８】ＧＰＳ衛星からの信号の構成を説明する図である。
【図１９】従来の拡散符号及びキャリアの同期処理を説明するための図であって、周波数サーチを説明するための図である。
【図２０】ディジタルマッチドフィルタを用いて検出した相関値の時間変化を示す出力波形の例を説明する図である。
【図２１】従来のＧＰＳ受信機に適用されるＦＦＴを利用したディジタルマッチドフィルタの構成を説明するブロック図である。
【符号の説明】
１０ ＧＰＳ受信機、 １１ ＸＯ、 １２ ＴＣＸＯ、 １３ 逓倍／分周器、 １４ アンテナ、 １５ ＬＮＡ、 １６ ＢＰＦ、 １７，２０ 増幅器、 １８ 周波数シンセサイザ、 １９ ミキサ、 ２１，６７，６８，７７，７８，８２，８３ ＬＰＦ、 ２２ Ａ／Ｄ、 ２３ 周波数変換部、 ２４同期捕捉部、 ２５ 同期保持部、 ２６ ＣＰＵ、 ２７ ＲＴＣ、 ２８タイマ、 ２９，１０２，１０５，１１０，１１５，１１８ メモリ、 ３０復調回路、 ５１，５１_１，５１_２，・・・，５１_Ｎ チャンネル回路、 ５２ コントロール・レジスタ、 ６１ コスタスループ、 ６２ ＤＬＬ、 ６３，６５，６６，７３，７４，７５，７６，８０，８１，１１３ 乗算器、 ６４，８７ ＮＣＯ、 ６９，８６ ループフィルタ、 ７０，８５ 位相検出器、 ７１ ２値化回路、 ７２，７９，８４ ２乗和算出回路、 ８８，１０７拡散符号発生器、 １００ ディジタルマッチドフィルタ、 １０１，１２１サンプラ、 １０３，１０８ ＦＦＴ処理部、 １０４，１０９ 負の周波数除去フィルタ、 １０６ 虚数反転フィルタ、 １１１ 補完フィルタ、 １１２ シフタ、 １１４ ＩＦＦＴ処理部、 １１６ ピーク検出器、 １１７ サイン／コサイン発生器、 １２２ ＲＡＭ、 １２３ ＲＡＭ／ＲＯＭ、 １２４ ＤＳＰ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a matched filter device and a correlation detection method for detecting a correlation between a spread code and a spread code generated by itself in order to detect the phase of the spread code in the spread spectrum signal when demodulating the spread spectrum signal, The present invention also relates to a receiving device to which these matched filter device and correlation detection method are applied, which receives a signal from a satellite in a so-called GNSS (Global Navigation Satellites System) and calculates its position and velocity.
[0002]
[Prior art]
In recent years, GNSS systems that measure the position of a moving object on the ground using an artificial satellite are becoming widespread. As this GNSS system, for example, there is a global positioning system (hereinafter referred to as GPS). In this GPS system, a GPS receiver that receives signals from GPS satellites receives signals from at least four GPS satellites, calculates the position of the GPS receiver based on the received signals, and It is a basic function to notify to.
[0003]
In other words, the GPS receiver demodulates the signal from each GPS satellite to obtain the orbit information of each GPS satellite, and based on the orbit and time information of each GPS satellite and the delay time of the received signal, the GPS receiver Is derived by simultaneous equations. In the GPS system, at least four GPS satellites for obtaining received signals are required because there is an error between the internal time due to the clock provided in the GPS receiver and the time due to the atomic clock provided in the GPS satellite. This is because the pseudo distances from at least four GPS satellites are necessary to calculate the four unknown parameters of the three-dimensional position and the accurate time from which the influence of the above is removed.
[0004]
In the GPS system, when a consumer GPS receiver is used, a spread spectrum signal radio wave called a C / A (Clear and Acquisition) code is received from the GPS satellite (Navstar) and positioning calculation is performed. Do.
[0005]
The transmission signal called the L1 band and C / A code has a transmission signal speed, that is, a chip rate of 1.023 MHz, and a pseudo-random noise (PN) having a code length of 1023 such as a so-called Gold code. ) Binary phase shift keying (hereinafter referred to as BPSK modulation method) with respect to a carrier having a frequency of 1575.42 MHz (hereinafter referred to as carrier) using a signal obtained by directly spreading 50 bps data with a sequence spreading code. It is a signal that has been modulated based on. In this case, since the code length is 1023, the C / A code has a spread code of 1023 chips as one cycle, that is, one cycle = 1 millisecond (msec), as shown in the first stage in FIG. Will be repeated.
[0006]
The spreading code of this C / A code is different for each GPS satellite, but which GPS satellite uses which spreading code can be detected in advance by a GPS receiver. Further, the GPS receiver can grasp which GPS satellite can receive a signal at that point and at that point by a navigation message described later. Therefore, for example, in the case of three-dimensional positioning, a GPS receiver receives radio waves from at least four or more GPS satellites that can be acquired at that point and at that time, performs spectrum despreading, and performs positioning calculation Thus, the position of itself is calculated.
[0007]
One bit of the signal data from the GPS satellite is transmitted for 20 cycles of the spread code, that is, in units of 20 milliseconds, as shown in the second stage in the figure. That is, the data transmission rate is 50 bps as described above. Further, 1023 chips for one cycle of the spread code are inverted when the bit is “1” and when it is “0”.
[0008]
Further, the signal from the GPS satellite forms one word with 30 bits, that is, 600 milliseconds, as shown in the third row in FIG. Furthermore, the signal from the GPS satellite forms one subframe in 10 words, that is, 6 seconds, as shown in the fourth row in FIG. In the signal from the GPS satellite, as shown in the fifth row in the figure, a preamble that always has a prescribed bit pattern is added to the first word of one subframe even when data is updated. Inserted, and data is transmitted following this preamble.
[0009]
Furthermore, signals from GPS satellites form 5 subframes, ie, 1 frame in 30 seconds. And in the signal from a GPS satellite, the navigation message mentioned above is transmitted in the data unit of this 1 frame.
[0010]
The first three subframes of the data of one frame are information specific to GPS satellites called ephemeris information. The ephemeris information includes a parameter for obtaining the orbit of the GPS satellite and a transmission time of the signal from the GPS satellite.
[0011]
All GPS satellites use the common time information by providing an atomic clock, and the transmission time of the signal from the GPS satellite included in the ephemeris information is in units of one second of the atomic clock. Further, the spread codes of GPS satellites are generated in synchronization with the atomic clock.
[0012]
The trajectory information included in the ephemeris information is updated every few hours, but is the same information until the update is performed. Therefore, the GPS receiver can use the same orbit information accurately for several hours by holding the orbit information included in the ephemeris information in the memory. Note that the signal transmission time from the GPS satellite is updated every 6 seconds as TOW (Time Of Week) information.
[0013]
On the other hand, the navigation messages of the remaining two subframes in one frame of data are information transmitted in common from all GPS satellites called almanac information. This almanac information is required for 25 frames in order to acquire all information, and is composed of approximate position information of each GPS satellite, information indicating which GPS satellite can be used, and the like. This almanac information is updated every few days, but is the same information until the update is performed. Therefore, the GPS receiver can use the same information accurately for several days by holding the almanac information in the memory. However, the GPS receiver can use the same almanac information for several months, although the accuracy is somewhat reduced.
[0014]
In order to receive the signal from the GPS satellite and obtain the above-mentioned data, the GPS receiver first removes the carrier and then uses the same spreading code as the C / A code used by the GPS satellite to be received. Using the signal from the GPS satellite, the signal from the GPS satellite is captured by phase-synchronizing the C / A code and the spectrum is despread. When the GPS receiver performs spectrum despreading in phase synchronization with the C / A code, bits are detected, and a navigation message including time information and the like can be acquired based on a signal from a GPS satellite. Become.
[0015]
The GPS receiver captures a signal from a GPS satellite by a phase-locked search of a C / A code. As this phase-locked search, a correlation between a spread code generated by itself and a spread code of a received signal from a GPS satellite is performed. For example, when the correlation value of the correlation detection result is larger than a predetermined value, it is determined that the two are synchronized. If the GPS receiver determines that synchronization is not achieved, it uses some synchronization technique to control the phase of the spreading code generated by itself and synchronize it with the spreading code of the received signal. Yes.
[0016]
By the way, as described above, the signal from the GPS satellite is a signal obtained by modulating the carrier based on the BPSK modulation method with the signal obtained by spreading the data with the spreading code. Therefore, in order to receive a signal from a GPS satellite, the GPS receiver needs to synchronize not only the spreading code but also the carrier and data, but cannot synchronize the spreading code and the carrier independently.
[0017]
The GPS receiver usually converts the received signal into an IF signal by converting the carrier frequency of the received signal into an intermediate frequency (hereinafter referred to as IF) within several MHz, and the IF signal is used to convert the received signal into the IF signal. Perform the synchronization detection process. The carrier in the IF signal (hereinafter referred to as IF carrier) mainly includes a frequency error due to Doppler shift according to the moving speed of the GPS satellite, and an internal part of the GPS receiver when the received signal is converted into an IF signal. The frequency error of the local oscillator generated by
[0018]
Therefore, in the GPS receiver, since the IF carrier frequency is unknown due to these frequency error factors, it is necessary to search for the frequency. In addition, since the synchronization point (synchronization phase) within one cycle of the spread code is unknown due to dependence on the positional relationship between the GPS receiver and the GPS satellite, the GPS receiver described above Thus, some kind of synchronization method is required.
[0019]
A conventional GPS receiver uses a synchronization method that combines a frequency search for a carrier, synchronization acquisition by a sliding correlator, and synchronization maintenance by a DLL (Delay Locked Loop) and a Costas loop. Hereinafter, this synchronization method will be described.
[0020]
As a clock for driving a spread code generator of a GPS receiver, a clock obtained by dividing a reference frequency oscillator prepared in the GPS receiver is generally used. A high-precision crystal oscillator is used as the reference frequency oscillator, and the GPS receiver uses a local oscillation signal used to convert a received signal from a GPS satellite into an IF signal based on the output of the reference frequency oscillator. Generate.
[0021]
Here, FIG. 19 shows the processing contents for the frequency search. The GPS receiver performs a phase synchronization search for a spread code when the frequency of the clock signal that drives the spread code generator is a certain frequency f1. That is, the GPS receiver detects the correlation between the received signal from the GPS satellite and the spreading code at each chip phase by sequentially shifting the phase of the spreading code by one chip, and detects the correlation peak. Thus, a phase that can be synchronized is detected. In addition, when the frequency of the clock signal is f1, the GPS receiver changes the frequency division ratio with respect to the reference frequency oscillator, for example, if there is no phase that is synchronized in all the phase searches for 1023 chips. The frequency of the signal is changed to another frequency f2, and the phase search for 1023 chips is similarly performed. The GPS receiver implements a frequency search by repeating such an operation by changing the frequency of the clock signal stepwise.
[0022]
When the GPS receiver detects the frequency of the clock signal that can be synchronized by performing such a frequency search, the GPS receiver performs phase synchronization of the final spread code at the frequency of the clock signal. As a result, the GPS receiver can capture a signal from a GPS satellite even when there is a deviation in the oscillation frequency of the crystal oscillator.
[0023]
However, such a conventional synchronization method is not suitable for high-speed synchronization in principle. In the GPS receiver, if it takes time to synchronize the spread code and the IF carrier, the reaction becomes slow and inconvenience occurs in use. Therefore, in an actual GPS receiver, in order to compensate for this disadvantage, the time until synchronization acquisition is shortened by parallel processing by increasing the number of channels.
[0024]
On the other hand, as a technique for performing high-speed acquisition of a spread spectrum signal instead of the above-described technique using sliding correlation, a matched filter is used. The matched filter can be digitally realized by a so-called transversal filter. In addition, as a matched filter, a spread code is obtained by a digital matched filter using a fast Fourier transform (hereinafter referred to as FFT) due to an improvement in hardware capability represented by a recent DSP (Digital Signal Processor). A technique for performing high-speed synchronization is realized. The latter is based on a correlation calculation speed-up method that has been known for a long time.
[0025]
By using these matched filters, the GPS receiver detects a correlation peak, for example, as shown in FIG. 20 for one period of the output waveform when there is a correlation. The position of this peak indicates the beginning of the spread code. By detecting this peak, the GPS receiver can acquire synchronization, that is, detect the phase of the spread code in the received signal. Further, the GPS receiver can detect the IF carrier frequency together with the phase of the spread code by using the above-described digital matched filter using FFT and performing an operation in the frequency domain of the FFT. Then, the GPS receiver converts the phase of the spread code into a pseudorange, and can calculate the position of the GPS receiver when at least four GPS satellites are detected. Based on this, the speed of the GPS receiver can be calculated.
[0026]
[Problems to be solved by the invention]
By the way, in the GPS receiver, as described above, a digital matched filter using FFT may be used to perform synchronization acquisition.
[0027]
Specifically, as shown in FIG. 21, the digital matched filter 200 includes an antenna 301 that receives an RF signal transmitted from a GPS satellite and an IF signal obtained by a frequency converter 302 that converts the RF signal into an IF signal. Are sampled by a sampler 201 that samples an input signal at a predetermined sampling frequency. The digital matched filter 200 includes a memory 202 that buffers the IF signal sampled by the sampler 201, an FFT processing unit 203 that reads the IF signal buffered by the memory 202 and performs FFT processing, and the FFT processing unit 203. A memory 204 for buffering the frequency domain signal obtained by performing FFT processing in accordance with the above, an imaginary inversion filter 205 for converting the frequency domain signal buffered by the memory 204 into a complex conjugate signal, and a GPS satellite A spreading code generator 206 that generates the same spreading code as the spreading code in the RF signal from the signal, an FFT processing unit 207 that performs FFT processing on the spreading code generated by the spreading code generator 206, and the FFT processing unit FFT by 207 A memory 208 for buffering the frequency domain signal obtained by the processing, a shifter 209 for shifting the frequency domain signal buffered by the memory 208 on the frequency domain, and a frequency passed by the imaginary inversion filter 205 A multiplier 210 that multiplies the domain signal and the frequency domain signal shifted by the shifter 209, and an inverse fast Fourier transform (hereinafter referred to as IFFT) process on the frequency domain signal multiplied by the multiplier 210. IFFT processing unit 211 that performs IFFT processing, a memory 212 that buffers a cross-correlation function that is a time-domain signal obtained by performing IFFT processing by the IFFT processing unit 211, and a cross-correlation function buffered by the memory 212 RF signal from GPS satellite based on And a peak detector 213 for detecting a peak of the correlation between the definitive spreading code and the spread code generated by the spread code generator 206.
[0028]
In addition, the digital matched filter 200 repeatedly uses a sine function and / or a cosine function when performing calculations by the FFT processing units 203 and 207 and / or the IFFT processing unit 211, so that the calculation speed of the FFT processing and / or IFFT processing is high. And a sine / cosine generator 214 for generating a sine function and / or cosine function, and a memory 215 for holding the sine function and / or cosine function generated by the sine / cosine generator 214. As a pre-process, a sine calculation and / or cosine calculation is performed in advance by the sine / cosine generator 214, and the result is stored in the memory 215, and arbitrarily selected by the FFT processing units 203 and 207 and / or the IFFT processing unit 211. It is configured to be readable.
[0029]
Such a digital matched filter 200 actually includes FFT processing sections 203 and 207, an imaginary inversion filter 205, a spread code generator 206, a shifter 209, a multiplier 210, an IFFT processing section 211, a peak detector 213, and a sine Each part of the cosine generator 214 is implemented as software executed by the DSP.
[0030]
In the digital matched filter 200, for convenience of explanation, for example, if the carrier of the IF signal supplied from the frequency converter 302 is 1 MHz, the sampler 201 samples the IF signal at a sampling frequency of 4.096 MHz. Here, in the GPS receiver, since the cycle of the spread code is 1 millisecond, the digital matched filter 200 performs data processing every 1 millisecond. In this case, in the digital matched filter 200, the input to the FFT processing unit 203 is 4096 points, and in the case of 32-bit operation, the buffer capacity of the memory 204 is 32k in order to buffer the frequency domain signal obtained by the FFT processing unit 203. Bytes are required.
[0031]
Further, in the digital matched filter 200, in order to hold all the sine functions and / or cosine functions used in the calculation by the FFT processing units 203 and 207 and / or the IFFT processing unit 211, the capacity of the memory 215 is set. However, 32k bytes are required.
[0032]
Further, in the digital matched filter 200, since the IF signal is sampled at 4.096 MHz, the spread code generated by the spread code generator 206 for obtaining the cross-correlation function of the IF signal needs to have the same resolution. It is. Accordingly, in the digital matched filter 200, the input to the FFT processing unit 207 is also 1 millisecond data consisting of 4096 points, as in the FFT processing unit 203, and the frequency domain signal obtained by the FFT processing unit 207 is buffered. Similarly to the memory 204, the capacity of the memory 208 to be ringed is 32 kbytes.
[0033]
Furthermore, in the digital matched filter 200, either the frequency domain signal buffered by the memory 204 or the frequency domain signal buffered by the memory 208 is passed through the imaginary inversion filter 205 to be complex conjugate. And the other is shifted in the frequency domain using the shifter 209 to make the carriers equal to each other. In the figure, as described above, the frequency domain signal buffered by the memory 204 is passed through the imaginary inversion filter 205, and the frequency domain signal buffered by the memory 208 is shifted by the shifter 209. Here, when the frequency domain signal buffered by the memory 204 obtained by performing the FFT process on the IF signal is shifted, it is shifted by 1 MHz. In the digital matched filter 200, the IFFT processing unit 211 applies the frequency domain signal obtained by multiplying the frequency domain signal passed by the imaginary inversion filter 205 and the frequency domain signal shifted by the shifter 209 by the multiplier 210. By performing the IFFT process, the cross-correlation function between the IF signal and the spread code is obtained and held in the memory 212. Therefore, in the digital matched filter 200, the capacity of the memory 212 for buffering the frequency domain signal obtained by the IFFT processing unit 211 is also required to be 32 kbytes, similarly to the memories 204 and 208. In the digital matched filter 200, the peak of the correlation is detected by the peak detector 213 from the signal buffered by the memory 212.
[0034]
Thus, in the digital matched filter 200, the capacity of the memories 204, 208, 212, and 215 requires 32 kbytes, and requires a total capacity of 128 kbytes. In the digital matched filter 200, the FFT processing units 203 and 207, the IFFT processing unit 211, the peak detector 213, and the sine / signature processing unit process input / output signals for the memories 204, 208, 212, and 215, respectively. Each cosine generator 214 needs to perform 4096 operations.
[0035]
These values are values when processing is performed on 1 millisecond data, and as the data length increases, the capacity of the memory and the amount of computation of each unit also increase.
[0036]
In the GPS receiver, since the memory capacity greatly affects the chip area when the integrated circuit is formed, the large memory capacity leads to an increase in size and cost of the GPS receiver. It is not preferable.
[0037]
In addition, while the ability of hardware such as a DSP has been improved, as the amount of data handled increases, the computation time also increases. Therefore, in the GPS receiver, as the calculation time becomes longer, the power consumption increases, and the time until the user presents his / her position and speed as the final calculation result becomes longer, which impairs convenience. Invite you.
[0038]
This problem is not limited to the GPS receiver, but is common to all mobile communications employing a spread spectrum modulation method similar to the GPS signal.
[0039]
The present invention has been made in view of such circumstances, and a matched filter device and a correlation detection method that can reduce the capacity of the memory to be mounted, reduce the size and cost, and reduce the calculation time. The purpose is to provide. It is another object of the present invention to provide a receiving apparatus that can reduce the calculation time while reducing the size and cost by applying these matched filter apparatus and correlation detection method.
[0040]
[Means for Solving the Problems]
The matched filter device according to the present invention that achieves the above-described object is a matched filter device that detects the correlation between a spread code and a spread code generated by itself in order to detect the phase of the spread code in the input spread spectrum signal. The first fast Fourier transform processing means for performing the fast Fourier transform processing on the input data obtained by sampling the spectrum spread signal at a predetermined sampling frequency, and the first fast Fourier transform processing means. Negative frequency removing means for removing negative frequency components from the frequency domain signal obtained by performing Fourier transform processing, and buffering frequency domain signals from which negative frequency components have been removed by this negative frequency removing means First storage means for performing the same spreading code as the spreading code in the spread spectrum signal Generated spreading code generating means, second fast Fourier transform processing means for performing fast Fourier transform processing on the spreading code generated by the spreading code generating means, and at least the second fast Fourier transform processing means. And a second storage means for buffering a frequency domain signal obtained by performing the Fourier transform process.
[0041]
Such a matched filter device according to the present invention removes the negative frequency component from the frequency domain signal obtained by performing the fast Fourier transform processing by the first fast Fourier transform processing means by the negative frequency removing means. The obtained frequency domain signal is stored in the first storage means, and the frequency domain signal obtained by performing the fast Fourier transform processing by at least the second fast Fourier transform processing means is stored in the second storage means. Let
[0042]
Further, in the matched filter device according to the present invention, the second fast Fourier transform processing means includes a spreading code generated by the spreading code generating means at a frequency twice the chip rate of the spreading code in the spread spectrum signal. It is characterized by being sampled and input.
[0043]
In such a matched filter device according to the present invention, a spreading code consisting of 1/2 the number of data of the spread spectrum signal subjected to the fast Fourier transform processing by the first fast Fourier transform processing means, Fast Fourier transform processing is performed by the second fast Fourier transform processing means.
[0044]
Further, the matched filter device according to the present invention removes the negative frequency component from the frequency domain signal obtained by performing the fast Fourier transform processing by the second fast Fourier transform processing means. And the second storage means buffers the frequency domain signal from which the negative frequency component has been removed by another negative frequency removal means.
[0045]
In such a matched filter device according to the present invention, the negative frequency component of the frequency domain signal obtained by performing the fast Fourier transform processing by the second fast Fourier transform processing means is removed by other negative frequency removing means. The frequency domain signal obtained by the removal is stored in the second storage means.
[0046]
Furthermore, the matched filter device according to the present invention includes a complementary means for restoring the negative frequency component removed by the other negative frequency removing means for the frequency domain signal buffered by the second storage means. It is characterized by providing.
[0047]
Such a matched filter device according to the present invention restores the negative frequency component by the complementing means from the frequency domain signal consisting only of the positive frequency component from which the negative frequency component has been removed by the other negative frequency removing means. .
[0048]
Further, the matched filter device according to the present invention includes a multiplying unit that multiplies at least the frequency domain signal buffered by the first storage unit and the frequency domain signal buffered by the second storage unit, Inverse fast Fourier transform processing means for performing inverse fast Fourier transform processing on the frequency domain signal multiplied by the multiplication means, and a cross-correlation function obtained by applying inverse fast Fourier transform processing by the inverse fast Fourier transform processing means And a third storage means for buffering.
[0049]
Such a matched filter device according to the present invention stores the cross-correlation function obtained by the inverse fast Fourier transform processing by the inverse fast Fourier transform processing means in the third storage means.
[0050]
Further, in the matched filter device according to the present invention, the inverse fast Fourier transform processing means performs an inverse fast Fourier transform process only on a positive frequency component of the frequency domain signal obtained by the multiplication means. Yes.
[0051]
Such a matched filter device according to the present invention performs inverse fast Fourier transform processing by the inverse fast Fourier transform processing means on the frequency domain signal consisting of half the number of data among the frequency domain signals obtained by the multiplication means. Apply.
[0052]
Furthermore, the matched filter device according to the present invention includes a sine / cosine generating means for generating a sine function or a cosine function, and a sine function or cosine function generated by the sine / cosine generating means. And a fourth storage means that is held so as to be readable by each of the transform processing means, the second fast Fourier transform processing means, and / or the inverse fast Fourier transform processing means.
[0053]
In addition, the matched filter device according to the present invention includes a trigonometric function generation unit that generates a calculation formula including a plurality of patterns using a trigonometric function based on the sine function or the cosine function held in the fourth storage unit. Storage means for holding a calculation formula composed of a plurality of patterns generated by the trigonometric function generating means, wherein the sine / cosine generating means generates only a part of the components of the sine function or cosine function to generate a fourth component. The first fast Fourier transform processing means, the second fast Fourier transform processing means, and / or the inverse fast Fourier transform processing means are respectively stored in the storage means according to the phase of the required function. Use the sine function and / or cosine function of any phase by switching the calculation formula consisting of multiple patterns stored in It is characterized.
[0054]
In such a matched filter device according to the present invention, only the sine function or the partial component of the cosine function is generated by the sine / cosine generation means and is stored in the fourth storage means.
[0055]
In addition, the correlation detection method according to the present invention that achieves the above-described object is a correlation that detects the correlation between a spread code and a spread code generated by itself in order to detect the phase of the spread code in the input spread spectrum signal. A detection method obtained by performing a fast Fourier transform process on input data obtained by sampling a spread spectrum signal at a predetermined sampling frequency, and performing a fast Fourier transform process on the input data. Removing the negative frequency component from the frequency domain signal; buffering the frequency domain signal from which the negative frequency component has been removed to the first storage means; and the same spreading code as the spreading code in the spread spectrum signal. And a step of performing a fast Fourier transform process on the generated spreading code, and at least generated And a step of buffering the frequency domain signal obtained by performing the fast Fourier transform process on the spread code in the second storage means.
[0056]
Such a correlation detection method according to the present invention removes negative frequency components from the frequency domain signal obtained by performing fast Fourier transform processing on the input data, and obtains the obtained frequency domain signal as the first frequency domain signal. And at least a frequency domain signal obtained by performing fast Fourier transform processing on the generated spreading code is stored in the second storage unit.
[0057]
Furthermore, a receiving apparatus according to the present invention that achieves the above-described object is a receiving apparatus that receives a signal from a satellite and calculates its position and velocity, and a receiving means for receiving the signal from the satellite, Frequency conversion means for converting the frequency of the received signal received by the reception means to a predetermined intermediate frequency, and synchronization acquisition for detecting the phase of the spread code in the intermediate frequency signal obtained by the frequency conversion means, and carrier frequency in the intermediate frequency signal Synchronization acquisition means for detecting the signal, and the phase of the spread code detected by the synchronization acquisition means and the carrier frequency detected by the synchronization acquisition means for a plurality of channels provided independently for a plurality of satellites. Each satellite is assigned and set for each, and the spread code phase and carrier frequency are set as initial values. A synchronization holding means for demodulating a message included in the intermediate frequency signal and detecting a phase of the spreading code in the intermediate frequency signal that is a spread spectrum signal. The synchronization acquisition means for detecting the correlation with the spreading code generated by itself is a first fast Fourier transform processing means for performing fast Fourier transform processing on data inputted by sampling the intermediate frequency signal at a predetermined sampling frequency. A negative frequency removing means for removing a negative frequency component from the frequency domain signal obtained by performing the fast Fourier transform processing by the first fast Fourier transform processing means, and a negative frequency removing means by the negative frequency removing means. First storage means for buffering the frequency domain signal from which the frequency component is removed, and the intermediate frequency signal Spreading code generating means for generating the same spreading code as the spreading code, second fast Fourier transform processing means for performing fast Fourier transform processing on the spreading code generated by the spreading code generating means, and at least the second And a second storage means for buffering a frequency domain signal obtained by performing the fast Fourier transform processing by the fast Fourier transform processing means.
[0058]
Such a receiving apparatus according to the present invention includes a negative frequency component that removes a negative frequency component from the frequency domain signal obtained by performing the fast Fourier transform process by the first fast Fourier transform process unit in the synchronization acquisition unit. And the obtained frequency domain signal is stored in the first storage means and at least the frequency domain signal obtained by performing the fast Fourier transform processing by the second fast Fourier transform processing means is stored in the second storage. Memorize in means.
[0059]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.
[0060]
In this embodiment, a global positioning system (hereinafter referred to as GPS), which is a kind of GNSS (Global Navigation Satellites System) system that measures the position of a moving body on the ground using an artificial satellite. This is a GPS receiver that receives signals from at least four GPS satellites and calculates its position based on the received signals. This GPS receiver receives a spread spectrum signal radio wave called a C1 / A (Clear and Acquisition) code as an L1 band as a reception signal, and performs synchronization acquisition of the spread spectrum signal using a digital matched filter. In addition, it is possible to reduce the calculation time while reducing the capacity of the mounted memory to reduce the size and cost, and to accurately detect the correlation peak.
[0061]
As shown in FIG. 1, the GPS receiver 10 has a pseudo-random noise (PN) sequence spread code generated by itself when the received signal is demodulated and the spread in the received signal. By separating the function for capturing the synchronization with the code and the function for maintaining the synchronization between the spread code and the carrier wave (hereinafter referred to as carrier), speeding up the synchronization acquisition with a small circuit scale It is something that can be done.
[0062]
In the following, first, the overall configuration of the GPS receiver 10 in which the synchronization acquisition function and the synchronization holding function are separated will be described, and then the processing by the synchronization acquisition unit 24 and the synchronization holding unit 25 will be described in detail. The specific configuration of the synchronization capturing unit 24 will be described in detail.
[0063]
First, the overall configuration of the GPS receiver will be described.
[0064]
As shown in the figure, the GPS receiver 10 includes a crystal oscillator (X'tal Oscillator; hereinafter referred to as XO) 11 that generates an oscillation signal D1 having a predetermined oscillation frequency, and a predetermined oscillation different from the XO11. Frequency F_OSCA temperature-compensated crystal oscillator (Temperature Compensated X'tal Oscillator; hereinafter referred to as TCXO) 12 that generates an oscillation signal D2 having the following characteristics, and the oscillation signal D2 supplied from the TCXO 12 is multiplied and / or divided ( and a multiplier / divider 13 for dividing.
[0065]
The XO 11 generates an oscillation signal D1 having a predetermined oscillation frequency of about 32.768 kHz, for example. The XO 11 supplies the generated oscillation signal D1 to an RTC (Real Time Clock) 27 described later.
[0066]
The TCXO 12 is different from the XO 11, for example, a predetermined oscillation frequency F of about 18.414 MHz._OSCAn oscillation signal D2 having the following is generated. The TCXO 12 supplies the generated oscillation signal D2 to the multiplier / divider 13 and a frequency synthesizer 18 described later.
[0067]
The multiplier / divider 13 multiplies the oscillation signal D2 supplied from the TCXO 12 by a predetermined multiplication factor based on a control signal D3 supplied from a CPU (Central Processing Unit) 26, which will be described later, and / or Divide by the division ratio. The frequency multiplier / frequency divider 13 supplies the multiplied and / or frequency-divided oscillation signal D4 to a synchronization acquisition unit 24 described later, a synchronization holding unit 25 described later, a CPU 26, a timer 28 described later, and a memory 29 described later.
[0068]
The GPS receiver 10 also includes an antenna 14 that receives an RF (Radio Frequency) signal transmitted from a GPS satellite, and a low noise amplifier (Low Noise Amplifier) that amplifies the received RF signal D5 received by the antenna 14. (Hereinafter referred to as LNA) 15, a band-pass filter (hereinafter referred to as BPF) 16 that passes a predetermined frequency band component of the amplified RF signal D 6 amplified by the LNA 15, and the BPF 16 An amplifier 17 for further amplifying the amplified RF signal D7 and a predetermined frequency F based on the oscillation signal D2 supplied from the TCXO 12_LOA frequency synthesizer 18 that generates a local oscillation signal D10 having a predetermined frequency F amplified by an amplifier 17_RFA mixer 19 that multiplies the amplified RF signal D8 having a local oscillation signal D10 supplied from the frequency synthesizer 18 by the amplified RF signal D8, and a predetermined frequency F that is downconverted by being multiplied by the mixer 19._IFAnd an amplifier 20 that amplifies an intermediate frequency (hereinafter referred to as IF) signal D11 and a low-pass filter (Low) that passes a predetermined frequency band component of the amplified IF signal D12 amplified by the amplifier 20. Pass Filter (hereinafter referred to as LPF) 21 and an analog / digital converter (Analog / Digital Converter; hereinafter referred to as A) for converting the analog amplified IF signal D13 passed by the LPF 21 into a digital amplified IF signal D14. / D.) 22.
[0069]
The antenna 14 receives an RF signal in which a carrier having a frequency of 1575.42 MHz transmitted from a GPS satellite is spread. The reception RF signal D5 received by the antenna 14 is supplied to the LNA 15.
[0070]
The LNA 15 amplifies the reception RF signal D5 received by the antenna 14. The LNA 15 supplies the amplified RF signal D6 that has been amplified to the BPF 16.
[0071]
The BPF 16 is a so-called SAW (Surface Acoustic Wave) filter, and allows a predetermined frequency band component of the amplified RF signal D6 amplified by the LNA 15 to pass therethrough. The amplified RF signal D7 passed by the BPF 16 is supplied to the amplifier 17.
[0072]
The amplifier 17 further amplifies the amplified RF signal D7 passed by the BPF 16. The amplifier 17 has an amplified predetermined frequency F_RFThat is, the amplified RF signal D8 of 1575.42 MHz is supplied to the mixer 19.
[0073]
The frequency synthesizer 18 has a predetermined frequency F based on the oscillation signal D2 supplied from the TCXO 12 under the control of the control signal D9 supplied from the CPU 26._LOA local oscillation signal D10 having the following is generated. The frequency synthesizer 18 supplies the generated local oscillation signal D10 to the mixer 19.
[0074]
The mixer 19 has a predetermined frequency F amplified by the amplifier 17._RFIs multiplied by the local oscillation signal D10 supplied from the frequency synthesizer 18 to downconvert the amplified RF signal D8, for example, a predetermined frequency F of about 1.023 MHz._IFIF signal D11 is generated. The IF signal D11 generated by the mixer 19 is supplied to the amplifier 20.
[0075]
The amplifier 20 amplifies the IF signal D11 down-converted by the mixer 19. The amplifier 20 supplies the amplified amplified IF signal D12 to the LPF 21.
[0076]
The LPF 21 passes the low frequency component of the amplified IF signal D12 amplified by the amplifier 20 at a frequency lower than a predetermined frequency. The amplified IF signal D13 passed by the LPF 21 is supplied to the A / D 22.
[0077]
The A / D 22 converts the analog amplified IF signal D13 passed by the LPF 21 into a digital amplified IF signal D14. The amplified IF signal D14 converted by the A / D 22 is supplied to the synchronization acquisition unit 24 and the synchronization holding unit 25.
[0078]
In the GPS receiver 10, among these units, the LNA 15, BPF 16, amplifiers 17 and 20, frequency synthesizer 18, mixer 19, LPF 21, and A / D 22 are as high as 1575.42 MHz received by the antenna 14. The received RF signal D5 having a frequency is set to a low frequency F of, for example, about 1.023 MHz so that digital signal processing can be easily performed._IFIs configured as a frequency conversion unit 23 that down-converts the amplified IF signal D14.
[0079]
Further, the GPS receiver 10 includes a synchronization acquisition unit 24 that performs synchronization acquisition of the spreading code generated by itself and the spreading code in the amplified IF signal D14 supplied from the A / D 22 and detection of the carrier frequency in the amplified IF signal D14; , A synchronization holding unit 25 for holding the synchronization between the spread code and the carrier in the amplified IF signal D14 supplied from the A / D 22 and demodulating the message, a CPU 26 for performing various arithmetic processes by comprehensively controlling each unit, and the XO 11 RTC 27 for measuring time based on the oscillation signal D1 supplied from, a timer 28 as an internal clock of the CPU 26, and a memory 29 such as a RAM (Random Access Memory) and a ROM (Read Only Memory).
[0080]
Although the details will be described later, the synchronization acquisition unit 24 is supplied from the A / D 22 based on the multiplied and / or divided oscillation signal D4 supplied from the multiplier / divider 13 under the control of the CPU 26. The synchronous acquisition of the spread code in the amplified IF signal D14 is performed, and the carrier frequency in the amplified IF signal D14 is detected. At this time, the synchronization acquisition unit 24 performs synchronization acquisition with coarse accuracy, as will be described later. The synchronization acquisition unit 24 supplies the satellite number for identifying the detected GPS satellite, the phase of the spreading code, and the carrier frequency to the synchronization holding unit 25 and the CPU 26.
[0081]
Although the details will be described later, the synchronization holding unit 25 is supplied from the A / D 22 based on the multiplied and / or divided oscillation signal D4 supplied from the multiplier / divider 13 under the control of the CPU 26. In addition to maintaining synchronization between the spread code and the carrier in the amplified IF signal D14, the navigation message included in the amplified IF signal D14 is demodulated. At this time, as will be described later, the synchronization holding unit 25 starts the operation using the satellite number, the phase of the spread code, and the carrier frequency supplied from the synchronization acquisition unit 24 as initial values. The synchronization holding unit 25 performs synchronization holding on the amplified IF signals D14 from a plurality of GPS satellites in parallel, and supplies the detected spreading code phase, carrier frequency, and navigation message to the CPU 26.
[0082]
The CPU 26 acquires the phase of the spread code, the carrier frequency, and the navigation message supplied from the synchronization holding unit 25, calculates the position and speed of the GPS receiver 10 based on these various information, and also uses the navigation message. Based on the accurate time information of the GPS satellites obtained from the above, various GPS-related arithmetic processes such as correcting the time information of the GPS receiver 10 are performed. In addition, the CPU 26 performs overall control related to each part and various peripherals of the GPS receiver 10 and input / output with the outside.
[0083]
The RTC 27 measures time based on the oscillation signal D1 supplied from the XO 11. The time information measured by the RTC 27 is substituted until the accurate time information of the GPS satellite is obtained, and the CPU 26 that has obtained the accurate time information of the GPS satellite controls the XO 11. Corrected as appropriate.
[0084]
The timer 28 functions as an internal clock of the CPU 26, and is used for generation of various timing signals necessary for the operation of each unit and time reference. For example, in the GPS receiver 10, the timer 28 refers to the timing at which the synchronization holding unit 25 starts the operation of a spread code generator, which will be described later, in accordance with the phase of the spread code that the synchronization acquisition unit 24 has acquired synchronization.
[0085]
The memory 29 includes a RAM, a ROM, and the like. In the memory 29, a RAM is used as a work area when performing various processes by the CPU 26 and the like, and when buffering various input data and holding intermediate data and calculation result data generated in the calculation process. Also, a RAM is used. In the memory 29, a ROM is used as means for storing various programs, fixed data, and the like.
[0086]
In the GPS receiver 10, the synchronization acquisition unit 24, the synchronization holding unit 25, the CPU 26, the RTC 27, the timer 28, and the memory 29 are configured as a baseband processing unit.
[0087]
In the GPS receiver 10 including such units, at least each unit excluding the XO 11, the TCXO 12, the antenna 14, the LNA 15, and the BPF 16 can be configured as a demodulating circuit 30 that is an integrated circuit.
[0088]
The GPS receiver 10 receives RF signals from at least four or more GPS satellites, converts the RF signals into IF signals by the frequency converter 23, and then performs synchronization acquisition and carrier of spreading codes by the synchronization acquisition unit 24. The frequency is detected, and the synchronization holding unit 25 holds the synchronization between the spread code and the carrier and demodulates the navigation message. Then, the GPS receiver 10 calculates the position and velocity of the GPS receiver 10 by the CPU 26 based on the phase of the spread code, the carrier frequency, and the navigation message.
[0089]
In the following, processing by the synchronization acquisition unit 24 and the synchronization holding unit 25 in the GPS receiver 10 will be described in detail. As described above, the GPS receiver 10 is obtained by separating the synchronization acquisition function and the synchronization holding function into the synchronization acquisition unit 24 and the synchronization holding unit 25. Here, the reason why the functions are separated in this way will also be described.
[0090]
The synchronization acquisition unit 24 uses a matched filter to perform synchronization acquisition of the spread code at high speed. Specifically, the synchronization acquisition unit 24 can use a digital matched filter using a fast Fourier transform (hereinafter referred to as FFT) as a matched filter, which will be described in detail later. This digital matched filter is actually implemented as software in which processing such as FFT processing and peak detection is executed by a DSP (Digital Signal Processor).
[0091]
The synchronization acquisition unit 24 is configured as a digital matched filter, thereby detecting a correlation peak in a phase synchronized with the spreading code and determining a synchronization point of the spreading code. The synchronization acquisition unit 24 samples, for example, a 1.023 MHz IF signal at 4.096 MHz, and performs an operation equivalent to a digital matched filter by a DSP, so that the synchronization acquisition of the spread code, that is, the spread code of the IF signal is performed. Phase detection can be performed with an accuracy of 1/4 chip. In addition, the synchronization acquisition unit 24 assumes that the capacity of the RAM for buffering the input IF signal is 16 milliseconds, and performs an operation in the frequency domain of the FFT by the DSP to 1/16 kHz. The carrier frequency (hereinafter referred to as IF carrier) frequency in the IF signal can be detected with an accuracy of (± 1/32 kHz). Since the IF signal stored in the RAM includes signals from a plurality of GPS satellites, the synchronization acquisition unit 24 detects a plurality of GPS satellites by calculating the correlation with the spreading code of each GPS satellite. can do.
[0092]
The GPS receiver 10 can calculate the position and velocity of the GPS receiver 10 based on the phase of the spreading code and the carrier frequency for at least four or more GPS satellites detected by the synchronization acquisition unit 24. .
[0093]
However, in the GPS receiver 10, the position and speed of the GPS receiver 10 obtained based on the above-described 1/4 chip as the phase detection accuracy of the spread code and 1/16 kHz as the detection accuracy of the carrier frequency. The calculation result of is difficult to say with sufficient accuracy. In the GPS receiver 10, in order to improve accuracy, it is necessary to increase the sampling frequency of the IF signal and increase the time length for storing the IF signal. It is assumed that the memory capacity increases and the processing time until the phase of the spread code and the carrier frequency are detected becomes long. Further, in the GPS receiver 10, if the synchronization acquisition unit 24 does not receive a navigation message from the outside, it is necessary to demodulate a navigation message from at least four GPS satellites every 20 milliseconds. The DSP always needs to detect synchronization and demodulate navigation messages very quickly. These problems cause an increase in cost and an increase in power consumption due to an increase in the size of hardware.
[0094]
Therefore, in the GPS receiver 10, the synchronization acquisition unit 24 performs synchronization acquisition with coarse accuracy, and the synchronization holding unit 25 performs synchronization holding of a plurality of GPS satellites and demodulation of navigation messages.
[0095]
The synchronization acquisition unit 24 supplies the detected satellite number, the phase of the spread code, and the carrier frequency to the synchronization holding unit 25. On the other hand, the synchronization holding unit 25 starts the operation using the various information supplied from the synchronization capturing unit 24 as initial values. Based on the phase of the spreading code, the synchronization holding unit 25 matches the start timing of the spreading code generated by a DLL (Delay Locked Loop) circuit described later. In addition, the GPS receiver 10 sets what corresponds to the satellite number of the detected GPS satellite as a spreading code to generate. At this time, the GPS receiver 10 is affected by the error of the oscillation frequency of the oscillation signal generated by the Doppler shift and the oscillator such as the TCXO 12, but basically the spreading code is repeated at a cycle of 1 millisecond. Therefore, the start timing of the spread code generated by the DLL circuit may be shifted by an integral multiple of 1 millisecond.
[0096]
Note that the IF carrier frequency includes an error of the TCXO 12 that generates a sampling clock for fetching the IF signal into a memory such as the above-described RAM. Therefore, even if the resolution problem described above is removed, an accurate value, That is, it is not the sum of the carrier frequency and the Doppler shift amount. However, in the GPS receiver 10, when the synchronization acquisition unit 24 and the synchronization holding unit 25 operate with the same oscillator, that is, with a clock having the TCXO 12 as an oscillation source, both have the same frequency error. Therefore, there is no problem for the synchronization holding unit 25 to start the operation using the IF carrier frequency detected by the synchronization acquisition unit 24 as an initial value.
[0097]
Since the synchronization holding unit 25 performs synchronization holding of a plurality of GPS satellites in parallel, as shown in FIG. 2, for example, a plurality of independent channel circuits 51 are provided.₁, 51₂, ..., 51_NHave Channel circuit 51₁, 51₂, ..., 51_NAre respectively assigned to the individual detection results by the synchronization acquisition unit 24 according to the setting of the control register 52.
[0098]
Channel circuit 51₁, 51₂, ..., 51_NAs shown in FIG. 3, each of the basic circuit and the combination of a Costas loop 61 for IF carrier synchronization and a DLL 62 for spreading code synchronization that realizes both synchronization acquisition and synchronization maintenance in a conventional GPS receiver. Is similarly configured.
[0099]
That is, the channel circuit 51₁, 51₂, ..., 51_NAs shown in the figure, the Costas loop 61 has a spread code generator (described later) for the IF signal corresponding to the amplified IF signal D14 obtained by the antenna 14 and the frequency converter 23 described above. (PN Generator; hereinafter referred to as PNG)) A signal obtained by multiplying the multiplier 63 by a spreading code whose phase generated by P is P (Prompt) is input. On the other hand, the channel circuit 51₁, 51₂, ..., 51_N, Each of the DLLs 62 receives an IF signal corresponding to the amplified IF signal D14 obtained by the antenna 14 and the frequency conversion unit 23 described above.
[0100]
In the Costas loop 61, the input signal is multiplied by a sine component (in-phase component) of a reproduction carrier generated by an NCO (Numeric Controlled Oscillator) 64 by a multiplier 65, while being generated by the NCO 64. A multiplier 66 multiplies the cosine component (orthogonal component) of the reproduced carrier. In the Costas loop 61, a predetermined frequency band component of the in-phase component signal obtained by the multiplier 65 is passed by the LPF 67, and this signal is passed through the phase detector 70, the binarization circuit 71, and the square sum calculation circuit 72. To be supplied. On the other hand, in the Costas loop 61, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 66 is passed by the LPF 68, and this signal is supplied to the phase detector 70 and the square sum calculation circuit 72. . In the Costas loop 61, the phase information detected by the phase detector 70 based on the signals output from the LPFs 67 and 68 is supplied to the NCO 64 via the loop filter 69. In the Costas loop 61, the signals output from the LPFs 67 and 68 are supplied to the square sum calculation circuit 72, and the square sum (I) calculated by the square sum calculation circuit 72 is supplied.²+ Q²) Is output as a correlation value (P) for a spreading code whose phase is P. Further, in the Costas loop 61, the signal output from the LPF 67 is supplied to the binarization circuit 71, and information obtained by binarization is output as a navigation message.
[0101]
On the other hand, the DLL 62 multiplies the input IF signal by a spreading code which is E (Early) whose phase generated by the PNG 88 is ahead of P by the multiplier 73 and is generated by the PNG 88. The multiplier 74 multiplies the spread code whose phase is L (Late) delayed from P. In the DLL 62, the signal obtained by the multiplier 73 is multiplied by the sine component of the regenerated carrier generated by the NCO 64 in the Costas loop 61 by the multiplier 75, and the regenerated carrier generated by the NCO 64 is also transmitted. The cosine component is multiplied by the multiplier 76. In the DLL 62, a predetermined frequency band component of the in-phase component signal obtained by the multiplier 75 is passed by the LPF 77, and this signal is supplied to the square sum calculation circuit 79. On the other hand, in the DLL 62, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 76 is passed by the LPF 78, and this signal is supplied to the square sum calculation circuit 79. In the DLL 62, the signal obtained by the multiplier 74 is multiplied by a sine component of the reproduction carrier generated by the NCO 64 in the Costas loop 61 by the multiplier 80, and the reproduction generated by the NCO 64 is also performed. A cosine component of the carrier is multiplied by a multiplier 81. In the DLL 62, a predetermined frequency band component of the in-phase component signal obtained by the multiplier 80 is passed by the LPF 82, and this signal is supplied to the square sum calculation circuit 84. On the other hand, in the DLL 62, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 81 is passed by the LPF 83, and this signal is supplied to the square sum calculation circuit 84.
[0102]
In the DLL 62, signals output from the square sum calculation circuits 79 and 84 are supplied to the phase detector 85, and phase information detected by the phase detector 85 based on these signals passes through the loop filter 86. Then, based on the signal having a predetermined frequency generated by the NCO 87 and generated by the NCO 87, the PNG 88 generates a spreading code of each phase E, P, and L. Furthermore, in the DLL 62, the sum of squares (I²+ Q²) Is output as a correlation value (E) for a spreading code whose phase is E, while the square sum (I) calculated by the square sum calculation circuit 84 is output.²+ Q²) Is output as a correlation value (L) for a spreading code whose phase is L.
[0103]
Thus, a channel circuit 51 configured in the same manner as a circuit in which the Costas loop 61 for IF carrier synchronization and the DLL 62 for spreading code synchronization are combined.₁, 51₂, ..., 51_NIn the synchronization holding unit 25 having the above, the satellite number of the GPS satellite, the phase of the spread code, and the carrier frequency are set as initial values before the operation starts. The initial value is set by communicating directly with the synchronization acquisition unit 24 or via the CPU 26 that controls the synchronization acquisition unit 24 and the synchronization holding unit 25.
[0104]
Such a synchronization holding unit 25 synchronizes with the spread code as follows. That is, as shown in FIG. 4, the synchronization acquisition unit 24 starts a timer at the timing when the IF signal is taken into a memory such as a RAM, and the phase of the spread code with respect to the IF signal stored in the memory by the synchronization acquisition unit 24 When h is detected, the synchronization holding unit 25 receives the value of the phase h, and then starts the spreading code generated by the DLL 62 at the time when the same timer deviates from an integral multiple of 1 millisecond by h. Match the phase to the spreading code of the signal. Note that “PN” in the figure indicates a PN sequence code, that is, a spreading code.
[0105]
Here, in the circuit combining the conventional Costas loop and the DLL, since the phase of the spreading code in the received signal is unknown, the IF carrier frequency generated by the DLL and the period of the spreading code are slightly shifted, and the IF signal In the process of sliding the phase with respect to the spread code, a phase having a significant intensity correlation was detected. Therefore, in the conventional circuit, in the worst case, the detection is performed for the carrier frequency in the range of several kHz and all the phases in the spreading code having a code length of 1023. It took quite a while to establish.
[0106]
On the other hand, in the GPS receiver 10, the synchronization holding unit 25 has basically the same configuration as the conventional circuit, but the initial phase of the spread code received by the synchronization holding unit 25 and the IF carrier frequency are the same. Since the value is slightly deviated from the true value, a phase having a significant intensity correlation always exists in the vicinity of the initial value even if an error is included. Therefore, as in the conventional circuit, the synchronization holding unit 25 first stops the control of the loop filters 69 and 86 in the Costas loop 61 and the DLL 62, and generates signals generated by the NCOs 64 and 87 in the vicinity of the initial values. After searching for a significant intensity correlation while changing, and detecting the correlation, the control is switched to each of the loop filters 69 and 86. Thereby, the synchronization holding unit 25 can establish the synchronization of the phase of the spread code by the DLL 62 and the synchronization of the phase of the carrier by the Costas loop 61 in a very short time, and can continue to maintain the synchronization thereafter. . Since the synchronization holding unit 25 can set the initial value of the frequency of the reproduced carrier generated by the NCO 64 with respect to the IF carrier frequency within an error range of several tens of Hz, the LPF 67, 68, 77, 78, 82, 83, and The bandwidth of the loop filters 69 and 86 can be narrowed from the beginning, and synchronization can be established with a high S / N (Signal to Noise ratio).
[0107]
In the GPS receiver 10, if the synchronization holding unit 25 is operated with a clock of, for example, 1.023 MHz × 16 = 16.668 MHz and the phase of the spread code is detected with a time resolution of 1 / 1.368 MHz in the DLL 62, 1 / The pseudo-range from the phase of the spread code to the GPS satellite can be calculated with an accuracy of 16 chips, and if the NCO 64 in the Costas loop 61 can be controlled in units of 1 Hz, the IF carrier frequency resolution is 1 Hz. The DLL 62 and the Costas loop 61 can maintain synchronization with these precisions.
[0108]
As described above, in the GPS receiver 10, when synchronization is held by the synchronization holding unit 25, the position of the GPS receiver 10 is continuously calculated based on the phase of the spreading code generated by the DLL 62. In addition to being able to output, based on the IF carrier frequency obtained by the Costas loop 61, the speed of the GPS receiver 10 can be continuously calculated and output.
[0109]
As described above, the synchronization holding unit 25 uses the phase of the spread code and the IF carrier frequency passed from the synchronization acquisition unit 24 as initial values, thereby obtaining a significant intensity correlation in the vicinity of these initial values. Search for the phase to be generated. This is one reason that the clock source oscillator mounted on the GPS receiver 10, ie, the TCXO 12, has an error with respect to the nominal frequency. In the GPS receiver 10, when the synchronization acquisition unit 24 is configured using a digital matched filter using FFT, the IF signal is stored in the memory, and then detected by the synchronization holding unit 25 with a delay corresponding to the DSP processing time. Since the result is supplied, the nominal frequency F of the oscillator_OSCThe error with ΔF_OSCAssuming that the processing time of the DSP is T seconds, when the detection result is supplied to the synchronization holding unit 25, T × ΔF_OSC/ F_OSCError occurs. For example, in the GPS receiver 10, T = 3 seconds and ΔF_OSC/ F_OSCIs within the range of ± 3 ppm, an error within ± 9 microseconds = about ± 9 chips occurs. As described above, in the GPS receiver 10, when the DSP processing time is increased, the error increases accordingly.
[0110]
In the GPS receiver 10, the carrier frequency Doppler shift caused by the movement of the GPS satellite and the GPS receiver 10 also causes an error. In the GPS receiver 10, the carrier frequency, that is, 1575.42 MHz is set to F._RFAnd the Doppler shift of the received signal is ΔF_DThen, the period of the spread code, that is, 1 millisecond is approximately (1-ΔF) by Doppler shift._D/ F_RFFor example, when a Doppler shift in the range of +5 to -5 kHz occurs, an error of about -9.5 to 9.5 microseconds = about -9.5 to 9.5 chips in 3 seconds. Occurs.
[0111]
These two examples are values that are relatively close to reality. In the GPS receiver 10, when both the error of the oscillator and the Doppler shift are combined, an error occurs within a range of about ± 20 chips. From this, only this range is searched to detect the correlation. For example, the synchronization holding unit 25 starts the spreading code generated by the DLL 62 earlier than the phase of the spreading code supplied from the synchronization capturing unit 24 by 20 chips, and the period of the spreading code at that time is determined by the NCOs 64 and 87. If the frequency setting is set longer than (1 + 5 / 1575.420) milliseconds, the slide with respect to the spread code of the signal from the GPS satellite included in the IF signal starts when the slide shifts by +20 chips. It is possible to search for the presence or absence of correlation while the phases of the spreading codes slide during the time.
[0112]
Thus, in the past, correlation detection was performed using a DLL and a Costas loop while changing the IF carrier frequency in the range of the error of the oscillator and the amount of Doppler shift. In contrast, in the GPS receiver 10, the initial carrier frequency has only a slight error, and the correlation detection range is only a few tenths. The time required for establishment can be made extremely short.
[0113]
As described above, the GPS receiver 10 is configured by separating the synchronization acquisition function and the synchronization holding function, so that the phase of the spread code of the signal from the GPS satellite included in the IF signal by the synchronization acquisition unit 24. In addition, the IF carrier frequency can be detected at high speed, and the synchronization holding unit 25 can quickly shift to the synchronization holding operation based on the detection result. However, in the GPS receiver 10, when the processing sequence increases in order to detect a weak GPS satellite signal included in the IF signal, and the synchronization acquisition unit 24 is operated with a low-speed clock to reduce power consumption. In such a case, the processing time in the synchronization acquisition unit 24 becomes long, and accordingly, the search range until the synchronization establishment by the synchronization holding unit 25 is widened, which is not preferable.
[0114]
In general, in a GPS receiver, a common crystal oscillator is used as a source oscillator that generates a clock for signal processing in a local oscillator and a baseband processing unit in a frequency conversion unit. As previously shown in FIG. 1, the source oscillator of the local oscillator in the frequency conversion unit 23 and the source oscillator of the operation clock of the synchronization acquisition unit 24 and the synchronization holding unit 25 are shared by the TCXO 12. Then, the synchronization holding unit 25 is, for example, an intermediate frequency F of 1.023 MHz based on the IF carrier frequency detected by the synchronization acquisition unit 24 and the nominal value of the TCXO 12._IFΔF_IFAnd the carrier frequency of a signal from a GPS satellite of 1575.42 MHz is F_RFIf the time required for the synchronization acquisition processing after the IF acquisition of the IF signal to the memory is T seconds and the phase of the spread code is h, the phase h of the spread code is h + Δh as shown in FIG. (Δh = −T × ΔF_IF/ F_RFCorrect as follows. For example, ΔF_IFWhen +3 kHz and T = 10 seconds, Δh = −19 microseconds = about −19 chips. The synchronization holding unit 25 performs the correction as described above to thereby generate the oscillation frequency F of the TCXO 12._OSCThe phase shift of the spread code caused by the error and the Doppler shift can be corrected very accurately, and even if the synchronization acquisition process by the synchronization acquisition unit 24 takes several tens of seconds, it is approximately one chip. Synchronization can be established by searching in the range of.
[0115]
The reason why such correction is possible is as follows.
[0116]
In the GPS receiver 10, a carrier frequency F that is a known signal from a GPS satellite by the frequency converter 23._RFIs known intermediate frequency F_IFTo convert to a nominal oscillation frequency F_OSCOscillating frequency F by frequency synthesizer 18 based on TCXO12_LO= NxF_OSC(N is a constant number, N >> 1) and F_IF= F_RF-F_LOTo be. Here, the signal from the GPS satellite that is actually received has an intermediate frequency F_IFTCXO12 oscillation frequency F_OSCΔF caused by the error of and the Doppler shift_IFIs added. That is, in the GPS receiver 10, the Doppler shift amount is set to ΔF._DAnd the error from the nominal oscillation frequency by TCXO12 is ΔF_OSCThen,
F_IF+ ΔF_IF= F_RF+ ΔF_D-F_LO= F_RF+ ΔF_D-N × (F_OSC+ ΔF_OSC)
It becomes. Therefore, in the GPS receiver 10, the IF carrier frequency detected by the synchronization capturing unit 24 is
F_IF+ ΔF_IF, ΔF_IF= ΔF_D-N × ΔF_OSC
It becomes. What is important here is that what the synchronization capturing unit 24 can detect is ΔF._IFΔF_D, ΔF_OSCIs unknown at the initial acquisition stage.
[0117]
Here, if the timer counts 1 millisecond, which is one cycle length of the spread code, at the nominal oscillation frequency by the TCXO 12, the error ΔF_OSCIn fact, 1 millisecond x F_OSC/ (F_OSC+ ΔF_OSC) ≒ (1-ΔF_OSC/ F_OSC) Milliseconds. On the other hand, the one-cycle length of the spread code in the received signal is the Doppler shift amount ΔF._D1 ms x F_RF/ (F_RF+ ΔF_D) ≒ (1-ΔF_D/ F_RF) Milliseconds. Therefore, the ratio between the 1-cycle length of the spread code in the received signal and 1 millisecond counted at the nominal oscillation frequency by the TCXO 12 is:
(1-ΔF_D/ F_RF) / (1-ΔF_OSC/ F_OSC) ≒ 1-ΔF_D/ F_RF+ ΔF_OSC/ F_OSC
It becomes. Furthermore, if the right side of this equation is transformed,
1-ΔF_IF/ F_RF+ (ΔF_OSC/ F_OSC) X (F_IF/ (N × F_OSC)) ≒ 1-ΔF_IF/ F_RF
It becomes. As described above, in the GPS receiver 10, ΔF that is an unknown parameter for the synchronization acquisition unit 24._D, ΔF_OSCA fairly good approximation can be made without including.
[0118]
As a result, in the GPS receiver 10, the time from when the synchronization capturing unit 24 captures the IF signal to the memory performs the synchronization capturing process and the phase h of the detected spread code is supplied to the synchronization holding unit 25. When T seconds are required, the phase of the spread code detected by the synchronization acquisition unit 24 during this T seconds is −T × ΔF_IF/ F_RFWill be shifted. Therefore, as shown in FIG. 5, the synchronization holding unit 25 adds the correction value Δh = −T × ΔF to the phase h of the spread code supplied from the synchronization acquisition unit 24._IF/ F_RFBy adjusting the start timing of the spreading code generated by the DLL 62 by adding h + Δh, the phase shift of the spreading code that occurred during the synchronization acquisition processing time can be corrected, and thus the correlation can be achieved within a range of about one chip. Can be detected and synchronization can be established in a very short time. In the GPS receiver 10, for example, the CPU 26 calculates the correction value, supplies the calculation result to the synchronization holding unit 25, corrects the phase by the synchronization holding unit 25, and then starts the synchronization acquisition processing by the synchronization acquisition unit 24. That's fine.
[0119]
Information necessary for such a method of correcting the phase of the spread code is only the IF carrier frequency detected by the synchronization acquisition unit 24. In the GPS receiver 10, the oscillation frequency F of the TCXO 12 is detected._OSCNeither the error nor the Doppler shift amount is required as information. Further, in the GPS receiver 10, F is not dependent on the IF carrier frequency._IF= F_RO-F_LOSo that the local oscillation frequency F_LOEven when setting_IFIt is only necessary to change the sign of.
[0120]
Now, a specific configuration of the above-described synchronization capturing unit 24 will be described below. In the following, for convenience of explanation, the carrier of the IF signal supplied from the frequency conversion unit 23 is 1 MHz.
[0121]
As described above, the synchronization acquisition unit 24 is configured by mounting a digital matched filter using FFT as software executed by the DSP in order to perform synchronization acquisition of a spread code at high speed. The synchronization acquisition unit 24 is provided with a filter for removing negative frequency components from the data in the frequency domain obtained by subjecting the sampled IF signal to the FFT processing, and the diffusion generated by itself. A filter for removing negative frequency components from data in the frequency domain obtained by performing FFT processing on the code, and a complementary filter for restoring the negative frequency components removed by the filter; Is provided.
[0122]
Specifically, as shown in FIG. 6, the digital matched filter 100 generates an IF signal corresponding to the amplified IF signal D14 obtained by the antenna 14 and the frequency converter 23 described above, and an oscillation signal generated by the TCXO 12 described above. The input signal is sampled and input by the sampler 101 that samples the input signal at a predetermined sampling frequency based on D2. The digital matched filter 100 includes a memory 102 that buffers an IF signal of a certain time length sampled by the sampler 101, an FFT processing unit 103 that reads the IF signal buffered by the memory 102 and performs an FFT process, A negative frequency elimination filter 104 that removes negative frequency components from the frequency domain signal obtained by performing FFT processing by the FFT processing unit 203, and a buffer for the frequency domain signal passed by the negative frequency elimination filter 104 A memory 105 for ringing, an imaginary inversion filter 106 for converting the frequency domain signal buffered by the memory 105 into a complex conjugate signal, and a spread for generating the same spreading code as the spreading code in the RF signal from the GPS satellite Code generator 10 An FFT processing unit 108 that performs an FFT process on the spreading code generated by the spreading code generator 107, and a negative frequency among frequency domain signals obtained by performing the FFT process by the FFT processing unit 108. A negative frequency rejection filter 109 for removing components, a memory 110 for buffering a frequency domain signal passed by the negative frequency rejection filter 109, and a negative for the frequency domain signal buffered by the memory 110 A complementary filter 111 that restores the negative frequency component removed by the frequency removal filter 109, a shifter 112 that shifts the frequency domain signal obtained by complementation by the complement filter 111 on the frequency domain, and an imaginary inversion filter 106 Passed frequency domain signal and shifter 112 Therefore, a multiplier 113 that multiplies the shifted frequency domain signal, and an IFFT processing unit that performs an inverse FFT (Inverted Fast Fourier Transform; hereinafter referred to as IFFT) process on the frequency domain signal multiplied by the multiplier 113. 114, a memory 115 that buffers a cross-correlation function that is a time-domain signal obtained by performing IFFT processing by the IFFT processing unit 114, and a GPS satellite based on the cross-correlation function buffered by the memory 115 A peak detector 116 for detecting a correlation peak between the spread code in the RF signal from the spread signal and the spread code generated by the spread code generator 107.
[0123]
Further, since the digital matched filter 100 repeatedly uses a sine function and / or a cosine function in the calculation by the FFT processing units 103 and 108 and / or the IFFT processing unit 114, the calculation speed of the FFT processing and / or IFFT processing is high. And a sine / cosine generator 117 for generating a sine function or cosine function, and a memory 118 for holding the sine function or cosine function generated by the sine / cosine generator 117. The sine / cosine generator 117 performs sine calculation or cosine calculation in advance, and the result is stored in the memory 118 and can be arbitrarily read by the FFT processing units 103 and 108 and / or the IFFT processing unit 114. Yes.
[0124]
Such a digital matched filter 100 actually includes FFT processing units 103 and 108, negative frequency elimination filters 104 and 109, an imaginary inversion filter 106, a spread code generator 107, a complementary filter 111, a shifter 112, and a multiplier 113. The IFFT processing unit 114, the peak detector 116, and the sine / cosine generator 117 are implemented as software executed by the DSP. That is, the synchronization acquisition unit 24 to which the digital matched filter 100 is applied includes, for example, as shown in FIG. 7, a sampler 121 corresponding to the sampler 101 described above, a RAM 122 corresponding to the memory 102 described above, and the memories 105 and 110 described above. , 115, 118 and a RAM / ROM 123 including a DSP program area and work area, the FFT processing units 103 and 108, the negative frequency elimination filters 104 and 109, the imaginary inversion filter 106, the spreading code generator 107, and the complement The filter 111, the shifter 112, the multiplier 113, the IFFT processing unit 114, the peak detector 116, and the DSP 124 that executes the processing of the sine / cosine generator 117. The DSP 124 may be a CPU.
[0125]
The sampler 121 samples the IF signal input at a predetermined sampling frequency based on the oscillation signal D2 generated by the TCXO 12 described above. At this time, the sampler 121 starts sampling of the IF signal in response to a sampling start command from the DSP 124 or the CPU replacing the DSP 124 or the main CPU 26 described above. The IF signal sampled by the sampler 121 is written into the RAM 122 and buffered.
[0126]
The RAM 122 stores an IF signal having a fixed time length sampled and written by the sampler 121. The IF signal stored in the RAM 122 is read out by the DSP 124 or a CPU in place thereof, and used for correlation detection processing with a spread code.
[0127]
The RAM / ROM 123 stores various information. Of the RAM / ROM 123, the RAM is used as an area for storing the detected correlation value and a work area for the DSP 124 or a CPU replacing it. Of the RAM / ROM 123, the ROM is used as a program area executed by the DSP 124 or a CPU in place thereof and an area for storing necessary data. Note that the RAM of the RAM / ROM 123 may be physically shared with the RAM 122, and is merely illustrated as a logically different storage element in FIG.
[0128]
The DSP 124 or a CPU replacing it generates a spreading code corresponding to the GPS satellite instructed by the CPU 26 and performs an operation equivalent to the digital matched filter 100 to perform each phase of the spreading code for the IF signal stored in the RAM 122. The correlation value for is detected. The DSP 124 or a CPU instead thereof stores the detected correlation value in a part of the RAM in the RAM / ROM 123.
[0129]
In the digital matched filter 100 applied to the synchronization acquisition unit 24 having such a DSP 124, the sampler 101 samples the IF signal at a sampling frequency of 4.096 MHz. In the digital matched filter 100, a spread code generator 107 generates a spread code corresponding to a GPS satellite, and the FFT processing unit 108 performs FFT processing on the spread code.
[0130]
Here, a frequency as an output when a spread code sampled at a sampling frequency of 4.096 MHz is input to an FFT processing unit in a conventional digital matched filter corresponding to the FFT processing unit 108 in the digital matched filter 100. The spectral function of the region signal is shown in FIG. In addition, although the horizontal axis in the same figure shows a frequency, it has shown the number of points of the FFT operation which consists of 4096 points as a value. As is apparent from the figure, the frequency domain signal obtained by subjecting the spreading code generated by the FFT to the FFT processing is that most of the information is concentrated in the band up to 1 MHz, and the component of 2.048 MHz or higher. Even if “0” is set to “0”, the final result is hardly affected.
[0131]
Therefore, in the digital matched filter 100, when the spreading code generated by the spreading code generator 107 is input to the FFT processing unit 108, sampling is not performed at a sampling frequency of 4.096 MHz, but a sampling frequency of 2.048 MHz. For example, sampling is performed at a frequency twice the chip rate of the spreading code in the IF signal.
[0132]
Thereby, in the digital matched filter 100, the number of points of the FFT calculation in the FFT processing unit 108 is halved from 4096 points to 2048 points, and the calculation amount can be reduced.
[0133]
Further, in the digital matched filter 100, only the positive frequency component is obtained by passing the frequency domain signal obtained by the FFT processing unit 108 through the negative frequency elimination filter 109, and is stored in the memory 110.
[0134]
As described above, in the digital matched filter 100, the negative frequency elimination filter 109 is provided, and by removing the negative frequency component, the sampling frequency of the spread code is halved, so that the memory 110 Can be reduced to 1/4 from 32 kbytes to 8 kbytes.
[0135]
Further, in the digital matched filter 100, the complementary filter 111 is applied to the negative frequency component before supplying the multiplier 113 with the frequency domain signal from which the negative frequency component buffered in the memory 110 is removed. To restore.
[0136]
Here, since the spreading code is a real signal having no imaginary number component, the real number component in the frequency domain signal as a calculation result by the FFT processing unit 108 is an even function, and the imaginary number component is an odd function. When the calculation result by the FFT processing unit 108 is expressed by PN (k) using an integer k where 0 ≦ k <N where the number of data is “N”, the following expression (2) is established.
[0137]
[Expression 2]

[0138]
In the above equation (2), PN_r(K) indicates the real component of PN (k), and PN_j(K) indicates an imaginary component of PN (k).
[0139]
In the digital matched filter 100, the complementary filter 111 can restore the negative frequency component by using the above equation (2).
[0140]
In the digital matched filter 100, the frequency domain signal obtained through the complementary filter 111 is shifted by, for example, 1 MHz on the frequency domain using the shifter 112 in order to make the carrier equal to the carrier in the IF signal. The obtained frequency domain signal is supplied to the multiplier 113.
[0141]
On the other hand, in the digital matched filter 100, the IF signal is sampled at the sampling frequency of 4.096 MHz by the sampler 101 as described above.
[0142]
Here, FIG. 9 shows a spectral function of the frequency domain signal output from the multiplier in the conventional digital matched filter corresponding to the multiplier 113 in the digital matched filter 100. Note that the horizontal axis in the figure indicates the frequency as in FIG. 8, but indicates the number of points of the FFT operation consisting of 4096 points as values. As is apparent from the figure, this spectrum function has almost no negative frequency component because the spread code is shifted by 1 MHz. Further, a cross-correlation function, which is a time domain signal obtained by subjecting a frequency domain signal composed of this spectrum function to IFFT processing by an IFFT processing unit in a conventional digital matched filter corresponding to IFFT processing unit 114, is shown in FIG. As shown.
[0143]
On the other hand, as shown in FIG. 11, the time obtained by performing IFFT processing on the frequency domain signal in which the negative frequency component is set to “0” in the frequency domain signal output from the multiplier. The cross-correlation function that is the region signal is as shown in FIG. As is clear from comparison between the cross-correlation function shown in FIG. 10 and the cross-correlation function shown in FIG. 12, the cross-correlation function shown in FIG. 12 has a slightly lower peak value, but the peak is detected. Has a sufficient intensity, and the positions of the peaks indicating the phase of the spread code are exactly the same, and it can be said that both have almost the same result.
[0144]
Therefore, in the digital matched filter 100, only the positive frequency component is obtained by passing the frequency domain signal obtained by the FFT processing unit 103 through the negative frequency elimination filter 104, and is stored in the memory 105.
[0145]
As described above, in the digital matched filter 100, the negative frequency elimination filter 104 is provided to remove the negative frequency component, thereby reducing the required capacity of the memory 105 from 32 kbytes to 16 kbytes by half. Can do.
[0146]
In the digital matched filter 100, the frequency domain signal obtained through the negative frequency elimination filter 104 is passed through the imaginary inversion filter 106 to be converted into a complex conjugate signal, and the obtained frequency domain signal is multiplied by a multiplier. 113.
[0147]
In FIG. 6, the frequency domain signal buffered by the memory 105 is passed through the imaginary inversion filter 106, and the frequency domain signal buffered by the memory 110 is shifted by the shifter 112 via the complementary filter 111. However, in the digital matched filter 100, one of the frequency domain signal buffered by the memory 105 and the frequency domain signal buffered by the memory 110 is passed through the imaginary inversion filter 106 to obtain a complex conjugate. The signal is converted into a signal and the other is shifted in the frequency domain using the shifter 112. Even if the imaginary inversion filter 106 and the shifter 112 are replaced, the same effect can be obtained. Further, in the digital matched filter 100, the shifter 112 may be provided on both the IF signal side and the spread code side instead of being provided on either the IF signal side or the spread code side.
[0148]
Furthermore, in the digital matched filter 100, the calculation amount in the IFFT processing unit 114 is reduced, and accordingly, the necessary capacity of the memory 115 for buffering the cross-correlation function obtained by the IFFT processing unit 114 is also reduced. Can do.
[0149]
FIG. 13 shows a signal flow when IFFT processing is performed on a frequency domain signal whose negative frequency component is “0” and the number of data N is “16”. In the figure, the left side is an input signal R (k) (0 ≦ k <N) indicating the result of the FFT operation, and the right side is an output signal r (n) (0 ≦ n <N). In the figure, R0 (k ′) and R1 (k ′) (0 ≦ k ′ <N / 2) are signals indicating intermediate operation values at the time when the first stage of IFFT operation is completed, respectively. R0 (n ′) and r1 (n ′) (0 ≦ n ′ <N / 2) represent signals indicating the results of IFFT operations on R0 (k ′) and R1 (k ′), respectively. It is. The IFFT process is realized by repeating such a butterfly operation.
[0150]
Here, since the negative frequency component is “0”, the following expression (3) is established.
[0151]
[Equation 3]

[0152]
Note that the coefficient W in the above equation (3) is represented by W = exp (2πj / N), where the imaginary unit is “j”. That is, the signal R1 (k ′) indicating the intermediate operation value is equal to the coefficient W with respect to the input signal R (k ′).^{k '}While the signal R0 (k ′) is the input signal R (k ′) itself. Specifically, the signals R0 (0) to R0 (7) are R (0) to R (7), respectively, and the signals R1 (0) to R1 (7) are respectively R (0) W.⁰~ R (7) W⁷It becomes. From the figure, out of the output signal r (n) indicating the result of the IFFT operation on the input signal R (k), the even-numbered data extracted by the comb filter and the signal R0 (k ′) indicating the intermediate operation value It is clear that the signal r0 (n ′) indicating the result of the IFFT operation on () is equivalent as indicated by a rectangle C in FIG.
[0153]
Therefore, in the digital matched filter 100, the IFFT process is performed only on the signal R0 (k ′) corresponding to the positive frequency component of the input signal R (k). That is, in the digital matched filter 100, the IFFT processing unit 114 performs IFFT processing only on the positive frequency component of the frequency domain signal obtained by the multiplier 113.
[0154]
Thereby, in the digital matched filter 100, the number of points of IFFT calculation in the IFFT processing unit 114 is halved from 4096 points to 2048 points, and the amount of calculation can be reduced. Therefore, in the digital matched filter 100, the required capacity of the memory 115 can be reduced to ½ from 32 kbytes to 16 kbytes.
[0155]
However, in the digital matched filter 100, the time resolution of the cross-correlation function, which is the result obtained, is reduced by halving the number of points in the IFFT calculation. Specifically, a part of the cross-correlation function output from the IFFT processing unit in the conventional digital matched filter corresponding to the IFFT processing unit 114 in the digital matched filter 100 is shown in FIG. 14 and output from the IFFT processing unit 114. A part of the cross-correlation function is shown in FIGS. A black circle in the figure indicates one sample point.
[0156]
Here, the cross-correlation function shown in FIG. 15 is a case where the correlation peak in the cross-correlation function shown in FIG. 14 is extracted at the even-numbered sample point by the peak detector 116 made of a comb filter. Show. On the other hand, the cross-correlation function shown in FIG. 16 shows a case where the peak of the correlation in the cross-correlation function shown in FIG. 14 is extracted by the peak detector 116 formed of a comb filter when it is at an odd-numbered sample point. ing.
[0157]
Thus, in the digital matched filter 100, the time resolution of the cross correlation function shown in FIGS. 15 and 16 is lower than the time resolution of the cross correlation function shown in FIG. Further, in the digital matched filter 100, when the correlation peak is at the even-numbered sample point, as shown in FIG. 15, the correlation peak can be accurately detected, but the correlation peak is the odd-numbered sample point. 16, the peak value is reduced to about 3/4 times as shown in FIG.
[0158]
However, in the digital matched filter 100, the example shown in FIG. 16 is the worst case. Actually, the noise component is reduced as well as the peak value, so that the S / N is greatly deteriorated. No problem is caused by the decrease in time resolution.
[0159]
Further, in the digital matched filter 100, the amount of calculation in the sine / cosine generator 117 is reduced, and accordingly, the necessary capacity of the memory 118 that holds the sine function or cosine function generated by the sine / cosine generator 117. Can also be reduced.
[0160]
In general, a sine function can be obtained from a cosine function by using a trigonometric function. Also, the cosine function can be obtained for all phases from components with phases ranging from 0 radians to π / 2 radians by utilizing the symmetry. That is, in the sine function and cosine function, the relationships shown in the following equations (4) to (7) are established.
[0161]
[Expression 4]

[0162]
[Equation 5]

[0163]
[Formula 6]

[0164]
[Expression 7]

[0165]
Therefore, in the digital matched filter 100, the sine / cosine generator 117 calculates and generates only the components of the cosine function whose phase is from 0 radians to π / 2 radians, and these are stored in the memory 118. Then, in the digital matched filter 100, as a formula using a trigonometric function, a calculation composed of a plurality of patterns incorporating each of the above formulas (4) to (7) based on the cosine function held in the memory 118. When an equation is generated by a predetermined trigonometric function generator (not shown) and stored in a predetermined memory, and the cosine function stored in the memory 118 is read by the FFT processing units 103 and 108 and / or the IFFT processing unit 114 By switching the expression used according to the phase, the sine function and / or cosine function for all phases can be used using only the cosine function held in the memory 118.
[0166]
Specifically, in the digital matched filter 100, the phase generated by the sine / cosine generator 117 and held in the memory 118 is 0 radians to π / 2 radians through a series of processes shown in FIG. The sine function and / or cosine function of an arbitrary phase is used by the FFT processing units 103 and 108 and / or the IFFT processing unit 114 using the components of the cosine function up to.
[0167]
That is, in the digital matched filter 100, when the FFT processing units 103 and 108 and / or the IFFT processing unit 114 input a signal as shown in the figure, in step S1, the FFT processing units 103 and 108 and / or the IFFT processing are performed. It is determined whether the phase of the function required by each of the units 114 is 0 radians to π / 2 radians.
[0168]
Here, when it is determined that the phase of the required function is 0 radians to π / 2 radians, in the digital matched filter 100, in step S2, it is generated by the trigonometric function generator and stored in the memory. The necessary sine function and / or cosine function having a phase of 0 radians to π / 2 radians by each of the FFT processing units 103 and 108 and / or the IFFT processing unit 114, using the expression A of the first pattern Use.
[0169]
On the other hand, if it is determined that the phase of the required function is not 0 radians to π / 2 radians, the digital matched filter 100 proceeds to step S3, and the FFT processing units 103, 108 and / or It is determined whether or not the phase of the function required by each of the IFFT processing units 114 is π / 2 radians to π radians.
[0170]
Here, when it is determined that the phase of the required function is π / 2 radians to π radians, in the digital matched filter 100, in step S4, it is generated by the trigonometric function generator and stored in the memory. The necessary sine function and / or cosine function having a phase of π / 2 radians to π radians by the FFT processing units 103 and 108 and / or the IFFT processing unit 114, respectively, using the second pattern equation B. Use.
[0171]
On the other hand, if it is determined that the phase of the required function is not π / 2 radians to π radians, the digital matched filter 100 proceeds to step S5, and the FFT processing units 103, 108 and / or It is determined whether or not the phase of the function required by each of the IFFT processing units 114 is π radians to 3π / 2 radians.
[0172]
Here, if it is determined that the phase of the required function is π radians to 3π / 2 radians, in the digital matched filter 100, in step S6, it is generated by the trigonometric function generator and stored in the memory. The necessary sine function and / or cosine function having a phase of π radians to 3π / 2 radians by the FFT processing units 103 and 108 and / or the IFFT processing unit 114, respectively, using the third pattern equation C. Use.
[0173]
On the other hand, if it is determined that the required function phase is not π radians to 3π / 2 radians, the required function phase is 3π / 2 radians to 2π radians. , The process proceeds to step S7, and each of the FFT processing units 103 and 108 and / or the IFFT processing unit 114 is performed using the fourth pattern expression D generated by the trigonometric function generator and held in the memory. To use the necessary sine and / or cosine functions with a phase of 3π / 2 radians to 2π radians.
[0174]
In the digital matched filter 100, a component of a cosine function whose phase generated by the sine / cosine generator 117 and held in the memory 118 is 0 radians to π / 2 radians through such a series of processes. The sine function and / or cosine function of an arbitrary phase can be used by the FFT processing units 103 and 108 and / or the IFFT processing unit 114.
[0175]
Thereby, in the digital matched filter 100, the calculation amount in the sine / cosine generator 117 can be reduced to 1/8 times, and the required capacity of the memory 118 is reduced to 1/8 from 32 kbytes to 4 kbytes. can do.
[0176]
Note that the function generated by the sine / cosine generator 117 and stored in the memory 118 does not necessarily have to be a component of a cosine function having a phase of 0 radians to π / 2 radians. Any component whose phase is 0 radians to π / 2 radians, π / 2 radians to π radians, π radians to 3π / 2 radians, or 3π / 2 radians to 2π radians may be held in the memory 118, and the cosine function The sine function may be held in the memory 118, and a sine function and / or cosine function having an arbitrary phase can be used in all of these cases.
[0177]
Thus, in the digital matched filter 100, the necessary capacity of the memory 105 that holds the frequency domain signal obtained by performing the FFT process on the IF signal is 16 kbytes, and obtained by performing the FFT process on the spread code. The required capacity of the memory 110 that holds the frequency domain signal is 8 kbytes, and the required capacity of the memory 115 that holds the cross-correlation function obtained by performing IFFT processing on the frequency domain signal is 16 kbytes. Since the necessary capacity of the memory 118 for holding the sine function or cosine function generated by the device 117 is 4 kbytes, it is sufficient that there is a total capacity of 44 kbytes, which is about 1/3 of the conventional 128 kbytes. The required memory capacity can be reduced to a certain extent.
[0178]
Further, in the digital matched filter 100, the amount of calculation in the FFT processing unit 108 can be reduced by reducing the number of data when the spreading code is converted into the frequency domain signal. Further, in the digital matched filter 100, the number of data when multiplying each of the IF signal converted into the frequency domain signal and the spread code is halved compared to the conventional case, so that the amount of calculation in the multiplier 113 is also large. It can be reduced to 1/2 compared to the conventional case. Furthermore, in the digital matched filter 100, the number of points in the IFFT operation when performing the IFFT processing is halved compared to the conventional case, so the amount of computation in the IFFT processing unit 114 is reduced to ½ or less than the conventional case. can do. Further, in the digital matched filter 100, the calculation amount in the sine / cosine generator 117 can be reduced to 1/8 compared to the conventional case.
[0179]
As described above, when the GPS receiver 10 detects the correlation value for searching for the phase of the spread code by the synchronization acquisition unit 24, the capacity of the mounted memory is reduced, and the calculation amount of each unit is also increased. Regardless of the reduction, the same result as before can be obtained, and the correlation peak can be detected accurately and easily. Therefore, especially when the GPS receiver 10 is configured as an integrated circuit, it is possible to increase the degree of integration. Therefore, it is possible to reduce the calculation time while reducing the size and cost.
[0180]
The present invention is not limited to the embodiment described above. For example, in the above-described embodiment, the GPS receiver 10 has been described. However, the present invention can be applied to any receiver that receives and demodulates a spread spectrum signal.
[0181]
In the above-described embodiment, the GPS receiver 10 has been described. However, the present invention may be a positioning system using a satellite, that is, an electronic device incorporating a receiver function to which a GNSS system is applied. Anything can be applied. Examples of the GNSS system include the above-described GPS system in the United States, GLONASS (Global Navigation Satellites System) in the former Soviet Union, and GALILEO that is being developed mainly in Europe. The system can be applied.
[0182]
Thus, it goes without saying that the present invention can be modified as appropriate without departing from the spirit of the present invention.
[0183]
【The invention's effect】
As described above in detail, the matched filter device according to the present invention detects a correlation between a spread code and a spread code generated by itself in order to detect the phase of the spread code in the input spread spectrum signal. A first fast Fourier transform processing means for performing a fast Fourier transform process on data inputted by sampling a spectrum spread signal at a predetermined sampling frequency, and the first fast Fourier transform processing means. The negative frequency removing means for removing the negative frequency component from the frequency domain signal obtained by performing the fast Fourier transform processing by the, and the frequency domain signal from which the negative frequency component has been removed by the negative frequency removing means First storage means for buffering, and the same spreading code as the spreading code in the spread spectrum signal A spreading code generating means for generating a signal, a second fast Fourier transform processing means for applying a fast Fourier transform to the spreading code generated by the spreading code generating means, and at least the second fast Fourier transform processing means. Second storage means for buffering a frequency domain signal obtained by performing the fast Fourier transform process.
[0184]
Therefore, the matched filter device according to the present invention removes the negative frequency component from the frequency domain signal obtained by the fast Fourier transform processing by the first fast Fourier transform processing means by the negative frequency removing means, The obtained frequency domain signal is stored in the first storage means, and at least the frequency domain signal obtained by performing the fast Fourier transform processing by the second fast Fourier transform processing means is stored in the second storage means. As a result, the capacity of the first storage means can be reduced to reduce the size and cost.
[0185]
Further, in the matched filter device according to the present invention, the second fast Fourier transform processing means includes a spreading code generated by the spreading code generating means at a frequency twice the chip rate of the spreading code in the spread spectrum signal. Sampled and input.
[0186]
Therefore, the matched filter device according to the present invention applies the first to the spreading code composed of 1/2 the number of data of the spread spectrum signal subjected to the fast Fourier transform processing by the first fast Fourier transform processing means. By performing the fast Fourier transform processing by the two fast Fourier transform processing means, the amount of computation in the second fast Fourier transform processing means can be reduced, and the computation time can be reduced.
[0187]
Further, the matched filter device according to the present invention removes the negative frequency component from the frequency domain signal obtained by performing the fast Fourier transform processing by the second fast Fourier transform processing means. The second storage means buffers the frequency domain signal from which the negative frequency component has been removed by the other negative frequency removal means.
[0188]
Furthermore, the matched filter device according to the present invention includes a complementary means for restoring the negative frequency component removed by the other negative frequency removing means for the frequency domain signal buffered by the second storage means. Prepare.
[0189]
Therefore, the matched filter device according to the present invention removes the negative frequency component of the frequency domain signal obtained by performing the fast Fourier transform processing by the second fast Fourier transform processing means by using another negative frequency removing means. Then, the obtained frequency domain signal is stored in the second storage means, and further complemented from the frequency domain signal consisting only of the positive frequency component from which the negative frequency component has been removed by the other negative frequency elimination means. Thus, by restoring the negative frequency component, the capacity of the second storage means can be reduced, and the size and cost can be reduced.
[0190]
Further, the matched filter device according to the present invention includes a multiplying unit that multiplies at least the frequency domain signal buffered by the first storage unit and the frequency domain signal buffered by the second storage unit, Inverse fast Fourier transform processing means for performing inverse fast Fourier transform processing on the frequency domain signal multiplied by the multiplication means, and a cross-correlation function obtained by applying inverse fast Fourier transform processing by the inverse fast Fourier transform processing means And third storage means for buffering.
[0191]
Furthermore, in the matched filter device according to the present invention, the inverse fast Fourier transform processing means performs inverse fast Fourier transform processing only on the positive frequency component of the frequency domain signal obtained by the multiplication means.
[0192]
Therefore, the matched filter device according to the present invention performs the inverse fast Fourier transform processing by the inverse fast Fourier transform processing means on the frequency domain signal composed of ½ of the number of data in the frequency domain signal obtained by the multiplication means. Furthermore, by storing the cross-correlation function obtained by performing the inverse fast Fourier transform processing by the inverse fast Fourier transform processing means in the third storage means, the calculation amount in the inverse fast Fourier transform processing means is reduced, The calculation time can be reduced, and the capacity of the third storage means can be reduced to reduce the size and cost.
[0193]
Furthermore, the matched filter device according to the present invention includes a sine / cosine generating means for generating a sine function or a cosine function, and a sine function or cosine function generated by the sine / cosine generating means. And a fourth storage unit that is held so as to be readable by each of the transform processing unit, the second fast Fourier transform processing unit, and / or the inverse fast Fourier transform processing unit.
[0194]
In addition, the matched filter device according to the present invention includes a trigonometric function generation unit that generates a calculation formula including a plurality of patterns using a trigonometric function based on the sine function or the cosine function held in the fourth storage unit. Storage means for holding a calculation formula composed of a plurality of patterns generated by the trigonometric function generating means, wherein the sine / cosine generating means generates only a part of the components of the sine function or cosine function to generate a fourth component. The first fast Fourier transform processing means, the second fast Fourier transform processing means, and / or the inverse fast Fourier transform processing means are respectively stored in the storage means according to the phase of the required function. The sine function and / or cosine function of an arbitrary phase is utilized by switching the calculation formulas composed of a plurality of patterns stored in.
[0195]
Therefore, the matched filter device according to the present invention generates only a partial component of the sine function or cosine function by the sine / cosine generation means and stores it in the fourth storage means, thereby calculating the sine / cosine generation means. The amount can be reduced, the calculation time can be reduced, and the capacity of the fourth storage means can be reduced to reduce the size and cost.
[0196]
As described above, the matched filter device according to the present invention can reduce the capacity of the storage means to be mounted, thereby reducing the size and cost, and reducing the calculation time.
[0197]
A correlation detection method according to the present invention is a correlation detection method for detecting a correlation between a spread code and a spread code generated by itself in order to detect the phase of the spread code in the input spread spectrum signal, A process of performing a fast Fourier transform process on input data obtained by sampling a spread spectrum signal at a predetermined sampling frequency, and a negative frequency domain signal obtained by performing a fast Fourier transform process on the input data. A step of removing the frequency component of the signal, a step of buffering the frequency domain signal from which the negative frequency component has been removed in the first storage means, a step of generating the same spreading code as the spreading code in the spread spectrum signal, and Performing a fast Fourier transform process on the generated spreading code and at least a high speed for the generated spreading code And buffering the frequency domain signal obtained by performing the Fourier transform process in the second storage means.
[0198]
Therefore, the correlation detection method according to the present invention removes the negative frequency component from the frequency domain signal obtained by performing fast Fourier transform processing on the input data, and uses the obtained frequency domain signal as the first frequency domain signal. The capacity of the first storage means is reduced by storing in the storage means and storing in the second storage means a frequency domain signal obtained by performing fast Fourier transform processing on at least the generated spreading code. This makes it possible to reduce the size and cost.
[0199]
Furthermore, a receiving apparatus according to the present invention is a receiving apparatus that receives a signal from a satellite and calculates its own position and velocity, a receiving means for receiving a signal from the satellite, and a reception received by the receiving means. Frequency conversion means for converting the frequency of the signal to a predetermined intermediate frequency, and synchronization acquisition for detecting the phase of the spread code in the intermediate frequency signal obtained by the frequency conversion means and detecting the carrier frequency in the intermediate frequency signal The acquisition means, the phase of the spread code detected by the synchronization acquisition means, and the carrier frequency detected by the synchronization acquisition means for each of a plurality of channels provided independently corresponding to the plurality of satellites. The phase and carrier frequency of the set spreading code are set as initial values, and synchronization between the spreading code and the carrier is maintained. And a synchronization maintaining means for demodulating a message included in the intermediate frequency signal, and for detecting the phase of the spread code in the intermediate frequency signal, which is a spread spectrum signal, The synchronization acquisition means for detecting the correlation with the first fast Fourier transform processing means for performing fast Fourier transform processing on the input data obtained by sampling the intermediate frequency signal at a predetermined sampling frequency, and the first fast Fourier transform processing means The negative frequency component is removed from the frequency domain signal obtained by performing the fast Fourier transform processing by the fast Fourier transform processing unit, and the negative frequency component is removed by the negative frequency removing unit. First storage means for buffering the frequency domain signal, and the same as the spreading code in the intermediate frequency signal A spread code generating means for generating a spread code; a second fast Fourier transform processing means for performing a fast Fourier transform process on the spread code generated by the spread code generating means; and at least a second fast Fourier transform process. A matched filter having second storage means for buffering a frequency domain signal obtained by performing fast Fourier transform processing by the means.
[0200]
Therefore, the receiving apparatus according to the present invention removes the negative frequency component of the frequency domain signal obtained by performing the fast Fourier transform processing by the first fast Fourier transform processing means in the synchronization acquisition means by the negative frequency removing means. The frequency domain signal obtained by the removal is stored in the first storage means, and the frequency domain signal obtained by performing fast Fourier transform processing by at least the second fast Fourier transform processing means is stored in the second storage means. Thus, the capacity of the first storage means can be reduced to reduce the size and cost.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a GPS receiver shown as an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a synchronization holding unit included in the GPS receiver.
FIG. 3 is a block diagram illustrating a configuration of a channel circuit included in a synchronization holding unit included in the GPS receiver.
FIG. 4 is a diagram for explaining phase alignment of spread codes in a synchronization holding unit provided in the GPS receiver.
FIG. 5 is a diagram for explaining spread code phase correction in a synchronization holding unit included in the GPS receiver;
FIG. 6 is a block diagram illustrating a configuration of a digital matched filter using FFT that can be applied as a synchronization acquisition unit included in the GPS receiver.
7 is a block diagram for explaining an actual implementation example when the digital matched filter shown in FIG. 6 is applied as a synchronization acquisition unit provided in the GPS receiver. FIG.
FIG. 8 is a diagram illustrating an example of a spectrum function of a frequency domain signal obtained by performing FFT processing on a spread code using a conventional digital matched filter.
FIG. 9 is a diagram illustrating an example of a spectrum function of a frequency domain signal output from a multiplier in a conventional digital matched filter.
10 is a diagram for explaining an example of an output waveform showing a temporal change in a correlation value obtained by performing IFFT processing on a frequency domain signal whose spectrum function is shown in FIG. 9 by a conventional digital matched filter.
11 is a diagram illustrating an example of a spectrum function of a frequency domain signal in which a negative frequency component output from a multiplier in the digital matched filter illustrated in FIG. 6 is “0”.
12 is a diagram for explaining an example of an output waveform showing a temporal change of a correlation value obtained by performing IFFT processing on a frequency domain signal whose spectrum function is shown in FIG. 11 by the digital matched filter shown in FIG. 6;
FIG. 13 is a diagram for explaining a signal flow when IFFT processing is performed on a frequency domain signal in which the negative frequency component is “0” and the number of data N is “16”.
FIG. 14 is a diagram for explaining a part of a cross-correlation function obtained by a conventional digital matched filter.
15 is a diagram for explaining a part of the cross-correlation function obtained by the digital matched filter shown in FIG. 6, and shows a part of the cross-correlation function extracted when the correlation peak is at an even-numbered sample point. It is a figure explaining.
16 is a diagram for explaining a part of the cross-correlation function obtained by the digital matched filter shown in FIG. 6, and shows a part of the cross-correlation function extracted when the correlation peak is at an odd-numbered sample point. It is a figure explaining.
FIG. 17 is a diagram illustrating an example of using a cosine function component having a phase of 0 radians to π / 2 radians generated by a sine / cosine generator in the digital matched filter shown in FIG. It is a flowchart explaining a series of processes at the time of utilizing a sine function and / or a cosine function.
FIG. 18 is a diagram illustrating a configuration of a signal from a GPS satellite.
FIG. 19 is a diagram for explaining a conventional spreading code and carrier synchronization process and a diagram for explaining a frequency search;
FIG. 20 is a diagram illustrating an example of an output waveform showing a temporal change in a correlation value detected using a digital matched filter.
FIG. 21 is a block diagram illustrating a configuration of a digital matched filter using FFT applied to a conventional GPS receiver.
[Explanation of symbols]
10 GPS receiver, 11 XO, 12 TCXO, 13 multiplier / divider, 14 antenna, 15 LNA, 16 BPF, 17,20 amplifier, 18 frequency synthesizer, 19 mixer, 21, 67, 68, 77, 78, 82 , 83 LPF, 22 A / D, 23 frequency conversion unit, 24 synchronization acquisition unit, 25 synchronization holding unit, 26 CPU, 27 RTC, 28 timer, 29, 102, 105, 110, 115, 118 memory, 30 demodulation circuit, 51,51₁, 51₂, ..., 51_N  Channel circuit, 52 control register, 61 Costas loop, 62 DLL, 63, 65, 66, 73, 74, 75, 76, 80, 81, 113 multiplier, 64, 87 NCO, 69, 86 loop filter, 70, 85 phase detector, 71 binarization circuit, 72, 79, 84 square sum calculation circuit, 88, 107 spreading code generator, 100 digital matched filter, 101, 121 sampler, 103, 108 FFT processing unit, 104, 109 Negative frequency rejection filter, 106 Imaginary inversion filter, 111 Complement filter, 112 Shifter, 114 IFFT processing unit, 116 Peak detector, 117 Sine / cosine generator, 122 RAM, 123 RAM / ROM, 124 DSP

Claims (15)

In order to detect a phase of a spread code in an input spread spectrum signal, a matched filter device that detects a correlation between the spread code and a spread code generated by the self,
First fast Fourier transform processing means for performing fast Fourier transform processing on data input by sampling the spectrum spread signal at a predetermined sampling frequency;
A negative frequency removing means for removing a negative frequency component from the frequency domain signal obtained by performing the fast Fourier transform processing by the first fast Fourier transform processing means;
First storage means for buffering the frequency domain signal from which the negative frequency component has been removed by the negative frequency removal means;
Spreading code generating means for generating the same spreading code as the spreading code in the spread spectrum signal;
Second fast Fourier transform processing means for performing fast Fourier transform processing on the spreading code generated by the spreading code generating means;
Second storage means for buffering a frequency domain signal obtained by performing fast Fourier transform processing by at least the second fast Fourier transform processing means;
Imaginary inversion means for converting the frequency domain signal buffered by the first storage means or the second storage means into a complex conjugate signal;
Shift means for shifting the frequency domain signal buffered by the second storage means and / or the first storage means on the frequency domain;
A matched filter device comprising:   The second fast Fourier transform processing means receives the spread code generated by the spread code generation means after being sampled and input at a frequency twice the chip rate of the spread code in the spread spectrum signal. The matched filter device according to claim 1.   The second storage means includes other negative frequency removing means for removing a negative frequency component from the frequency domain signal obtained by performing the fast Fourier transform processing by the second fast Fourier transform processing means. 2. The matched filter device according to claim 1, wherein the frequency domain signal from which the negative frequency component has been removed by the other negative frequency removing means is buffered.   4. The matched filter device according to claim 3, wherein each of the negative frequency removing unit and the other negative frequency removing unit is a filter that passes only a positive frequency component of the frequency domain signal. The complementing means which restore | restores the negative frequency component removed by the said other negative frequency removal means with respect to the frequency domain signal buffered by the said 2nd memory | storage means is characterized by the above-mentioned. Matched filter device. The complementing means uses the frequency domain signal obtained by performing the fast Fourier transform processing by the second fast Fourier transform processing means, using the integer k of 0 ≦ k <N, where N is the number of data, PN ( 6. The matched filter device according to claim 5, wherein the filter is a filter that restores a negative frequency component using an operation represented by the following general formula (1) when represented by k).

(However, PN _r (k) indicates the real component of PN (k), and PN _j (k) indicates the imaginary component of PN (k).) Multiplication means for multiplying at least the frequency domain signal buffered by the first storage means by at least the frequency domain signal buffered by the second storage means;
Inverse fast Fourier transform processing means for performing inverse fast Fourier transform processing on the frequency domain signal multiplied by the multiplication means;
2. The matched filter device according to claim 1, further comprising third storage means for buffering a cross-correlation function obtained by performing inverse fast Fourier transform processing by the inverse fast Fourier transform processing means.   8. The matched filter device according to claim 7, wherein the inverse fast Fourier transform processing means performs inverse fast Fourier transform processing only on a positive frequency component of the frequency domain signal obtained by the multiplication means.   Peak detecting means for detecting a correlation peak between the spread code in the spread spectrum signal and the spread code generated by the spread code generating means based on the cross-correlation function buffered by the third storage means. The matched filter device according to claim 8. A sine / cosine generating means for generating a sine function or a cosine function;
The sine function or cosine function generated by the sine / cosine generating means is converted by the first fast Fourier transform processing means, the second fast Fourier transform processing means, and / or the inverse fast Fourier transform processing means, respectively. The matched filter device according to claim 7, further comprising a fourth storage unit that holds the data in a readable manner. A trigonometric function generating means for generating a calculation formula consisting of a plurality of patterns using a trigonometric function based on the sine function or the cosine function held in the fourth storage means;
Storage means for holding a calculation formula composed of the plurality of patterns generated by the trigonometric function generation means,
The sine / cosine generating means generates only a partial component of the sine function or cosine function and stores it in the fourth storage means,
The first fast Fourier transform processing means, the second fast Fourier transform processing means, and / or the inverse fast Fourier transform processing means are each stored in the storage means in accordance with the phase of the required function. 11. The matched filter device according to claim 10, wherein a sine function and / or cosine function having an arbitrary phase is used by switching calculation formulas composed of the plurality of patterns.   The part of the components may have a phase of 0 radians to π / 2 radians, π / 2 radians to π radians, π radians to 3π / 2 radians, or 3π / 2 radians to 2π radians. The matched filter device according to claim 11, wherein:   2. The matched filter according to claim 1, wherein synchronization acquisition is performed to detect a phase of a spread code in the spread spectrum signal when receiving a signal from a satellite and calculating its position and velocity. apparatus. A correlation detection method for detecting a correlation between the spread code and a spread code generated by itself in order to detect a phase of the spread code in the input spread spectrum signal,
A step of performing a fast Fourier transform on the input data obtained by sampling the spread spectrum signal at a predetermined sampling frequency;
Removing a negative frequency component from a frequency domain signal obtained by performing a fast Fourier transform on the input data;
Buffering the frequency domain signal from which the negative frequency component has been removed into the first storage means;
Generating the same spreading code as the spreading code in the spread spectrum signal;
Applying a fast Fourier transform to the generated spreading code;
Buffering a frequency domain signal obtained by performing a fast Fourier transform process on at least the generated spreading code in the second storage means;
Converting the frequency domain signal buffered by the first storage means or the second storage means into a complex conjugate signal;
Shifting the frequency domain signal buffered by the second storage means and / or the first storage means on the frequency domain;
A correlation detection method comprising: A receiving device that receives a signal from a satellite and calculates its position and velocity,
Receiving means for receiving a signal from the satellite;
Frequency converting means for converting the frequency of the received signal received by the receiving means to a predetermined intermediate frequency;
Synchronization acquisition means for detecting the phase of the spreading code in the intermediate frequency signal obtained by the frequency conversion means and detecting the carrier frequency in the intermediate frequency signal;
The satellite of the phase of the spreading code detected by the synchronization acquisition means and the carrier frequency detected by the synchronization acquisition means for each of a plurality of channels provided independently for the plurality of satellites. Synchronous holding that performs assignment and setting for each phase, maintains the synchronization between the spreading code and the carrier using the set phase of the spreading code and the carrier frequency as initial values, and demodulates the message included in the intermediate frequency signal Means and
In order to detect the phase of the spread code in the intermediate frequency signal that is a spread spectrum signal, the synchronization acquisition means for detecting the correlation between the spread code and the spread code generated by the self,
First fast Fourier transform processing means for performing fast Fourier transform processing on data input by sampling the intermediate frequency signal at a predetermined sampling frequency;
A negative frequency removing means for removing a negative frequency component from the frequency domain signal obtained by performing the fast Fourier transform processing by the first fast Fourier transform processing means;
First storage means for buffering the frequency domain signal from which the negative frequency component has been removed by the negative frequency removal means;
Spreading code generating means for generating the same spreading code as the spreading code in the intermediate frequency signal;
Second fast Fourier transform processing means for performing fast Fourier transform processing on the spreading code generated by the spreading code generating means;
Second storage means for buffering a frequency domain signal obtained by performing fast Fourier transform processing by at least the second fast Fourier transform processing means;
Imaginary inversion means for converting the frequency domain signal buffered by the first storage means or the second storage means into a complex conjugate signal;
A shift means for shifting the frequency-domain signal buffered in the frequency domain by the second storage means and / or the first storage means,
A receiving apparatus comprising: a matched filter having

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