WO2002052725A3 - Circuit de temporisation a temporisation reglable - Google Patents

Circuit de temporisation a temporisation reglable Download PDF

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Publication number
WO2002052725A3
WO2002052725A3 PCT/DE2001/004311 DE0104311W WO02052725A3 WO 2002052725 A3 WO2002052725 A3 WO 2002052725A3 DE 0104311 W DE0104311 W DE 0104311W WO 02052725 A3 WO02052725 A3 WO 02052725A3
Authority
WO
WIPO (PCT)
Prior art keywords
delay
block
circuit
switch
adjustable
Prior art date
Application number
PCT/DE2001/004311
Other languages
German (de)
English (en)
Other versions
WO2002052725A2 (fr
Inventor
Thomas Hein
Patrick Heyne
Thilo Marx
Torsten Partsch
Original Assignee
Infineon Technologies Ag
Thomas Hein
Patrick Heyne
Thilo Marx
Torsten Partsch
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Thomas Hein, Patrick Heyne, Thilo Marx, Torsten Partsch filed Critical Infineon Technologies Ag
Publication of WO2002052725A2 publication Critical patent/WO2002052725A2/fr
Publication of WO2002052725A3 publication Critical patent/WO2002052725A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)

Abstract

L'invention concerne un circuit de temporisation à temporisation réglable, comprenant un premier bloc (1) et un second bloc (2) monté en aval, qui présentent chacun une chaîne d'éléments de temporisation (11 à 16, 21 à 26). Il est alloué à chaque bloc, un groupe de commutateurs (4, 5) permettant de sélectionner des prélèvements côté sortie sur les éléments de temporisation (11 à 16, 21 à 26), au moyen de commutateurs (S1 à S6), afin de pouvoir sélectionner un temps de temporisation voulu. Afin de pouvoir amorcer simultanément le commutateur (S6) relié à l'élément de temporisation côté sortie (16) du premier bloc (1) et le commutateur (S6) relié à l'élément de temporisation côté entrée (26) du second bloc (2), leurs entrées de commande sont interconnectées. Ce qui permet d'éviter les impulsions perturbatrices, même en cas de cycles d'horloge de signaux d'horloge (A) applicables côté entrée aux éléments de temporisation. Le circuit de temporisation décrit est de ce fait particulièrement adapté à une utilisation dans des boucles de régulation de temporisation dans des puces mémoire à faisceau hertzien numérique.
PCT/DE2001/004311 2000-12-27 2001-11-15 Circuit de temporisation a temporisation reglable WO2002052725A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10065376A DE10065376C1 (de) 2000-12-27 2000-12-27 Verzögerungsschaltung mit einstellbarer Verzögerung
DE10065376.6 2000-12-27

Publications (2)

Publication Number Publication Date
WO2002052725A2 WO2002052725A2 (fr) 2002-07-04
WO2002052725A3 true WO2002052725A3 (fr) 2003-08-28

Family

ID=7669234

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/004311 WO2002052725A2 (fr) 2000-12-27 2001-11-15 Circuit de temporisation a temporisation reglable

Country Status (3)

Country Link
DE (1) DE10065376C1 (fr)
TW (1) TW517459B (fr)
WO (1) WO2002052725A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10345236B3 (de) * 2003-09-29 2005-03-10 Infineon Technologies Ag Verzögerungsregelkreis
DE102005009806A1 (de) 2005-03-03 2006-09-14 Infineon Technologies Ag Pufferbaustein für ein Speichermodul, Speichermodul und Speichersystem

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095233A (en) * 1991-02-14 1992-03-10 Motorola, Inc. Digital delay line with inverter tap resolution
US5521499A (en) * 1992-12-23 1996-05-28 Comstream Corporation Signal controlled phase shifter
EP1039637A1 (fr) * 1999-03-23 2000-09-27 Infineon Technologies North America Corp. Ligne de retard avec ajustage de la gamme des fréquences
US20020047739A1 (en) * 2000-10-24 2002-04-25 Mace Timothy Charles Modified clock signal generator

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US566849A (en) * 1896-09-01 Cable hoisting and conveying apparatus
JP3077813B2 (ja) * 1990-05-11 2000-08-21 ソニー株式会社 プログラマブル遅延回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095233A (en) * 1991-02-14 1992-03-10 Motorola, Inc. Digital delay line with inverter tap resolution
US5521499A (en) * 1992-12-23 1996-05-28 Comstream Corporation Signal controlled phase shifter
EP1039637A1 (fr) * 1999-03-23 2000-09-27 Infineon Technologies North America Corp. Ligne de retard avec ajustage de la gamme des fréquences
US20020047739A1 (en) * 2000-10-24 2002-04-25 Mace Timothy Charles Modified clock signal generator

Also Published As

Publication number Publication date
DE10065376C1 (de) 2002-07-25
TW517459B (en) 2003-01-11
WO2002052725A2 (fr) 2002-07-04

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