TW517459B - Delay circuit with adjustable delay - Google Patents

Abstract

The invention specifies a delay circuit with adjustable delay having a first block (1) and a downstream-connected second block (2) which respectively comprise a chain of delay elements (11 to 16, 21 to 26). Each block has an associated group of switches (4, 5), which groups can be used to select output-side taps on the delay elements (11 to 16, 21 to 26) using switches (S1 to S6) in order to be able to select a desired delay time. For the purpose of simultaneously driving the switch (S6) connected to the output-side delay element (16) of the first block (1) and the switch (S6) connected to the input-side delay element (26) of the second block (2), the control inputs of said switches are connected to one another. This makes it possible to prevent interference pulses even at high clock rates of clock signals (A) which can be applied to the inputs of the delay elements. The delay circuit described is therefore particularly suitable for use in delay locked loops in DDR memory chips.

Description

5. Description of the invention (1) The present invention relates to a delay circuit with adjustable delay. To provide a variable delay

The circuit usually has _reverse ^, digitized operation delay-locked back σ σ, 丼 includes multiple consecutively connected inverters, 2 = two identical circuit nodes in the chain have signal tapping points. Therefore, it is possible to adjust the delay time with the knife and the knife. In this case, you can use the delay time of the signal by a good inverter or group of inverters. In order to select the tapping point, a demultiplexer is usually provided. The input end of the demultiplexer is connected to the tapping point and the output end is tapped with an adjustable delay time. Signal, multiplexer is preferably multi-section, design 'for example two-section design. In this case, the mothers forming the individual reverse blocks all contain N consecutively connected reversers. Document No. EP 1039637 A1 details this type of delay-locked loop. The inverter chain has a multi-level arrangement 2: 1 multiplexer 1 to provide digitization. Adjust the delay time. Compare Figures 1 and 4. With the two-section design of the selection circuit in the breaker, a first selection line or: the first selection bit & for example, used in the first selection plate by selecting an inverter area The block makes a secondary selection of a tapping point. When a second selection line or a second selection bit is used, a tapping node can be selected in a block using a secondary 2 way. In this case, the first remote selection line is used to select all the first, second, and third tapping nodes' for all blocks, respectively. In this case, when switching from one inverter group to another, the problem that a large number of switches need to operate at the same time occurs, so that the output end is subject to China National Standard (CNS) ) A4 size (210X297) 517459 A7

The switching delay time 'and the input signal from the inverter will generate dry selection pulses at high frequencies. The other pulse interferences at the output end are changed from the first inverter group to the second inverter group, which can be adjusted by different levels of the output of the first inverter section. . The current problem can be solved by choosing a more complex demultiplexer with multiple stages. For example, 11 stages are required to give 2 ^ reverser taps. However, too long a delay time is generated in the decoder, which makes it impossible to operate the DLL memory chip at high frequencies using this circuit at the dual data rate. The object of the present invention is to describe in detail a delay circuit with adjustable delay, which is suitable for the south clock frequency and allows the delay circuit to be used in a DDR memory. ° The present invention achieves this object by a delay circuit with adjustable delay, including the following:-a first block 'has a first serially connected N-series delay element, the input of the first block The terminal and the output terminal are connected to individual taps. This tap is used to provide a delay signal to the N delay element and a clock signal provided to the input of the first block, a second block, There is a second serially connected N serial delay element between the input and output of the second block. The input of the second block is connected to the output of the first block,- A first group of switches, which are associated with the first block and have N switches with individual control inputs, another switch is connected to an individual tap of the first block, and- Two groups of switches, which are associated with the second block and have N possesses -6-This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 517459 A7 B7 V. Description of the invention (3 ) Individual control input switch 'Another switch is connected to a second The individual taps of each block and the control input of its switch are connected to the delay element. The delay element is connected to the output of the first block. In order to switch the switch at the same time, its output is connected to the control input of the switch. Its input is connected to the delay element. The delay element is connected to the input of the second block. When switching the delay time in the above delay circuit, this must be moved from one block to another. The delay circuit of the target uranium only needs to switch between the outputs of the first group of switches and the second group of switches. . However, switching is not required in the first and second group switches. This means that no interference signal will be generated, even if a high-frequency clock signal is input at the input of the first block, such as a square wave signal. In this case, with one N serial delay elements per block, the following conditions can be used to prevent interference signals:

T TD < — 2 where TD is equal to the delay time of a delay element and τ is equal to the cycle time of the clock signal. The clock signal can be input to the first block input. However, in the case of the circuit described in the introduction, based on In the prior art, the following conditions can be used to prevent interference signals: N · TD <-2 The present invention therefore allows a higher clock frequency, that is, a shorter clock period T, giving the same delay time TD. The demultiplexer of the current delay circuit is easy to drive, and the high-frequency clock signal provided to the inverter chain means that the current delay circuit is suitable for the delay phase-locked loop DLL, such as appears in double data rate, DDR memory. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 517459 A7 ___________ B7 V. Description of the invention (4) Each " " ~ ------ When a delayed signal is transmitted from the first One Ah block to two block conversion taps T 'does not need to be converted in the first and second group fine-shanbai group switches. This can be achieved by mistake, the first group switch associated with the first block 彡 g pq gq ^ φ, and the second group switch associated with the-侗 block. -Select a line, such as an LSB (least significant bit), so it is used to start or open the first solid tap to the second block, and together select a last tap to… block at the same time. This means that there is no need for any switching action on the first or first group switch, when switching from the first to the second block. > The principle described in the delay circuit with adjustable delay can naturally be extended to a delay circuit with more than two blocks. In this case, when an even block of N delay elements with a different series needs to be addressed in decreasing order, it is necessary to address an odd number of blocks separately, that is, the second and Five blocks and so on increase in sequence. When the last delay element is selected, in the ith block using the switch of the ith group, the delay signal tap point connected to the last delay element to download data It will be more accurate to select the inverter tap point at the input of the first block at the same time, that is, the connection switch of the i + 1th switch group is turned on. In a preferred embodiment of the present invention, the switches of the first group of switches are connected to the other at the first switch node, and the switches of the second group of switches are connected to the other at the second switch node, and one time is provided. The stage switch group is used to select a block, and has a first switch coupled to the output switch of the load-side delay circuit. The delay circuit developed in this way forms a demultiplexer of one or two stages, so it is particularly suitable for a DLL to delay the phase-locked loop. -8-This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X 297 mm) 517459 V. Description of the invention (5-directional device A_ ^ Best specific embodiment, & late element includes a In addition, a pair of Lianyungang, Chasha's preferred ascending embodiment, each delay element includes an inverter of ^, and there is a delay time TD between the input end and the output end.丨 / 、 Two-periodic clock shots' If a square wave clock signal is used. Connected to the input of a delay element, and then the rising edge α is the output of the pair. It is delayed for the input of the inverter pair. It is called delayed. Ascension margin, another preferred embodiment of this month, in the first and second:, and f: 'off of a three-state inverter, in the first Switching state ^ has surface impedance output. In order to select the required delay time, the switch group including the switches is present; hand ,, '/, have a low impedance, when the tap point is selected, and its /, have the same Impedance. In the case of the above specific embodiment, the high-impedance state is as simple as 4 inches. The method is generated by a three-state inverter. Another more advanced embodiment of this turtle month drives the switches in the first and second switch groups using a first bit, and uses a The switch in the secondary switching group of the second bit provides a driving circuit connected to the control input of the switch. In this example, the first bit, which can be referred to as the LSB, is the least significant bit and is simultaneously individually Use the flip to select an inverter tap point for each block. Because tap point nodes have been represented on the basis of sequential increase or decrease, however, all input tap points are given to all odd-numbered areas. The block, for example, is selected simultaneously with all the even numbers given to all outputs. The second bit, which can be referred to as the MSB, is the most significant bit, and is used to remotely select the relatively required block, which contains times Level switching group. -9-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 517459 A7 B7

In another preferred embodiment of the present invention, the number of delay elements in each delay block is greater than or equal to six. In another preferred embodiment of the present invention, the design of the delay circuit uses CMOS circuit technology (complementary metal oxide semiconductor). The circuit δ for the delay circuit uses fast and power-saving CMOS technology to allow use in large memory chips, such as DDR. Another preferred embodiment of the present invention provides one or more delay circuits in a delay phase locked loop, which may be a digital design. Another preferred embodiment of the present invention provides one or more delay-locked loops including one or more delay circuits in a DDR memory chip. A further feature of the invention is the subject matter of this patent application. The present invention is explained in more detail below in typical specific embodiments with reference to the drawings. Among them: FIG. 1 shows a simplified block diagram of a typical embodiment of a delay circuit of the invention, FIG. 2 shows a signal slot at a circuit node in a circuit selected by way of example shown in FIG. 1, and FIG. 3 shows a circuit selected from FIG. A brief history of a typical delay element in a delay circuit. Figure 4 shows the switches of a typical embodiment in the switch group from Figure 1. Figure 5 shows a typical implementation of a block containing a chain of delay elements, and connections. A switch group here, and FIG. 6 shows a typical embodiment of the switch in the form of a CMOS tri-state inverter from FIG. 4. -10- This paper size applies to China National Standard (CNS) A4 specifications (210X 297 public directors) 517459

Fig. 1 shows a delay circuit with adjustable delay, which has a first block 1 ... 2, a second block 2 and a third block 3, which are connected to each other in a series circuit. The first and second blocks, each with six delay elements, 11 to 16, 21 to 26, are connected in series with each other. The third block 3 and possibly the next block each have six delay elements, and the first in the third block 3 is labeled 31. The input of the first block can be inputted with pulse signals. The output of the first block 1 is connected to the input of the second block 2, and the output of the second block 2 is connected to the input of the third block 3. The first block 1 has six delay elements 11 to 6 and each delay element 6 to 6 has tap points for external windings at the output. In this example, the tap point on the first delay element 11 in the first block 1 is labeled 42. The first block 1 ′ and the second block 2 include six delay elements 21 to 26. The input of the delay element 26 is connected to the output of the delay element 16. The output terminal of the delay element 21 is arranged at the output terminal of the second block 2, and the input terminal of the third block is connected to the input terminal of the delay element 31. Each block 1,2,3 has a different group 4,5,6 of associated switches. The first switch group 4 is connected to the first block 1 and contains six switches S1 to S6, with individual switches s1 to S6 connected to a different tap to a delay element 11 to 16. In this case, the switch S1 is connected to the delay element 11, the switch S2 is connected to the delay element 12, and the switch S6 is connected to the delay element 16. The second switch group 5 likewise contains six switches S1 to S6 'with switch S6 connected to a tap to a delay element 26. In this case, the same reference symbols S 1 to S6 are individually labeled with switches in switch groups 4 and 5, which means that these switches have the same reference symbol at the same time as the on-11-this paper standard applies China National Standard (CNS) A4 (210 X 297 mm)

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Line 517459 A7 B7

turn off. In this case, please note that switch S6 is connected to the first switch group i.

Connected to switch S1. Out, labeled C.

All the switches 81 to% in each group of switches 4, 5, 6 are connected to each other at the nodes, respectively, and to the previous group of switches 7. The previous group of switches 7 has individual switches S 1 0, S 2 0 for switch 4, each block 1,2. In particular, in this arrangement, each group of 5 and the switch S 10 are connected to the switch group 4, and the switch S20 is connected to the switch group 5. The switches S10 and S20 are connected to each other in the previous-stage switch group 7 and to the output terminal of the delay circuit, and the output signal F delayed from the input clock signal A can be obtained therefrom. In the case of the above-mentioned specific embodiment of the delay circuit, if there is a switch-over from the tap of the delay element 16 to the tap of the delay element 26, it is only necessary to turn off the switch S10 and turn on the switch S20. Therefore, there is only one delay time between the taps of the delay elements 16 and 26. In this case, it is not necessary for switch group 4, 5 to switch one of switches s 丨 to S6 for this switch. This means that this can provide a particularly fast clock signal A. Therefore, in blocks i to 3, the addressing of the delay elements is sequentially increased or decremented. By switching groups 4 to 6, it means that a particularly fast clock signal may be used for signal A, so that the current specific embodiment Suitable for delay-locked loop DLL, giving double data rate memory, DDR. In this case, the applicable boundary strips and the paper size are applicable to the Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 517459 A7 --------- B7 V. Description of the invention (9) is no longer 6 · TD < 1 ~ 2 As usual in all blocks, the addressing method is increased one by one, but the following are used: TD < 丄 2 Clear, clear, clear; brother, the interference caused by the switch delay time The signal (pulse interference) can also be prevented by the current delay circuit in the high-speed clock. Here — the formula described by ^ / Brother 'applies to a square wave clock signal with 50% of the heart rate ^' that is, the time of the south potential and the low potential are the same 'and the time of the high potential is 50% of the clock signal time throughout the cycle. In order to drive the switches S1 to S6, S10, and S20 in the groups of switches 4 to 7, a driving circuit 50 is provided, which provides a higher significant bit and a lower significant bit MSB 'LSB to achieve driving the switches 31 to S6, si0, S20. In this case, the 'higher significant bit MSB is simultaneously the most significant bit and drives the switches S10, S20. Because only two switches are provided in a typical embodiment 'this bit MSB needs to adopt two states 1, 2. The lower significant bit LSB, the least significant bit can adopt six states to drive the individual six switches S1 to S6 ° In order to provide a better overview, select the reference number for the delay element 丨 to 1 6, 21 to 26 , 3 1 so that the latter displays the two digits to the left of the two digits driven by the MSB driven by the higher significant bits and the right digits to the right of the delay element by the lower digits LSB driven to display the two and driven. Therefore, -13-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 517459 A7 ______ B7__ V. Description of the invention (1〇) The same number of one-digit delay element tapping as the reference number Click on the individual switch group pads and always activate them individually at the same time. Figure 2 shows that the signals B, C, D, and E are delayed according to the input clock signal A. Similarly, the delayed output signal F from the delay circuit and the delay element 16 from the first block} to the second block 2 The delay element 26 in the switch generates the switching moment TS ° in this case. In this case, figure i shows the switching position before the switching moment. The signal B is a delayed clock signal and is connected to the output terminal of the delay element 16. — At this time, the pulse signal has a symmetrical duty cycle. The signal C is a clock signal 'which can be obtained at the output of the delay element 26, and is delayed relative to the signal b by the delay time TD of the delay elements 11 to 31. A delayed signal D represents the node K1 connected in common to the first group of switches 81 to S6 of the switch 4. As in the switch position described in FIG. 1, the delayed signal B is added to the switching time T of the switch S6. %. Similarly, the switches S1 to S6 in the second group of the switch 5 at the signal E of the common node K2 can be added to the delayed signal c by the switching time of the switching% _TS6. Finally, the output signal F may be added before the switching moment TS of the output node of the first group of the switch 4 to the switching time D0 of the switch si0 in the previous group of the switch 7. This is obviously the delay time TD and the switching delay time D μ. Tsw naturally causes an interference pulse (pulse interference). When using the outputs of the switches s 1 〇, s 2 0, the transition from signal D to signal E, if The signals 0 and £ are the same voltage, that is to say the same logic level, in this case the high potential. This condition can be satisfied. For an ideal duty cycle, as long as the following is true: TD < — 2 Figure 3 shows a typical, simplified circuit diagram at any extension in any block -14-This paper standard applies Chinese National Standard (CNS) A4 specification (210X297 male ------ 517459

The delay elements all have the same design and the same delay time TD. By way of example, a delay element n is shown. The delay element n includes an input terminal 8 and an output terminal 9. The input terminal 8 is connected to the output terminal of the delay element, which is connected to upload data or provide a clock signal A, and the output terminal 9 is connected to the input of the delay element. End, which is connected to the download data. Between the input terminal 8 and the output terminal 9 of the delay element, two inverters 40, 41 connected in series are provided to generate a delay time td between the input terminal 8 and the output terminal 9. At the same time, the output terminal 9 connected to the delay το member 11 is a tap 42 to give a delay signal. By way of example, the tap can be connected to the switch s 丨 and the switch 4. FIG. 4 shows a three-state inverter si, which has an input terminal 43 and an output terminal 44, and also has a control input terminal 45, 45, and a control input terminal 45 for the three-state inverter si as a complementary type. Control input 15 ′. Switch s 丨 is only shown by way of example in Figure 4, and all other switches "to" and sl0, S2O are also in the same form of the three-state inverter design. Fig. 5 has partial circuits of the first block 1 of the delay elements 11, 12, 13 and the tri-state inverters si, S2, S3. As just mentioned, the delay elements 丨 to i 3 are connected in series in a delay chain. A separate tap is provided at the output of each of the delay elements 11 to 13 and is connected to the input of the individual switch of the switch 4 group, namely the three-state inverters S1 to S3. At the outputs of the three-state inverters S1 to S3, the signal D delayed by the switch position is connected to the delay time for the clock signal A. The delay time TD of a delay element and the number of actively inserted delay elements can be Multiply by the product. Finally, Fig. 6 shows a typical embodiment of a three-state inverter, as in Fig. 4 using complementary MOS circuit technology, CMOS, and complementary metal oxide half -15- ^ Paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm)

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517459 A7 B7 V. Description of the Invention (12) · Conductor. Specifically, an inverter is provided having a PMOS transistor p 丨 and an NMOS transistor N1 'connected to each other with the transistors p1, N1, and connected to the input terminal 43 of the tri-state inverter S1. PMoS transistor? 1 is individually connected to the output terminal 44 with a control section of the & NMOS electric crystal N1. In order to form a south impedance output at the tri-state output terminal 44, further transistors p2, N2 are provided. Similarly, complementary transistor pairs and coupling inverters pi, N1 are connected to the control input terminal 45'45. In addition, 'transistors P2, N2 are connected to the supply voltage connection points 46, 46'. Reference symbol list 1 Block 2 Block 3 Block 4 Switch group 5 Switch group 6 Switch group 7 Switch group 8 Input 9 Output 40 Inverter 41 Inverter 42 Tap 43 Input 44 Output Terminal 45, 45 丨 Control input terminal -16- The paper size is suitable for the country S (CNS) A4 specification (21GX 297 public love) '----------. 517459 A7 B7 V. Description of the invention (13) 46 , 46 'supply voltage contacts N1, N2 NMOS-FET PI, P2 PMOS-FET S1 to S6 switch S10 switch S20 switch A clock signal B signal one C signal D signal E signal F output signal TD delay time T cycle time TS Switching moment TS6 Switching time Ts 1 ο Switching time-17- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm)

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Claims (1)

517459 A8 B8 C8 D8 VI. Patent application scope 1. A delay circuit with adjustable delay, including-the first block (1), with the first N serially connected delay elements (1 1 to 16) keys The input and output of the first block (丨) are connected to individual taps. This tap is used to provide a delay signal (B) to the output of the N delay elements (11 to 16), and The clock signal (Α) provided at the input of the first block (1), a second block (2) 'has a second N consecutively connected delay element (21 to 26) chain, The input and output of the two blocks (2) are connected. The input of the second block is connected to the output of the first block (1), a first switch group (4 ), Which is related to the first block ㈠) and has N switches (s 丨 to S6) with individual control inputs, and another switch (S1 to S6) is connected to a first block (1) individual taps, and a second switch group (5), which is associated with the second block (2), and has N Switch (S1 to S6) of the control input, another switch (S1 to S6) is connected to the individual tap of the second block (2), and the control input of its switch (S6) is connected to the delay element (16) For the tap, the delay element is connected to the output of the first connected block. In order to switch the switch (S6) at the same time, its output is connected to the control input of the switch (S6), and its input is connected. To the tap of the delay element, the delay element (26) is connected to the input of the second block (2). 2. If the delay circuit of the first scope of the patent application is characterized by -18-This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 517459 AB c D 6. Apply for patents for switches (S 1 to S 6) in the first switch group (4), at the first switch node ( κι) are connected to each other, to the switches (81 to S6) of the second switch group (5), to each other at the second switch node (K2), and to provide a block for selecting a block (1, 2) The front-stage switch group (7) has a first switch (S10) coupled to a first switch node (κ ΐ) An output connection to the load-side delay circuit, and an output connection with a second switch (S20) coupling the second switch node (K2) to the load-side delay circuit. Or the delay circuit of item 2, characterized in that the delay element (11 to 16, 21 to 26) contains another inverter. 4. If the delay circuit of item 1 or item 2 of the scope of patent application, its characteristics The delay elements (11 to 16, 21 to 26) each include a pair of continuously connected inverters' to form a delay time TD (TD) between the input and output of the delay element. 5. The delay circuit of item 1. or item 2 of the scope of patent application, characterized in that the switches (s 丨 to S6) in the first and second groups of switches (4, 5) are one to three State inverter with high impedance output in the first switching state. 6. If the delay circuit of the first or second item of the patent application scope is characterized in that a driving circuit (50) is provided in the first and second groups of the switches (4, 5) to drive the switches (S1 to S6), using a first bit (LSB), and driving the switch (S10, S20) in the previous switch group (7), using a second bit (MSB), the driving circuit (50) is connected to the switch (S1 to%, S 10, S20). 7. If the delay circuit of the first or second item of the scope of patent application is applied, it is characterized by -19- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 517459 8 8 8 8 AB c D "The number of delay elements in each block (1, 2) of the scope of patent application is greater than or equal to 6. 8. If the delay circuit of item 1 or 2 of the scope of patent application is characterized in that the delay circuit uses complementary driving metals Technical design of oxide semiconductor circuits. -20- This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm)