WO2002052725A2

WO2002052725A2 - Delay circuit having adjustable delay

Info

Publication number: WO2002052725A2
Application number: PCT/DE2001/004311
Authority: WO
Inventors: Thomas Hein; Patrick Heyne; Thilo Marx; Torsten Partsch
Original assignee: Infineon Technologies Ag
Priority date: 2000-12-27
Filing date: 2001-11-15
Publication date: 2002-07-04
Also published as: TW517459B; DE10065376C1; WO2002052725A3

Abstract

The invention relates to a delay circuit having adjustable delay. The delay circuit comprises a first block (1) and a second block (2) that is connected in outgoing circuit thereto. Said blocks each have a chain of delay elements (11 to 16, 21 to 26). A switch group (4, 5) is assigned to each block and enables output-side taps on the delay elements (11 to 16, 21 to 26) to be selected by means of switches (S1 to S6) in order to be able to select a desired delay time. In order to simultaneously control the switch (S6), which is connected to the output-side delay element (16) of the first block (1), and the switch (S6), which is connected to the input-side delay element (26) of the second block (2), the control inputs of these switches are connected to one another. This prevents the occurrence of disturbing pulses also in the event of high clock-pulse rates of clock signals (A) that can be applied to the delay elements on the input side. For this reason, the inventive delay circuit is suited especially for use in delay closed loops in DDR memory chips.

Description

description

Delay circuit with adjustable delay

The present invention relates to a delay circuit with adjustable delay.

In order to provide a variable delay time, digitally operating delay locked loops (DLL, Delay Locked Loop) usually have an inverter chain with a large number of inverters connected in series, which has signal taps at different circuit nodes of the inverter chain. The delay time can accordingly be set by selecting a tap node. Signal run times are used by the various inverters or inverter groups.

To select the tap point, a demultiplexer is usually provided, the inputs of which are connected to the tap points and a signal with a set, desired delay time can be tapped at the output thereof. In order to reduce the control signals of the demultiplexer, the demultiplexer is preferably designed in several stages, for example in two stages. In each case, inverter blocks can be formed with N inverters connected in series.

Such a delay control loop is specified in document EP 1039637 A1, in which an inverter chain is provided with a multiplicity of hierarchically arranged 2: 1 multiplexers for digital setting of a delay time, cf. Figures 1 and 4.

In the case of a two-stage execution of the selection circuit in the demultiplexer, a higher selection of a tap point is made in a first selection level, for example with a first selection line or a first selection bit, by selecting an inverter block, while a second selection line or a second selection bit enable the selection of a tap node within a block selected with the higher-level circuit. With the second selection line, all first, second, third et cetera tap nodes of all blocks are selected.

The problem can arise that when switching from one inverter group to another, a plurality of switches have to be actuated simultaneously, so that inter alia interference pulses can occur at the output due to switch runtimes and at high frequencies of a clock pulse of an input signal of an input signal. Other causes of a glitch at the output can be caused by different levels on the output side of inverter groups of a first stage at the time of switching from a first to a second inverter group.

The present problem could be solved by selecting a more complex, multi-stage demultiplexer which, for example, has to be n-stage for 2 ⁿ inverter taps. However, this results in such a long delay time in the demultiplexer that the use of such a circuit in double data rate, DLL memory chips at a high operating frequency is excluded.

The object of the present invention is to provide a delay circuit with adjustable delay, which is suitable for a high clock frequency and enables the use of the delay circuit in DDR memories.

According to the invention, the object is achieved by a delay circuit with adjustable delay, comprising - a first block with a first chain of N delay elements connected in series between the input and output of the first block, one tap for each on the output side of the N delay elements a delayed signal is provided and a clock signal can be fed to the first block on the input side,

a second block with a second chain of N delay elements connected in series between the input and output of the second block, the delay elements of which are connected to the output of the first block,

- A first switch group assigned to the first block with N switches, each with a control input, whereby one switch is connected to a tap of the first block and - A second switch group assigned to the second block, with N switches, each with a control input, one switch each is connected to a tap of the second block and the control input of the switch connected to the delay element connected to the output of the first block is connected to the control input of the switch connected to the delay element connected to the input of the second block for simultaneous switching of the switches.

When switching the delay time in accordance with the delay circuit described so that the transition from one block to another block is required, in the present delay circuit it is only necessary to switch between outputs of the first switch group and the second switch group. However, no switching is required within the first and second switch groups. As a result, no interference signals can occur even at high clock rates of a clock signal that can be applied to the input of the first block, for example a square wave signal. With a chain of N delay elements per block, the following now applies to avoid

Interference signals the condition

T TD <-

2

with TD = delay time of a delay element and T = period of the input block on the first block Clock signal, while in the circuit described above according to the prior art to avoid interference signals the condition

N - TD <~

2

must apply. Accordingly, with the present invention, higher clock frequencies, that is, smaller clock periods T, are possible with the same delay time TD. Due to the easily controllable demultiplexer of the present delay circuit, as well as the high possible clock rates of the clock signal that can be supplied to the inverter chains, the present delay circuit is suitable for use in delay locked loops, DLL, Delay Locked Loop, as used in double data rate, DDR memories occurrence.

When switching the tap for a delayed signal from the first block to the second block, no switching in the first and second switching groups is required. This is achieved in that the addressing of the first switch group, which is assigned to the first block, takes place in ascending order, while the addressing of the second switch group, which is assigned to the second block, takes place in descending order. Via a selection line or a bit, for example an LSD (Least Significant Bit), the first tap of the second block is simultaneously activated or switched on together with the selection of a last tap of the first block. This eliminates the need for a switching operation in both the first and the second switch group when switching from the first to the second block.

The principle of the delay circuit with adjustable delay described can of course be extended to delay circuits with more than two blocks. The blocks with an odd number, i.e. 1st, 3rd, 5th block and so on, are to be addressed in ascending order, while the even blocks are addressed with one

• σ N SD P CQ ü N t P- <H LQ X <P. LQ & t μ- μ- CQ Pi H co PJ Φ 0 0 N N «

P> rf 0 Φ Φ 0 = μ- Φ 0 Φ 0 Φ φ Φ Φ fl) Φ Φ CQ rf 0 Ω 0 μ- φ PJ o = 0 Φ

PJ IQ CQ li μ- 0 LQ P 0 ü Φ ü H li CQ H 0 0 rf Φ 0 tr CQ 3 Ω LQ rf

H I- ¹ tQ rf LQ Φ rf Φ N Φ μ- ^• »N rf 0 Ω φ 0 LQ φ J LQ LQ tr φ PJ rf μ- DJ ι-3 μ- CQ ü Φ td μ- 0 = μ- LQ o = <CQ 0 Φ f ^» r Φ μ- μ- Φ J μ- LQ H D. Φ

Ω P PJ LQ LQ 0 ii li 0 LQ 0 0 £. LQ Φ φ LQ ti CQ μ- 0 to CQ 0 rf S 0 1 Φ 0 t

Φ tT LQ - 1- "P Φ Hl φ Φ φ Φ μ- Φ H μ- CQ CQ φ Ω μ- φ LQ PJ: LQ rf CQ 0 Φ <J fi CQ rf r μ- LQ μ- μ- HM fi rf φ HN et CQ et <φ 3 tr 0 ti t tr CQ Φ Ω LQ CQ 0

N p. CQ T φ Φ CQ P P 0 0 0 = μ- Ω Φ o P> Pi 0 CQ 0 tr CQ CQ 0

0 = Φ Φ Φ μ- D- NP ⁾ p. s; 0 ^ μ- φ 0 LQ LQ tr 0 H 0 = N tr TS rf Φ P ⁾ LQ μ-

IQ fi H- fi CQ φ Φ 0 0 Φ LQ Φ Q H LQ Φ PJ LQ r ≤ rf α Φ • Ö - μ- Öd Φ ≥!

Φ rf μ- 3 CQ μ- P. 0 μ- CQ μ- rf CQ H, Cb ω Φ Φ Φ X μ- <Φ rf rf μ- fi fi SU H- 0 μ- rf Φ LQ rf LQ rf • tr CQ 0 Φ rf Ω CQ H μ- 0 φ 0 Pi H- 0 Φ φ Φ <rf 0 Q P. φ tr Φ φ Φ Ω 0 0 0 tr Φ LQ et 0 ti Φ PJ LQ Ω rf Pi 0 Φ

• CQ Φ PJ t-3 LQ li μ- i CQ tr LQ 0 J tr φ Φ et o N μ- CQ X Φ φ f rf P> Q tr α Φ 3 Φ Φ φ 0 PJ CQ N LQ Φ 0 0 Φ Ω 0 0 P> 0 CQ CQ N

Φ 3 H3 S Φ CQ Hl 0 0 0 CQ ^ rf li 0 tr LQ LQ tr 3 3 - μ- 0 =

H- φ 0 N Ω ^ Φ rf Ω Φ X X Di co PJ rf Φ Φ μ- 0 LQ

IQ H PJ μ- g, tr CQ ü φ 0 tr μ- 0 0 3 0 Ω 0 Φ CQ μ- μ- rf tr LQ Di Φ

Φ 3 3 CQ μ- PJ ß tr tr H 0 P> rf TS 0 μ- Φ tr 0 rf 0 Ω CΛ rf LQ Φ H

3 <! LQ φ s; CQ Φ Φ ι_ι. φ CQ LQ Φ TJ rf rf rf P ⁾ D Φ tr rf + Φ Ü 0 0 p. Φ Φ μ- Ω rf 0 <Φ rf 0 φ Φ Φ ii! P ⁾ μ- P ⁾ 0

Φ fi φ ii t φ 0 0 N tr 0 0 φ rf Di 0 ¹ CQ Hi 0 Φ LQ

0 rf Φ μ- P- φ rf D- H Φ ii 0 μ- 0 CQ rf μ- to X μ- CQ rf Φ • Hi Φ l CQ

Φ LQ 0 P φ μ- N μ- N t LQ Ω 3 0 Ω 0 φ Φ Hl Φ fi P. φ li J LQ f rf PJ H φ p: 0 0 P ^ tr 0 μ- φ tr 0 H 0 = rf td φ CQ ii

• O ^• «H 0 td LQ Φ LQ φ X P> 0 et 3 J rf CQ tr N (- ^■ Hj D. et H- JP> φ μ- H <rf 0 rf 0 rf O P. Φ Ω Φ H μ - 0 o Hi Φ Φ

3 P> CQ Ω φ 0 0 φ Φ Φ € * Ö rf Φ Φ rf 0 tr ti 0 CQ LQ Ω μ- 0 = CQ Pi t fi 0 ET μ- LQ <H 0 H 0 φ Φ OX 3 μ- Φ PJ CQ 0 rf Φ? 1 ü Pi Φ Π

Φ rf 0 PJ Φ N 0 0 μ- Φ 0 μ- 0 CQ ü 3 rf LQ • 0 rf Pi J

0 μ- Φ 0 => <! P ^ 0 0 rf φ rf LQ μ- et Φ CQ H i Φ Φ Φ CΛ 0

Φ 3 Q Ω <LQ rf LQ P φ 0 Φ rf rf 3 Φ J et Φ 0 Hi P <0 μ- 3

H- rf X φ Φ φ CQ CQ 0 0 • Φ Φ 0 0 Φ i 0 0 LQ 0 tr μ-

3 D- Hl h 0 fi Hl et Hl LQ 0 μ-> * σ μ- CO ü Φ φ to Φ 0

IQ μ-. 0 = N P 0 fr Φ 0 = N σ 0 0 cn w 0 P. Ω 3 rf 0 Ω <! Φ μ-

0 ⁾ Φ μ- ü 0 = P. 0 tr H t μ- $. μ- 3 φ CQ Ω Φ PJ Φ tr Φ H tr φ rf P ⁾

0 Φ 3 LQ P. LQ H • H 0 Φ φ μ- 3 LQ tr 0 H J Pi Pi J H N> tr

IQ <! μ- Φ H- CQ c: μ- et PJ PJ N Di Φ co 0 H N rf 0 CQ

CQ φ SD LQ fi 0 Φ LQ 0 0 ö Q P. N 0 0 Φ N rf ü Ω φ rf 0 = Φ to rf

CQ H 0 Φ 0 CQ LQ LQ I ¹ rf φ D. $, LQ rf 3 H ≤ φ tr rf φ LQ 0 ^ φ

Φ N CQ CQ LQ CQ μ- CQ CQ tr ¹ 0 ü Φ Φ CQ Φ Φ H <! PJ Φ h Φ J μ-

H- 0 = rf LQ P> Φ φ Hl Hl Hi PJ 3 μ- P> li> <μ- LQ O LQ H <tr LQ rf LQ Φ ι-3 CQ P 3 P- 0 0 μ- li rt 0 • > 0 Φ rf li li r H fi rf Φ Φ

H- Φ μ- J ^ Ώ LQ Φ Φ 4 ü ö LQ rf> Φ CQ CQ li Φ 0 H Φ 0 0 φ li 0 il LQ X μ- ü 3 3 φ Φ 0 0 Ω D.% tr 0 Ti μ - H <<X5 CQ N Pi Pi

0 Φ rf μ- D- 0 0 ^ CO tr Φ P ⁾ = 0 O φ Φ J 0 = Φ Φ

0 ⁾ 0 0 CQ φ Φ CQ. 0 P ⁾ Φ LQ CO H tr 0 to Φ LQ Pi li Φ to LQ CQ li

3 LQ Ω. μ- Di CQ P ⁾ Φ Φ 3 ^ ü μ- PJ Ω 0 Di Ω Φ Φ rf μ- Φ

CQ φ LQ 3 ii Hl Φ et 0 t &> Φ Φ tr μ- 0 t Φ N LQ H fö

HN 0 φ <Φ ⁾ f 3 ω LQ J PJ 0 P PJ 0 D ü 0 0 0 Φ Φ

P Φ f P ⁾ μ- Φ Φ μ- <CQ 0 0 ii CQ D ⁱ CQ - _' Φ μ- J CQ J 0 rf H-

<! μ- 0 H μ- 0 0 CQ Ω LQ J rf Φ rf Φ rf Φ 0 tr LQ N tr

0 er 0 ⁾ LQ NPH Φ X rf Φ 0 Φ Hi CQ μ- 0 Φ μ- + LQ Φ CQ rf φ fi 0 3 P> o = φ ^► 0 0 φ μ- tr CQ ü φ 0 0 HHH μ- H - CQ Φ rf H3 X μ- P LQ PJ μ- P. »d μ- Ω <μ- φ D- LQ φ HH μ- Ω 0 0 Hl

Φ ö Φ rf LQ Φ PJ φ P * h- ¹ tr Φ rf CQ H 3 Hi • Hi tr μ- 0

H CQ 1 φ i LQ μ- t ¹ Φ P. li μ- Φ 0 μ- Hl Φ φ <

1 er Φ 1 li Φ φ 0 1 Φ 0 Φ N LQ CQ Ό φ 0 Pi μ- Pi Φ LQ

Φ μ- 1 0 0 rf Λ li 0 = ü i Φ 1 li Φ

1 i • P Φ 1 φ 1 I

1 1 1 1 4J 4J 1 1

0 rH 1 1 «. Φ 0 1 1 .. φ TJ 1 0 0 0 _^ 0 H Φ rö 1 rA 01 Λ 1 Φ SH SH PQ -n rö 0 3 M rö Φ Φ Φ, _^ -HH Dl -0 Φ Φ fÖ -H 0 0 4J Φ Φ CO P Φ Φ Φ υ Di -n tn SH 0

Φ υ tn XJ ε -H -H -H 0 J -H tn ^ - Xi ^ -i -H Φ φ 0 Dl Φ

© -H CO 3 U X! Φ 4H Φ = 0 Φ SH Φ • -H ü Φ 4H Φ -H SH -rl 4-> 0 SH H rH Φ SH CO 0 Tj SH SH 5 4-> Φ CQ Ά 4J Φ rö -rl CQ -H 4 -> rH Φ rH U 0 Φ o ω SH 0 0 φ SH Φ HN SH CQ TA rö SH 4-> φ 0 X! SH TJ SH 0 4-> TJ

0 Φ -H TJ Φ Φ ^• H 4-) Φ

Q 0 rö TJ Φ CQ Φ Φ Dl ü. 0 Φ 0 TJ rH

> - * -> Φ i TJ Φ SH SH T TJ 0 -H 4H CQ tn M -H CQ 4J> -H> 1 0 ro 4->

H -H rH D. φ Λ Φ Φ 0 Φ CQ TJ 4J 0 -H 0 o CO 0 CO 0 X! X!

U Φ 0 -0 0 -H> TJ 0 SH Φ tn Φ SH X rö φ Nl = 0 = 0 r SH Dl SH O υ u ü α. Φ ^■ ? - f fÖ SH 0 T 0 Φ 0 0 i -H φ ^■ rH 4-> = rö Φ CQ Φ S -H CQ -rl

Tj N & Dl SH H 3 0 4-> -H = rö υ & ι-i TJ CQ Φ PQ CQ Φ T Dl TJ o 3 CQ rH

4-> CQ SH CQ -H 1 SH Φ rH Φ tn φ 0 rH M O tn φ 0 Φ tn Dl ε TJ -H 0 Φ 4H £ Φ O 4J rö 0 φ «. CQ r-l Φ ü 0 S tn B 0 ε 0 co 0 = o

0 3 <4-> 4H 4-> 4H CQ XI 4-1 -H & 0 Φ -H = 0 φ CQ CQ SH SH SH -H 0 ε

0 0 H -HT rö CQ SH U -H Φ 0 J CQ ft TJ _^ ri 0 0 Φ 0 φ SH in

4H 4J! H f SH 0 4J Dl Φ co m SH _^ rö ü xi CQ PQ rö ffl -H rö 4H Dl • 4H Dl J Φ Φ

CQ 0 Φ 0. Dl ro CQ 0 φ 4_> M 0 o -H SH CO Φ CQ = 0 CQ CQ 0 -H Dl

01 Φ T tq o Λ 4-> -H 0 SH SH 0 0 -H! -A Φ Φ 0 Φ S Φ Dl N X! Tue 0 ix! = 0 sts

0 J rH CO ^ CQ SH SH Φ Φ Φ Φ PQ 0 PQ 5 Λ Φ Dl φ D. 0 in ü 0 4-1 o N -H •

0 CQ -rl. 0 EH - TJ TJ 4-> 4-> Φ rQ TJ CQ -n Di 0 $> φ 0 -i SH 0 Pi rQ Oil H. CQ N = 0 -H co 0 TJ 0 rö 0 rö SH rH 0 SH> CQ SH rö Φ Xi P i Φ φ 0 Φ Φ 3 • 4H SH TJ Φ Φ SH SH Φ SH Φ fÖ SH SH Xi X! Xi ro> CJ P

= 0 tn fÖ TJ T φ Φ 4-> CQ Φ 0 S 0 4-> Φ D. X! TJ Φ Φ tn = 0 Xi = 0 ü 4-) φ

4-1 CQ 01 Dl 0 0 4-> 0 N φ CQ ^ ü SH Dl rH CQ TJ 4-> 4H Φ ü 4H CQ φ SH EH Φ

CQ Φ 0 CQ 0 rH -H -H Φ; rH TJ SH 4H O Φ 0 rö Φ ^ -t CQ TJ -rl CQ CQ 1 -H

0 -H X! Office 4J s Φ

0 T fÖ 3 Φ 4J 4H TJ £ 0 Xi TJ rö 0 Φ 0 tn TJ CO

, rö r0 CQ 0 XI -H φ 4-> φ Φ 0 J SH i ι ~ i rH 0 s o

ΪH TJ & 0 4-> -H Φ U PQ 0 -H ε 0 SH -n ^ SH Φ rH -HU r Dl 0 SH 0 2 CQ O £ Φ Φ 0 0 CQ Xi -H -P CO -H 3 Φ XI tn TJ Φ 4H Φ CO 0 rö 0 rö rö CJ D,

Φ 4 4-> Φ -H 0 ü 3 fÖ 4H 0 Φ TJ U Λ Φ 0 rH 4H Φ N Φ Φ 4 rQ -H

4-) rH SH Oil CQ <0 Φ rö SH φ Φ -H rö M -H rH -H _^ 0 4-1 0 φ 4-> Dl 0 4H SH Xi

L71 rö Φ -H, 3 SH J Φ 4J 4J X! 4-> Φ V CQ rö SH _^ 0 Φ Di sC T tn = 0 Φ 0 Φ υ

0 Xi> ε 4-> -H SH rH TJ CQ -H υ -H N Φ = 0 Dl 4-) 0 4-) 0 0 0 N 3 rö TJ

N u 0, 0 -H Φ SH 0 φ -H SH 3 rH S Φ 4J <- 4-> Φ rQ -rH fö Φ N Φ N SH Φ CQ 0 Φ

SH co H 0 Φ Λ Φ 4H CQ Φ Dl Φ φ i SH PQ 4H <PQ M 0 -H SH Φ rH tn Φ xi

0 1 -0 NP CQ 4-) 0 Φ ^< :. Φ φ 4H TJ 0 TJ Φ 0>& 0 SH u

> φ Φ ü CQ Φ Dl Φ SH 0 ε P. 4 _* . SH -H -rl 0 0 0 SH> c £> 3 0 rö -H φ -H 4-) o Dl - • 0 12 O SH Φ D, _* . CQ 4J 0 Φ CQ SH Φ φ φ 0 Φ 4J = 0 φ Φ 0 4-> D. φ

Tj ro, 0 0 υ Tj 0> Φ 0 0 0 -H -H H TJ CQ tn tn 4-> TJ Φ rQ Dl SH rQ -H tυ CQ P4

4-> 0 rH 0 SH SH 0 ^• H φ PQ Φ Λ -H -H SH tn = fÖ Dl TJ ~ - rö 3 CO

~ TJ CQ Tj SH Φ -H Xi Φ _^ Φ Φ tn i 0 0 0 in <4J Φ Φ SH _^ SH _^ i 0 1

0 0 -H 0 Φ CQ = 0, 0 0 4 4-> Φ Φ 4 -H Φ TJ -H 5 & Φ 0 4-> M 0 4J r υ SH 0

Φ -H ⁽ Ö Di 4H ü Φ CQ 4-1 rH CQ J 0 Φ 4-1 rö 0 Φ N rQ Φ Φ υ Φ CQ -H o 4-> Φ

SH CQ EH 4-> = 0 Dl CQ rö SH 0 -rl rö Φ 0 fÖ 0 Φ CQ 4-> = 0 SH rQ 0 SH -H 0 CQ CQ

Φ CQ N 0 -H 0 4H Φ 3 xi Dl 0 ΓJ X! 0 TJ Di CQ 3 Φ Φ r-H Φ Xi SH CQ

4J n CQ 0 SH φ 3 0 4-> ü SH Q -H ü M 0 -rl tn φ 0 SH 4-) Oil rQ 4-> Dl ü Φ TJ rö

-H 0 H N Φ Xi xi -H -H SH Φ CQ 0 SH 4H -H CQ Φ 4-> 0 TJ X! Φ -H 0 CQ -H 0 φ R 0 £

Φ 0 rö 4> Φ 0 0 Φ φ 0 Di> Φ -H Φ 4H Dl -H rö U TJ Φ 0 Dl Φ 0 4 0

& Tj rH CQ xi Φ & tsi Di 0> 0 rH 4H -rl φ Dl 4J -rl TJ 0 5 J CQ • 0

0 Φ fÖ 0 Φ ü 0 CQ 0 Φ Di tn Dl -rl Φ CQ CQ -H φ 4-) 0 0 0 Di 4-> SH -rl

SH -H Di Xi φ oil 0 Φ SH SH 4 4J 0 -H P SH 4J CQ 0 S N -H SH -H SH SH -H 0 0 Φ

Φ 4-1 D. ü - SH i -D Φ Φ CQ Dl Φ 0 Φ CO N tn CQ Dl f φ ε φ 4H Φ φ 4H 0 rö r-i N

0 0 CO, 0 0 Φ TJ 0 ^• H 4J 0 4-> 4J Λ 0 • rQ 0 SH Dl 0 SH 4J rQ rH 4->

-HW SH ü> 4-) -H 0 -H rH TJ rH 4J CQ <rö rö 0 4 X -H --o -H m -i Φ φ rö o Φ Dl 0 CQ CQ 0 Φ Dl rö SH rö rö CQ rH Dl φ .. u Φ N Φ red 0 CQ

O 0 SH Φ 0 0 xi CQ 0 xi O X! i fÖ -H φ TJ 0 rH Φ 4-) 0 0 SH 0 Xi 4H xi 0

0 Φ Φ 4 = 0 Φ 0 u Φ 0 0 CJ Φ υ υ Φ Φ -H 0 -H ^ - {-H rH 0 Φ Φ 0 φ o 0 ü -H

H Tj 4J CQ £ 4J CQ CQ .Q H TJ co Di CQ co (0 S TJ 0 Φ rö 4-> PQ PQ H TJ> H TJ o rö CQ M

In a further preferred embodiment of the invention, one or more delay circuits are provided in a delay locked loop, which can be constructed digitally.

In a further, preferred embodiment of the present invention, one or more delay control loops with one or more delay circuits are provided in a DDR memory chip.

Further details of the invention are the subject of the dependent claims.

The invention is explained in more detail using an exemplary embodiment with reference to the drawings.

Show it:

FIG. 1 shows a simplified block diagram of an exemplary embodiment of a delay circuit according to the invention,

FIG. 2 shows the signal curve at exemplary selected circuit nodes of the circuit according to FIG. 1,

3 shows the schematic structure of an exemplary delay element of the delay circuit of FIG. 1,

FIG. 4 shows an exemplary embodiment of a switch of the switching groups from FIG. 1,

FIG. 5 shows the exemplary implementation of a block with a chain of delay elements and a switch group and connected thereto H 1 SH SH rl 3 J φ

H H 1 H CQ Φ Φ 0 1 1 CQ 1 ro 0 4J

"ψ CM 1 ro SH rH Dl P H H T φ CQ rl 0 φ X 0 0 -rl -rl

SH 01 CQ SH CQ 0 4-1 CQ Φ 0 Φ TJ 0 B φ rH tn ü -rl rH φ φ

SH Φ J 0 -i φ 01 4-> -H CQ Φ> SH rö • CQ - -H -H> Xi 0 0 φ CQ co CM -ä rQ

Dl rö 0 4-> φ Φ r0 0 3 cn TJ CQ CQ

-H rQ rH r-l £ -H J rl 4-> H 01 φ 0 -H J rH CQ Φ -H 0 Φ VO -rι 0 Φ TJ Φ 0

O rH PQ rö Φ rH -H Φ m CQ 0 CQ -H rö 0 m Dl vo P 4->> Dl 0 SH 4-> Φ -H _^ 0 rH Xi -n tn • -i 01 -H CQ rö X -l 4-> rH 0 CM -H 0 _^ Φ -rl Φ rH -HP VD

H 0 Φ 0 υ CQ Dl = 0 CQ X Dl υ Dl o rl PQ 0 0 Φ Dl rö IT) 4- ⁾ φ tn rö rH CO VO

U 0 4-> Φ CQ 0 tn -Ό N X H V CQ 0 CQ H Xi Φ SH TJ 4-> CQ 0 CQ rQ = 0 X! tn • CM

PH> CQ 4J 0 Φ 0 ε SH υ O 0 rH tn = 0 0 4-> Φ Φ CQ CQ rö X »in 0 N J CQ 0 CQ

0 -H Φ CQ 0 Φ 0 CQ - {<q 0 CQ 4H Φ CQ Di -rl -H 01 Dl CJ "Φ r5 SH co Di Φ -H TJ

CQ -H φ -H -H SH Φ> r- X PQ 0 -H Φ 4 SH = 0 rH 0 0 0 Φ 0 CQ rQ Φ

SH φ r5 SH Φ Φ -H PQ J SH 0 SH rQ Dl CQ Φ N Dl 0 rö -rl rH φ 3 »> 4-> 0 CQ -rl

Φ IS1 Φ £ tn £ CQ 0 0 Φ Φ Φ CQ SH SH CQ φ 01 H PQ D. Φ vo CQ SH 0 H rH

4-> 4-> co = 0 0 Xi 0 ri φ TJ 4 Dl rH 0 Φ ε Φ Dl CQ CQ D. TJ CO CQ -H Φ rH CO 0 ι- \ -rl 3 CM N CQ CJ φ PQ 4- 1 4-1 = o rH rö 0> 0 CQ 0 ε 0 0 Φ Oi i CQ rö 3 Φ SH SH Φ 4-> CQ J -HN SH CQ N 0 0 rö Φ SH 4J CQ 0 -H = 0 υ SH 0

X! 0 Φ _^ Φ cn CQ 4-> 0 SH 0 SH SH TJ Φ Φ CQ SH rH TJ 4 Dl -rl -H -rl Φ N CQ Φ 0 u Di -rl 0 rH> -H Φ Φ 0 TJ Φ Φ Xi T Φ X! Φ X! CQ 4-> SH B rQ φ rQ SH φ 4-> 0 o 0 φ -rl X Φ SH 4J> -H -H υ tn ü φ 4-) -H φ rö φ Dl rA SH

0 φ φ Φ ü -n TJ CQ CQ CM CQ rH rH Di Φ = 0 CQ xi -rl SH 4-) 4-) H 4H P> 0 rö Φ

CQ. 4-> _^ X 4-> 0 SH φ φ CQ Dl Φ H o CQ N Φ J 3 TJ rH CQ O 4H rö X! t φ rH H 0 Ό Φ rH CQ CQ Φ TJ CQ J Xi CQ Xi rH tn rH rö - -H 3 u = 0

TJ Φ rö -H = 0 4-> PQ rH Φ X υ oil CJ TJ rö CQ Φ 0 Φ 4-> 3 Xi SH 4-) rö o co N

4J X! Λi r- rl <- \ TJ CQ tn ü Dl Φ 0 rA Φ 0 rH> rö CQ -rl ü 'Φ φ Di CQ H SH -λ SH υ ü Φ PQ rö Φ rö Φ 0 O 0 CQ 0 Φ -H «R -H co 4J ä -H CM CQ Φ φ Φ CQ 0 Xi i 4J 4H φ TJ rö lH rö SH 5 rH rö 0 o - n Φ rA co T -l>

-H> CQ rH υ φ CJ 4J 0 4-) tn PQ tn 4J φ Di 0 4H O rl rH _^ - l Φ Di rö 0 φ rA

00 _ft 0 tn CQ <-t -H CQ -H Φ CQ Dl CQ 0 CQ Di _^ CQ H 0> CM 4J -P 0 D, i 0 Φ SH -H rö 0

CQ H 0 Φ P SH rQ SH 0 0 0 - l -H = 0 4J Di Φ TJ CQ -H -H 0 ü φ CQ φ r-l 4H O

-H 1 0 0 £ Φ TJ φ Φ rö Φ W Φ N CQ 0 • rQ tn φ CQ -H φ Φ SH co 0 CQ 4 tn 0>

Φ φ Φ •> Dl 4-) SH -rl 0 4-> φ 0 -rl Φ CQ tn -rl 0 rH CQ Φ rQ 4-> φ 4-> ~ TJ 0 CQ 0 SH -rl ε Φ φ SH Φ rö rH J 4 CQ Φ CQ φ -l πJ Dl rQ 4H

CQ rö tn CQ m 0 SH Φ φ rö -rl Φ φ Φ H> 3 = Φ 0 CM tn tn Φ Φ 01 -n Φ Xi Xi X! 0 Φ 4H

Dl 4-) = θ SH -H φ P CQ Tj m P £ 0 4H tn X! 0 CQ -H 0 0 4-> υ φ J υ 0 -H

0 CQ N Φ X CQ TJ -H N -H CQ 0 = 0 υ X tn r-l T rö 4 - Φ -n CQ co SH 4J SH

0 -H SH υ 0 Φ 0 0 • Φ CJ Φ ö N -rl ü H 0 01 SH Dl CQ rö CQ Φ φ 03 t

SH SH φ 3 0 0 rö 4H £ Φ Φ SH CQ O TJ SH φ 0 0 CQ 0 0 -rl Xi 0 tn>. tn rö r EH> Φ r-l Φ 0 0 0 TJ rö Φ 4-> rH Φ 4H φ N rH SH SH tn Φ -H υ 4-> rö 0 H = 0 4H

= 0 0 PQ TJ -rl rö Φ Φ rQ TJ -rl CQ -r-ι 4H> φ PQ Φ Φ 0 tn Φ cn O c rö rH N 3 ä

4H CO Φ - l 0 Φ X T 0 Dl B -rl rQ TJ tn 0 0 rö VD SH 0 0

CQ o 0 Φ 0 0 4-> vo υ Φ 01 Φ -H SH 0 Φ = 0 SH rö H _^ Φ 4H CO vo TJ Φ Φ

0 2 -H Φ rQ -rl CM = 0 0 rH 0 CM 4-) Φ tn Φ CM 4J -H N Φ cn CM 4J 3 H φ> LΩ T! J Φ 4-> 4-> SH 3 rH 0 • 0 rö CQ rQ rQ 4J -rl Φ SH tn CM CQ 0 CQ -rH

-H 4 Φ CQ PQ> 4J red CQ SH 0 CQ φ rQ Φ = 0 TJ _^ SH -H CQ rH 3 Φ 0

0 CQ 4-) 3 -H> CQ 0 Φ SH 4-> £ 0> N X Φ rH Φ TJ rQ -H tn rö P. rö

-H rH 01 SH! ~ RQ φ _^ -rl -H u 0 Φ -rl N rl CJ -rl 0 rQ CQ D.

Φ rö -rl Di T Φ TJ 4H H 0 SH .. Φ 3 0 Φ 0 r-i X φ 0 H tn vo 0 vo

Φ 0 Φ -HH 0 0 4-> rH rl Φ 4H 0 ε SH _^ 0> r- Dl CJ -H CO H 0 co co

N 0 3 TJ SH CM Φ rö Φ rö 3 PQ P 0 -rl rö -H Φ vo> PQ CQ 0 P 0 rH 0 Di

SH Φ 0 Φ D 0 0 Φ rö Φ Φ TJ CM CQ 01 rH φ SH SH SH SH SH rN VD H Φ 0 rö CQ>. r-l SH Xi tn 0 0 • 4H rQ 01 Φ 0 0 PQ. TJ Φ CQ Φ Φ Φ Φ

SH ^■ -0 φ -H CQ H 4H TJ -rl CQ Φ 4 Φ H -H -H TJ <-rl rö 4-) in 3 Φ 0 r- {TJ = 0 ι- \ rl rH

O Dl tn SH TJ 4J ü CQ J -H N X 4-) Φ 0 CQ -rl tn 4-1 4H Q 0 Φ 01 0 TJ TJ SH r0 -rl SH r Xi i

-H -rl Φ 0 -H φ -rl rö rH φ rö -H £ 0 -H φ rQ CQ ε rl 0 rö 3 = = 0 Φ Φ SH Φ ü rH φ ü υ ü H PH> 0 3 CQ rQ 0 tn rQ EH ε NX) rQ CQ -H 0 CM <tn N rj 0> co tn> co co co

LD o IT) o

HH CM ro ro

Switch Sl is connected to the tap of delay element 21. The same switch reference symbols S1 to S6 in switch groups 4 and 5 each designate switches with common activation, so that switches with the same reference symbol switch simultaneously. It should be noted that

Switch S6 is connected both on the output side to delay element 16 of first switching group 1 and on the tap of delay circuit 26 arranged on block 2 on the input side. The delayed signal that can be derived at the tap of the delay element 16 is denoted by B, the delayed signal that can be derived at the tap at the delay element 26 of the second block 2 is denoted by C.

A switch S1 in a switch group 6 is connected to the tap of the delay element 31 of the third block.

All switches S1 to S6 of each switching group 4, 5, 6 are each connected in a node to one another and to a higher-level switch group 7. The higher-level switch group 7 has one switch S10, S20 per switch group 4, 5 or per block 1, 2. In particular, switch S10 is connected to switch group 4 and switch S20 to switch group 5. The switches S10, S20 of the higher-level switching group 7 are connected to one another by a connection and to an output of the delay circuit, to which an output signal F delayed with respect to the input clock signal A can be derived.

If in the described embodiment of the delay circuit is to be switched from the tap of the delay element 16 to the tap of the delay element 26, then only switch S10 must be opened and switch S20 must be closed. Accordingly, there is only one delay time TD between the taps on delay elements 16 and 26. It is not necessary to switch one of the switches S1 to S6 in the switching groups 4, 5 for this switching. This makes it possible to use particularly fast frequencies © ω

Q H U α.

O

H

f f

©

O

LT) o IT) o rH rH ro cn

Φ SH 1 CQ

0 -rl Tue -rl 0 CQ 4J. Φ ε vo 0 vo rö, —1

Φ TJ 0 φ φ Φ -H = 0 01 X 4H TJ TJ Di 0 -H -H φ o -H SH Xi CQ P rö

CQ 0 5 0 J Φ Di N 0 0 0 SH -rl co Φ tn 4-> Φ rH Φ J 0 Q XI ~ φ φ C SH N Φ SH 0 SH rö 0 rö -H XI 4-1 xi rH = 0 SH CQ rö TJ 0 CQ tj 4J Φ ü 4-1

Dl -rl rH Φ 4-1 Φ tn SH Φ 01 D. £ CJ -H ü CQ rQ ISI Φ -rl P XI rö -H SH rH 4J CQ 0

= 0 Tj -H 0 in CQ 3 = 0 tn> CQ 4-> rH Φ -H rö rö SH 01 rQ CJ 0 rQ rH 0 rö CQ 0

SH 03 TJ

Q 3 = 4 <Xi 0 rH <φ CQ Φ tn CQ o> N H rö SH i H 0 SH ü Φ Φ X

Φ rö Φ CQ CJ xi rö N X 4 = 0 Dl CQ. CM SH co 0 0 Φ Φ CQ tn Φ CQ SH

H> TJ -n 0 Φ Φ rö υ X! r-H Φ 4J CJ rH N 0 Φ CQ φ Φ Di φ -H 01 -H X! ε SH Φ

U rH -H 0 -rl ü rö 4-> rH 0 rö Φ rö -H TJ 0> SH -rl 0 T SH CQ £> Φ o α. SH _^ -rl rH TJ 3 Φ co 0 SH rö rH Xi rQ tn 4-1 0 Φ -H Φ co φ TJ 0 Φ VD TJ to 0

Φ 4-> φ Φ Φ Φ N Dl Φ xi PQ ü CQ rH 4-1 -H Φ H 4-) rQ CQ 4-> 0 CQ ε ^ rö

TJ rH rQ -H 4-1 SH P Φ SH -rl tn CJ CQ CQ 0 Φ rH rH ro rH CQ φ 0 rH Φ 0 S

Xi 0 TJ CO Φ PQ Φ CQ = 0 co 0 Φ EH rö TJ = rö n ε rö φ -rl Xi φ rö 4-> CQ TJ Φ 4J

0 --rö £ TJ • 0 4J N φ S ¹ 0 Xi CQ 0 CQ XI 4-1 rl ü rQ Xi rl SH 4J -H •

Φ 3 = 0 φ Φ 4-> SH -H X SH 0 4-1 3 4 vo rö SH tn -H ü SH Xi SH υ φ Φ SH 0 Φ r

XI Φ _^ Φ 4-> -H Φ Φ φ rö φ φ CQ 0 X rH XI Φ 0 CQ rQ CQ Φ ü 0 CQ Dl 4-1 0 0 N ü 01 4-1 XI XI rH 4-> XI EH> TJ rH 0> 0 01 CQ TJ • = 0 rH> X 4-1 Φ

-H CQ U ü Dl 0 U φ Φ CM 0 TJ -H 4J SH rH H SH = 0 φ 4-> SH ISI rö CQ rH 0

Φ 0 -H -H Φ CQ Φ -rl -n CQ CQ φ D, φ Φ CQ φ rö H Φ N rQ PQ Xi Φ SH i XI Di rö D

N CQ Φ SH Dl T Φ Dl rH -rl CQ CQ 4J -H rP rö tn 0 TJ SH φ TJ Φ ü ü 0 X! 0

CQ rl N 0 Φ rH 0 0 rH Sä Φ X -H rH rö H = 0 01 CQ φ vH rH 01> co -H rö ü SH

Di H rö CQ Φ 0 rQ Dl rö rö 0 TJ ü Φ Dl P N -H Φ rH> rö SH CM CQ Dl CQ 0

0 ro π tn -H SH tn 4H CQ 0 N CQ 3 rl CQ TJ i4 0 0 W 3 CQ CQ in

ISI ε 0 TJ Φ PQ 4-> CQ • 0 0 VO rH Φ tn • Φ φ Φ 0 0 Dl> Φ φ 4J 0 SH φ φ xi N tn co -H rH 4-1 -H φ Dl rH PQ 4J 0 rH Xi> Xi -H 0 -H tn -rl SH 0 TJ TJ rQ Φ 4->

CQ vo φ Φ TJ = 0 ι-3 3 SH H rQ 0 rH 0 rö ü ü rH Φ Φ -rl CQ Φ Φ -H Tj rH

CM 0 PQ 0 N Φ Φ φ 0 J 0 ö SH 0 CQ ε -rl tn 4-1 EH XI 4-1 CQ co tn

4-1 Φ CQ ε ro

4-1 0 SH 4-> 0 3 = -H 3 φ i Φ Dl -rl rö rH 0 4J 0 0 0 EH SH rö 0 XI

CQ 0 0 Φ -rl Φ> Φ CQ rH -H 4-1 CJ • Di -H SH 01 Dl 0 CQ 0 φ vo 0 rö Φ Φ ü TJ -H φ Φ CQ> CQ Φ -n -H Tj rö rö rH -rl CQ 4-1 = 0 CQ 4-1 tn = 0 0 -H -rl 4-1 co i4 4-1 P SH co rQ 01 co TJ 4-> TJ Xi tn φ 3 Φ N 4-1 Φ -rl ISI 0 C £ SH Ül -H i Φ

TJ Di -H 2 SH 0 φ 0 X SH CJ CQ 0 SH 3 4J Φ SH 0 <SH Φ CQ 0 Φ υ rH -H 0

0 rH 0 rH Φ Φ -rl Φ rö Φ _^ CQ 01 N Xi φ rö 3 -H rQ Φ rH Φ n SH Φ φ N -H rö TJ Φ

CM 0 rH 4J TJ Dl rH XI rQ H CQ 0 ε υ> EH φ 01 Xi Φ TJ = 0 Φ 3 Pl 4-1 rH 0 TJ 4-1

CQ SH Φ -H -rl Dl CJ X! = 0 Dl 0 CQ φ -H CQ CQ CQ = 0 CJ Pi N 4-> rö D. rH <3 Dl Φ. Φ 4-> PQ 0 4-> CQ -rl ü 0 0 rl Φ TJ Φ 3 Φ CQ φ N CQ Pi -H SH rH CQ 0 rö φ -H 0

4 vo 0 CQ φ rl Oi Φ -H φ P 0 Φ TJ N rö 4-> 4-1 Dl xi SH 0 0 Φ Φ rö 0 SH Xi -H CQ Xi J xi H Φ -H 0 XI φ 0 N φ tn SH Oi SH Φ SH -rl 0 υ Φ SH rQ> XI -rl Dl CJ rH υ SH

CJ 4J Φ Φ ü £ 0 CQ rH Φ • φ = 0 VD 0 Oi CQ Φ ε rö rH> tn υ Φ SH CQ XI 3 SH 0

-rl CQ CQ 3 = Dl -rl SH rl tn Dl tn u tn N CM> rö Di Dl φ 0 SH CQ 3 co 3 Φ ü φ 0 Φ

CQ -μ 0 N -H φ Φ φ 0 0 = 0 SH 0 T = 0 rH CQ 3 = CQ Φ Φ φ Φ φ 4-> SH CQ J Tj 0 rl rQ 4-1 N TJ Di NN φ _^ N Φ J -H Φ N rö 0 Φ 3 4-> xi TJ CQ Dl rH Φ SH φ SH SH CQ Φ = 0 Φ -H PQ SH> Φ Φ tn 4-1 SH 0 rö _^ 0 rö rH ü φ rö TJ Et ) CQ ^• For Q H Φ Φ Φ tn -HN PQ SH TJ φ -rl rQ 0 CQ Φ tn rH -H CQ rö rH CQ TJ 3 i 0 rQ

= r-l tn TJ 3 = 0 0 SH Φ Φ> 3 rH rö 0 -rl> -rl CQ rö Φ 0 Xi Φ 0 rö ü 0 rH rö Φ = 0

-rl SH ISI Φ ε 3 4-> rH 0 01 T rH CQ rö 0 -rl ü 3 = rö co CQ Φ rö Di

0 rl 4H φ Φ φ 3> -rl 3 01 rö SH> CQ rH PQ «. X TJ Di P Φ CQ H PQ SH 0 CQ D. SH φ φ 0 rH X! PQ Φ -rl -rl 0 Φ Dl 4J Φ Φ U -rl EH 3 - tn 0 Φ tn EH 0 Φ rH TJ 4-> rH --o T 0 φ Φ 01 TJ ε 0 CQ 4-1 rH SH Φ 4 -> CQ Φ 0 4-1 0 4-1 rH Φ -rl -H SH TJ φ φ CQ Φ Xi 0 rö rH Φ N -rl Φ 0 -rl CQ rö rö 4-> CQ 4-> 4-1 tn Φ Φ 0 -H ro 4 TJ CQ 4-1 tn

CQ -rl -rl φ 4-> rH 0 co EH TJ SH SH 0 rQ xi -H X -H 4J 0 rH Φ 0 -H TJ CQ SH o

CQ rH Φ CO ε Di -rl Φ Φ Φ CM Φ H Φ Oi 4H ü rö Φ 3 CQ XI rH N Dl Φ <! 01 0 Φ r-H

Φ Dl ^ Φ -H 3 4H 4J rQ 0 rH 0 tn 4-> -rl -H φ U EH rsi U Φ 4- ⁾ -H 3- 0 0 4 CQ rQ CQ N Φ TJ rH 4H CO PQ SH φ rö rö = 0 SH rH CQ Φ CQ Φ -H 4-> rH CQ IS! xi rö D. rH 5

O 0 0 -rl -H -H 4-> 0 rQ Φ Φ -H φ -rl co φ -H ü rö rQ -H 0 rö 0 CQ Φ Φ Φ U rö Φ 0 0 φ ü Φ rsi SH TJ rH ε CQ SH <0 D. Dl CQ EH> EH CQ P rö Φ tn rQ SH -rl TJ Dl 4-1 TJ TJ TJ N o 4->

XI 1 4-1 rH 4-1 ü. X 1 1 in - H H CQ 1 1 -rl TJ Φ φ rö Xi in 1

1 -rl 0 1 = 0 rH 0 SH Dl 4-> _^ = 0 ^• SH f rl SH -rl Φ N Dl -rl 4-> 0 CQ 0 4H

Q -rl SH CQ CQ CQ rQ φ Φ S CQ 0>

H rH Φ -rl SH -rl n TJ 4-1 ε Φ rö 0 U tn T rQ Φ CQ SH 0 4 0 SH CQ rö tn Φ 4-> α. CQ 0 4J -H EH 0 -r | 0 Φ rl rH SH Dl -H tn rö H rH rQ rH Φ rQ 0 0 CQ 0 rö 0 3

0 0 H rö 0 rH N Φ 4J 01> rö = rö

0 -H XI H Φ Φ CQ Φ 4-> CQ 0 Pi Di CM rl Φ CQ υ CQ TJ 4-1 Dl> CQ -rl rö CM SH 0 £ φ 4-> Φ co CQ 0 Φ CQ tn S 0 - H tn -H TJ 0 0 SH 0 H tn 0 CQ 4-1 Φ _^ •

--0 3 Φ 3 rö φ SH CQ rö 0 .. CQ SH CM ei

N -rl Φ φ 4-> φ SH SH <CM -H Φ CM Φ rl rH rH 0 4J Dl rH tn CQ Φ H CQ 0 T

Φ rH tn -rl -rl rö = 0 SH 0 1 0 0 Φ 0 0

> Φ CQ φ φ 4-1 xi N Φ -H CQ Φ 0 ro 4-1 Φ 0

-rl tn -rl CJ SH 4-> Φ o n Φ SH CQ SH rQ φ rl 0 φ 0 φ CQ Φ SH £ -H SH H 0 SH

-H Φ 0 -r-i H CQ> Φ Φ! 2! ε 0 0 4J Φ J CQ SH 1 CQ SH> -r-i i 4J CQ φ Q

Φ 4J φ 01 Φ 0 0 CQ o CQ φ TJ -H

TJ Φ tn -rl 4 0 T φ H q φ xi -H SH CQ -

0 4-1 = 0 ε rö rö CQ 1 0 TJ u CQ --rö 4 0 vo ro - 4-1 N 4 01 0 CQ φ rH 0 0 4J -rl rö • φ

Φ SH SH CQ CQ 0 Φ 4-1 Xi Tj i rö 0 φ -rl ε SH

X φ 0> TJ rö ü 0 SH Φ H -

_^ CQ> Tj SH <4-1 CQ 0 CQ EH ε H vo

0 oil EH 0 ~ CQ 0 Φ Φ 12! Φ ^• φ φ 0 CQ _^ • -rl SH - l rf! H 0 Φ rH -rl rQ 0 Φ 0 XI 4-1 φ rö rl Oi -rl SH Pi _^ TJ 0

Φ SH TJ Φ ü CQ rQ EH 0 Φ Φ

- l Φ Φ Xi -rl -H 4J 4H ε H φ

-H CQ 4J 0 PL) TJ CQ rH tn -r-i Φ rH CQ -rl CQ Φ SH tn -rl X 0 CQ

XI = 0 CQ ε 0 -rl Φ φ 0 0 φ SH -rl = 0 ü N tn Φ --rö Φ SH J Φ 4J 0 £ CQ Φ CQ rH

CQ SH 0 tn 0 TJ ro Dl -r-i CQ T rH 4 XI

Φ Φ rö in 0 CQ rQ ro -rl rH TJ rö SH 0 u rQ> tn 0 _^ 0 rö ^• φ 4-> CQ -H 0 Φ -H CQ

CQ> "φ rP CQ CQ 0 PQ -rl CQ> Xi 0

CQ SH 0 -H P tn -H rö CQ rH 0 SH rö

4J Φ 4H φ Φ rQ 0 SH SH rH H Φ CQ

-rl 0 4H Pi> rH ro "Φ fπ 0" ro 4-> tn

Φ -rl B -rl P. rH rö tn ^• Φ 1 ti -Φ 4H 0 -H 0 rl φ 0 tn CO 0 0 CO 0 Φ φ 0

Φ Dl SH -H Dl -H oil o • tn Φ TJ rS 0 rQ 0 • a Dl 4-> 0 -H EH 0 £ 0 0 rQ 0 r ~~ -H 4-1 SH -rl SH CQ rö 04 φ rö Φ TJ • rö φ Φ Φ φ Φ 3 tn CQ tn 0 0 Pi

CQ rQ CQ -no Dl H tn

3 X CQ 4-1 3 = CQ X Dl

© ω

Q H U α.

Claims

and that a higher-level switching group (7) for selecting a block (1,

2) is provided with a first switch (S10), which couples the first switching node (Kl) on the load side to an output terminal of the delay circuit and with a second switch (S20), the second side on the load side

Switching node (K2) couples to the output terminal of the delay circuit.

3. delay circuit according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the delay elements (11 to 16, 21 to 26) each comprise an inverter.

4. Delay circuit according to one of claims 1 to 3, d a d u r c h g e k e n n z e i c h n e t that the delay elements (11 to 16, 21 to 26) each comprise a pair of inverters connected in series, which together form a delay time TD (TD) between the input and output of the delay element.

5. Delay circuit according to one of claims 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the switches (Sl to S6) of the first and second switch group (4, 5) are designed as tristate inverters with a high-resistance output in a first switching state.

6. Delay circuit according to one of claims 1 to 5, characterized in that a control circuit (50) is provided for controlling the switches (Sl to S6) of the first and second switch groups (4, 5) with a first bit (LSB) and the switch (S10, S20) of the higher-level switching group (7) with a second bit (MSB), the control circuit (50) being connected to the control inputs of the switches (S1 to S6, S10, S20).

7. Delay circuit according to one of claims 1 to 6, characterized in that the number of delay elements per block (1, 2) is greater than or equal to 6.

8. Delay circuit according to one of claims 1 to 7, d a d u r c h g e k e n n z e i c h n e t that the delay circuit is constructed in complementary metal oxide semiconductor circuit technology.