WO2002052725A3 - Delay circuit having adjustable delay - Google Patents

Delay circuit having adjustable delay Download PDF

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Publication number
WO2002052725A3
WO2002052725A3 PCT/DE2001/004311 DE0104311W WO02052725A3 WO 2002052725 A3 WO2002052725 A3 WO 2002052725A3 DE 0104311 W DE0104311 W DE 0104311W WO 02052725 A3 WO02052725 A3 WO 02052725A3
Authority
WO
WIPO (PCT)
Prior art keywords
delay
block
circuit
switch
adjustable
Prior art date
Application number
PCT/DE2001/004311
Other languages
German (de)
French (fr)
Other versions
WO2002052725A2 (en
Inventor
Thomas Hein
Patrick Heyne
Thilo Marx
Torsten Partsch
Original Assignee
Infineon Technologies Ag
Thomas Hein
Patrick Heyne
Thilo Marx
Torsten Partsch
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Thomas Hein, Patrick Heyne, Thilo Marx, Torsten Partsch filed Critical Infineon Technologies Ag
Publication of WO2002052725A2 publication Critical patent/WO2002052725A2/en
Publication of WO2002052725A3 publication Critical patent/WO2002052725A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)

Abstract

The invention relates to a delay circuit having adjustable delay. The delay circuit comprises a first block (1) and a second block (2) that is connected in outgoing circuit thereto. Said blocks each have a chain of delay elements (11 to 16, 21 to 26). A switch group (4, 5) is assigned to each block and enables output-side taps on the delay elements (11 to 16, 21 to 26) to be selected by means of switches (S1 to S6) in order to be able to select a desired delay time. In order to simultaneously control the switch (S6), which is connected to the output-side delay element (16) of the first block (1), and the switch (S6), which is connected to the input-side delay element (26) of the second block (2), the control inputs of these switches are connected to one another. This prevents the occurrence of disturbing pulses also in the event of high clock-pulse rates of clock signals (A) that can be applied to the delay elements on the input side. For this reason, the inventive delay circuit is suited especially for use in delay closed loops in DDR memory chips.
PCT/DE2001/004311 2000-12-27 2001-11-15 Delay circuit having adjustable delay WO2002052725A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10065376.6 2000-12-27
DE10065376A DE10065376C1 (en) 2000-12-27 2000-12-27 Delay circuit with adjustable delay

Publications (2)

Publication Number Publication Date
WO2002052725A2 WO2002052725A2 (en) 2002-07-04
WO2002052725A3 true WO2002052725A3 (en) 2003-08-28

Family

ID=7669234

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/004311 WO2002052725A2 (en) 2000-12-27 2001-11-15 Delay circuit having adjustable delay

Country Status (3)

Country Link
DE (1) DE10065376C1 (en)
TW (1) TW517459B (en)
WO (1) WO2002052725A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10345236B3 (en) * 2003-09-29 2005-03-10 Infineon Technologies Ag Delay regulation circuit for clock-controlled integrated circuit, e.g. semiconductor memory, has input clock signal frequency reduced before subjecting it to variable delay and restoring original clock signal frequency
DE102005009806A1 (en) 2005-03-03 2006-09-14 Infineon Technologies Ag Buffer component for use in e.g. dynamic random access memory module, has control unit setting control signal for activating memory chips group with consecutive address and command signals, so that signals are taken to memory chips of group

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095233A (en) * 1991-02-14 1992-03-10 Motorola, Inc. Digital delay line with inverter tap resolution
US5521499A (en) * 1992-12-23 1996-05-28 Comstream Corporation Signal controlled phase shifter
EP1039637A1 (en) * 1999-03-23 2000-09-27 Infineon Technologies North America Corp. Delay line with frequency range trimming
US20020047739A1 (en) * 2000-10-24 2002-04-25 Mace Timothy Charles Modified clock signal generator

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US566849A (en) * 1896-09-01 Cable hoisting and conveying apparatus
JP3077813B2 (en) * 1990-05-11 2000-08-21 ソニー株式会社 Programmable delay circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095233A (en) * 1991-02-14 1992-03-10 Motorola, Inc. Digital delay line with inverter tap resolution
US5521499A (en) * 1992-12-23 1996-05-28 Comstream Corporation Signal controlled phase shifter
EP1039637A1 (en) * 1999-03-23 2000-09-27 Infineon Technologies North America Corp. Delay line with frequency range trimming
US20020047739A1 (en) * 2000-10-24 2002-04-25 Mace Timothy Charles Modified clock signal generator

Also Published As

Publication number Publication date
WO2002052725A2 (en) 2002-07-04
TW517459B (en) 2003-01-11
DE10065376C1 (en) 2002-07-25

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