DE10065376C1 - Verzögerungsschaltung mit einstellbarer Verzögerung - Google Patents

Verzögerungsschaltung mit einstellbarer Verzögerung

Info

Publication number
DE10065376C1
DE10065376C1 DE10065376A DE10065376A DE10065376C1 DE 10065376 C1 DE10065376 C1 DE 10065376C1 DE 10065376 A DE10065376 A DE 10065376A DE 10065376 A DE10065376 A DE 10065376A DE 10065376 C1 DE10065376 C1 DE 10065376C1
Authority
DE
Germany
Prior art keywords
delay
block
switch
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10065376A
Other languages
German (de)
English (en)
Inventor
Patrick Heyne
Thomas Hein
Torsten Partsch
Thilo Marx
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10065376A priority Critical patent/DE10065376C1/de
Priority to PCT/DE2001/004311 priority patent/WO2002052725A2/fr
Priority to TW090129056A priority patent/TW517459B/zh
Application granted granted Critical
Publication of DE10065376C1 publication Critical patent/DE10065376C1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
DE10065376A 2000-12-27 2000-12-27 Verzögerungsschaltung mit einstellbarer Verzögerung Expired - Fee Related DE10065376C1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE10065376A DE10065376C1 (de) 2000-12-27 2000-12-27 Verzögerungsschaltung mit einstellbarer Verzögerung
PCT/DE2001/004311 WO2002052725A2 (fr) 2000-12-27 2001-11-15 Circuit de temporisation a temporisation reglable
TW090129056A TW517459B (en) 2000-12-27 2001-11-23 Delay circuit with adjustable delay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10065376A DE10065376C1 (de) 2000-12-27 2000-12-27 Verzögerungsschaltung mit einstellbarer Verzögerung

Publications (1)

Publication Number Publication Date
DE10065376C1 true DE10065376C1 (de) 2002-07-25

Family

ID=7669234

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10065376A Expired - Fee Related DE10065376C1 (de) 2000-12-27 2000-12-27 Verzögerungsschaltung mit einstellbarer Verzögerung

Country Status (3)

Country Link
DE (1) DE10065376C1 (fr)
TW (1) TW517459B (fr)
WO (1) WO2002052725A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10345236B3 (de) * 2003-09-29 2005-03-10 Infineon Technologies Ag Verzögerungsregelkreis
US7646650B2 (en) 2005-03-03 2010-01-12 Infineon Technologies Ag Buffer component for a memory module, and a memory module and a memory system having such buffer component

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US566849A (en) * 1896-09-01 Cable hoisting and conveying apparatus
EP0456231A1 (fr) * 1990-05-11 1991-11-13 Sony Corporation Circuit de retard programmable
EP1039637A1 (fr) * 1999-03-23 2000-09-27 Infineon Technologies North America Corp. Ligne de retard avec ajustage de la gamme des fréquences

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095233A (en) * 1991-02-14 1992-03-10 Motorola, Inc. Digital delay line with inverter tap resolution
US5521499A (en) * 1992-12-23 1996-05-28 Comstream Corporation Signal controlled phase shifter
GB2368473A (en) * 2000-10-24 2002-05-01 Advanced Risc Mach Ltd Modified clock signal generator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US566849A (en) * 1896-09-01 Cable hoisting and conveying apparatus
EP0456231A1 (fr) * 1990-05-11 1991-11-13 Sony Corporation Circuit de retard programmable
EP1039637A1 (fr) * 1999-03-23 2000-09-27 Infineon Technologies North America Corp. Ligne de retard avec ajustage de la gamme des fréquences

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10345236B3 (de) * 2003-09-29 2005-03-10 Infineon Technologies Ag Verzögerungsregelkreis
US7646650B2 (en) 2005-03-03 2010-01-12 Infineon Technologies Ag Buffer component for a memory module, and a memory module and a memory system having such buffer component

Also Published As

Publication number Publication date
WO2002052725A2 (fr) 2002-07-04
TW517459B (en) 2003-01-11
WO2002052725A3 (fr) 2003-08-28

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Legal Events

Date Code Title Description
8100 Publication of the examined application without publication of unexamined application
D1 Grant (no unexamined application published) patent law 81
8380 Miscellaneous part iii

Free format text: DIE ENTGEGENGEHALTENE DRUCKSCHRIFT "US 5 66 849" AENDERN IN "US 5 66 8491"

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee