WO2002017324A1 - Memoire integree comportant des cellules de memoire dans plusieurs blocs de cellules de memoire et procede pour actionner une telle memoire - Google Patents

Memoire integree comportant des cellules de memoire dans plusieurs blocs de cellules de memoire et procede pour actionner une telle memoire Download PDF

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Publication number
WO2002017324A1
WO2002017324A1 PCT/DE2001/003039 DE0103039W WO0217324A1 WO 2002017324 A1 WO2002017324 A1 WO 2002017324A1 DE 0103039 W DE0103039 W DE 0103039W WO 0217324 A1 WO0217324 A1 WO 0217324A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
memory cell
connection
memory location
integrated
Prior art date
Application number
PCT/DE2001/003039
Other languages
German (de)
English (en)
Inventor
Peter Weitz
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2002017324A1 publication Critical patent/WO2002017324A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Definitions

  • the object of the present invention is to provide a method for operating an integrated memory of the type mentioned at the outset, by means of which the time required for a test operation of the memory can be kept comparatively short.
  • the object relating to the method is achieved by a method for operating an integrated memory of the type mentioned at the outset according to claim 1.
  • the memory cell blocks of the memory or their sense amplifiers are activated at different times during an access cycle.
  • this ensures that a current requirement resulting from the activation is distributed over a certain period of time, so that there is no short-term, comparatively large voltage drop in the supply voltage.
  • any number of independent memory cell blocks or memory banks can be activated staggered in time.
  • the respective sense amplifiers for evaluating the respective data signal are activated virtually in parallel in one access cycle, the time required for a write access can be kept comparatively short, particularly in a test mode. 1 rH
  • Ti M ra £ 0 ⁇ Ti 0 -rH ti rH 0 AS ⁇ ⁇ 0 ⁇ tn -H rH £ iM -H CQ ⁇ rH 0 tn r
  • Ti 10 AS ⁇ > o ⁇ Ti li, -H CD IH CJ -H rd ⁇ ti S -. rH rd ⁇ ⁇ ⁇ rd 4H 4M rH -n XI ⁇
  • Figure 1 shows an embodiment of an integrated memory according to the invention
  • FIG. 2 shows a time sequence of command signals for operating the memory according to FIG. 1.
  • FIG. 1 shows an embodiment of an integrated memory 10 which has memory cells MC, which are each arranged in a first memory cell block 1 with a memory cell array 11 and in a second memory cell block 2 with a memory cell array 21.
  • the memory cell blocks 1 and 2 are referred to here as memory banks 1 and 2. They each have column lines BL and row lines WL. At the intersection of row lines WL and column lines BL, the memory cells MC are each connected to one of the row lines WL and one of the column lines BL.
  • the memory cells MC of the memory shown each contain a selection transistor and a storage capacitor. Control inputs of the selection transistors are connected to one of the row lines WL while one
  • Main current path of the selection transistors is arranged between the storage capacitor of the respective memory cell MC and one of the column lines BL.
  • the row lines WL are used to select one of the memory cells MC by activating the corresponding row line by switching the relevant selection transistor of a memory cell MC to be selected.
  • a sense amplifier 13 and 23 is assigned to each of the memory cell arrays 11 and 21.
  • the column lines BL of the respective memory banks 1 and 2 can each be connected to the relevant sense amplifier 13 or 23.
  • the sense amplifiers 13 and 23 are used in particular for evaluating a data signal from a corresponding selected memory cell MC.
  • the sense amplifiers 13 and 23 are also connected to a supply voltage VI. 3rd rA • «. ⁇

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Investigating Or Analysing Biological Materials (AREA)

Abstract

L'invention concerne une mémoire intégrée (10) comportant des cellules de mémoire (MC) disposées dans au moins un premier et un second bloc de cellules de mémoire (1,2) dont chacun présente des lignes en colonnes (BL) et des lignes en lignes (WL). Des lignes en colonnes (BL) munie dans chaque cas d'un amplificateur de lecture (13,23) activable servant à évaluer le signal de données d'une cellule de mémoire (MC) sélectionnée sont reliées à chaque bloc de cellules de mémoire (1,2). Un circuit de commande (4) permet de sélectionner dans chaque cas une cellule de mémoire (MC1,MC2) pendant un cycle d'accès (T) dans chacun des blocs de cellules de mémoire (1,2) et l'amplificateur de lecture (13,23) est activé. L'activation de l'amplificateur de lecture (13,23) de chaque bloc de cellules de mémoire (1,2) et d'un circuit de désactivation (TD1,TD2) est décalé dans le temps. Ce système permet d'effectuer un mode de fonctionnement rapide de test de la mémoire (10) sans entraîner de baisse significative de la tension d'alimentation (V1).
PCT/DE2001/003039 2000-08-24 2001-08-09 Memoire integree comportant des cellules de memoire dans plusieurs blocs de cellules de memoire et procede pour actionner une telle memoire WO2002017324A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10041688.8 2000-08-24
DE2000141688 DE10041688B4 (de) 2000-08-24 2000-08-24 Integrierter Speicher mit Speicherzellen in mehreren Speicherzellenblöcken und Verfahren zum Betrieb eines solchen Speichers

Publications (1)

Publication Number Publication Date
WO2002017324A1 true WO2002017324A1 (fr) 2002-02-28

Family

ID=7653704

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/003039 WO2002017324A1 (fr) 2000-08-24 2001-08-09 Memoire integree comportant des cellules de memoire dans plusieurs blocs de cellules de memoire et procede pour actionner une telle memoire

Country Status (3)

Country Link
DE (1) DE10041688B4 (fr)
TW (1) TW520517B (fr)
WO (1) WO2002017324A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10139724B4 (de) 2001-08-13 2004-04-08 Infineon Technologies Ag Integrierter dynamischer Speicher mit Speicherzellen in mehreren Speicherbänken und Verfahren zum Betrieb eines solchen Speichers
US7386749B2 (en) * 2005-03-04 2008-06-10 Intel Corporation Controlling sequence of clock distribution to clock distribution domains

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4222112A (en) * 1979-02-09 1980-09-09 Bell Telephone Laboratories, Incorporated Dynamic RAM organization for reducing peak current
US5222047A (en) * 1987-05-15 1993-06-22 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for driving word line in block access memory

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212690A (en) * 1981-06-24 1982-12-27 Hitachi Ltd Dynamic mos memory device
JPH0271493A (ja) * 1988-09-06 1990-03-12 Mitsubishi Electric Corp 半導体メモリ装置
US5959929A (en) * 1997-12-29 1999-09-28 Micron Technology, Inc. Method for writing to multiple banks of a memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4222112A (en) * 1979-02-09 1980-09-09 Bell Telephone Laboratories, Incorporated Dynamic RAM organization for reducing peak current
US5222047A (en) * 1987-05-15 1993-06-22 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for driving word line in block access memory

Also Published As

Publication number Publication date
DE10041688A1 (de) 2002-03-14
TW520517B (en) 2003-02-11
DE10041688B4 (de) 2008-03-27

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