WO2002011204A1 - Materiau multiphase a faible constante dielectrique et procede de depot - Google Patents
Materiau multiphase a faible constante dielectrique et procede de depot Download PDFInfo
- Publication number
- WO2002011204A1 WO2002011204A1 PCT/US2000/021091 US0021091W WO0211204A1 WO 2002011204 A1 WO2002011204 A1 WO 2002011204A1 US 0021091 W US0021091 W US 0021091W WO 0211204 A1 WO0211204 A1 WO 0211204A1
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- WO
- WIPO (PCT)
- Prior art keywords
- layer
- insulating material
- multiphase
- dielectric
- phase
- Prior art date
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Classifications
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention generally relates to a multiphase material that has a low dielectric constant (or low k), a method for fabricating films of this material and electronic devices containing such films. More particularly, the present invention relates to a low dielectric constant, multiphase material for use as an intralevel or interlevel dielectric film, a cap material, or a hard mask/polish stop in a ULSI back-end-of-the-line (BEOL) wiring structure, electronic structures containing the films and a method for fabrication such films and structures.
- BEOL ULSI back-end-of-the-line
- the low-k materials that have been considered for applications in ULSI devices include polymers containing Si, C, O, such as methylsiloxane, methylsesquioxanes, and other organic and inorganic polymers.
- polymers containing Si, C, O such as methylsiloxane, methylsesquioxanes, and other organic and inorganic polymers.
- materials described in a paper "Properties of new low dielectric constant spin-on silicon oxide based dielectrics" by N.Hacker et al., published in Mat. Res. Soc. Symp. Proc, vol. 476 (1997) p25 appear to satisfy the thermal stability requirement, even though some of these materials propagate cracks easily when reaching thicknesses needed for integration in the interconnect structure when films are prepared by a spin-on technique.
- the precursor materials are high cost and prohibitive for use in mass production.
- the first phase is a hydrogenated oxidized silicon carbon film ( contains Si, C, O and H and henceforth called SiCOH)
- the second phase consisting essentially of C and H atoms.
- a novel dielectric material that has two or more phases wherein the first phase is formed of a SiCOH material is provided.
- the invention further provides a method for fabricating the multiphase material by reacting a first precursor gas containing atoms of Si, C, O, and H and at least a second precursor gas containing mainly atoms of C, H , and optionally F, N and O in a plasma enhanced chemical vapor deposition chamber.
- the present invention still further provides an electronic structure that has layers of insulating materials as intralevel or interlevel dielectrics used in a BEOL wiring structure wherein the insulating material may be a multiphase film.
- a method for fabricating a dual phase film is described.
- the first phase is formed of hydrogenated oxidized silicon carbon and the second phase is formed of mainly C and H atoms.
- the method can be carried out by the operating steps of first providing a plasma enhanced chemical vapor deposition chamber, positioning an electronic structure in the chamber, flowing a first precursor gas containing atoms of Si, C, O, and H into the chamber, flowing a second precursor gas mixture containing atoms of C, H, and optionally F, N and O into the chamber, and depositing a dual-phase film on the substrate.
- the deposited film can be heat treated at a temperature of not less than 300°C for a time period of at least 0.25 hour.
- the method may further include the step of providing a parallel plate reactor which has a conductive area of a substrate chuck between about 300 cm 2 and about 700 cm 2 , and a gap between the substrate and a top electrode between about 1 cm and about 10 cm. A RF power is applied to at least one of the electrodes.
- the substrate may be positioned on the powered electrode or on the grounded electrode.
- the first precursor utilized may be selected from molecules containing at least some of Si, C, O, and H atoms.
- Oxidizing molecules such as O 2 or N 2 O can be added to the first precursor.
- the first precursor is selected from molecules with ring structures such as 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS or tetraethylcyclotetrasiioxane decamethylcyclopentasiloxane (CioHsoOsSis) molecules of methylsilanes mixed with an oxidizing agent such as O 2 or N 2 O or precursor mixtures including Si, O and C
- TCTS 1,3,5,7-tetramethylcyclotetrasiloxane
- CaoHsoOsSis tetraethylcyclotetrasiioxane decamethylcyclopentasiloxane
- the precursor can be delivered directly as a gas to the reactor, delivered as a liquid vaporized directly
- the second precursor gas mixture utilized may be selected from molecules containing C and H atoms.
- O, N or F atoms may be contained in the molecules, or molecules containing such atoms may be added to the precursor mixture.
- the second precursor is selected from the group comprising molecules with ring structures containing C and H atoms, such as cyclic hydrocarbons, cyclic alcohols, cyclic ethers, cyclic aldehydes, cyclic ketones, cyclic esters, pheonols, cycle (also known as bicyclo [2.2.1] hepta-2,5-diene ), norbornylene 2,5-norbornadiene (also known as bicyclo [2.2.1] hepta-2,5-diene ), norbornane (also known as bicyclo [2.2.1] heptane ).
- tricyclo[3.2.1.0]octane tricyclo[3.2.2.0]nonane
- connected ring hydrocarbons such as spiro[3.4]octane, spiro[4.5]nonane, spiro[5.6]decane, and the like.
- cyclic hydrocarbons containing from 5 to 12 carbon atoms cyclopentane, cyclohexane, and the like
- cyclic aromatic hydrocarbons containing 6 to 12 C atoms benzene, toluene, xylenes, and the like
- O or F atoms may be contained in the molecules, or molecules containing such atoms added to the precursor mixture.
- a method for fabricating a dual-phase film consisting of hydrogenated oxidized silicon carbon and a second phase consisting essentially of C and H atoms can be carried out by the operating steps of first providing a parallel plate deposition chamber, positioning an electronic structure in the chamber, providing a remote plasma source, flowing a first precursor gas containing atoms of Si, C, O, and H into the plasma source and from there into the deposition chamber, flowing a second gas mixture containing atoms of C, H, and optionally O, directly into the chamber, depositing a multiphase film on the substrate.
- a multiphase film is described.
- the second precursor gas mixture contains atoms of C, H and optionally, F, N, and O in at least two types of molecules.
- the mixture consists of at least one of cyclic molecules, as those described above, and at least one of noncyclic type molecules selected from the group of alkanes, alkenes, alkynes, ethers, alcohols, esters, ketones, aldehydes, amines, or other O, N or F containing noncyclic hydrocarbons.
- the deposition of the multiphase material of this invention may further include the steps of setting the substrate temperature at between about 25°C and about 400°C, setting the RF power density at between about 0.02 W/cm 2 and about 5.0 W/cm 2 , setting the first precursor flow rate at between about 5 seem and about 1000 seem, setting the flow rate of the first gas of the second precursor between about 5 seem and about 1000 seem, setting the flow rate of the second gas of the second precursor between about 5 seem and about 1000 seem, setting the chamber pressure at between about 50 m Torr and about 10 Torr, and setting a substrate DC bias at between about 0 VDC and about -400 VDC.
- the present invention is further directed to an electronic structure which has layers of insulating materials as intralevel or interlevel dielectrics in a BEOL interconnect structure which includes a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which includes a multiphase material, the second layer of insulating material being in intimate contact with the first layer of insulating material, the first region of conductor being in electrical communication with the first region of metal, and a second region of conductor being in electrical communication with the first region of conductor and being embedded in a third layer of insulating material including a multiphase material, the third layer of insulating material being in intimate contact with the second layer of insulating material.
- the electronic structure may further include a dielectric cap layer situated in-between the first layer of insulating material and the second layer of insulating material, and may further include a dielectric cap layer situated in-between the second layer of insulating material and the third layer of insulating mateinsulating material, and a second dielectric cap layer on top of the third layer of insulating material.
- the dielectric cap material can be selected from silicon oxide, silicon nitride, silicon oxinitride, refractory metal silicon nitride with the refractory metal being Ta, Zr, Hf or W, silicon carbide, silicon carbo-oxide, and their hydrogenated compounds.
- the first and the second dielectric cap layer may be selected from the same group of dielectric materials.
- the first layer of insulating material may be silicon oxide or silicon nitride or doped varieties of these materials, such as PSG or BPSG.
- the electronic structure may further include a diffusion barrier layer of a dielectric material deposited on at least one of the second and third layer of insulating material.
- the electronic structure may further include a dielectric layer on top of the second layer of insulating material for use as a RIE hard mask/polish stop layer and a dielectric diffusion barrier layer on top of the dielectric RIE hard mask/polish-stop layer.
- the electronic structure may further include a first dielectric RTE hard mask/polish-stop layer on top of the second layer of insulating material, a first dielectric RTE diffusion barrier layer on top of the first dielectric polish-stop layer, a second dielectric RTE hard mask/polish-stop layer on top of the third layer of insulating material, and a second dielectric diffusion barrier layer on top of the second dielectric polish-stop layer.
- the electronic structure may further include a dielectric cap layer of same materials as mentioned above between an interlevel dielectric of a multiphase material and an intralevel dielectric of a multiphase material.
- Figure 1 is a cross-sectional view of the present invention parallel plate chemical vapor deposition chamber.
- Figure 2A is an enlarged, cross-sectional view of the present invention dual-phase material.
- Figure 2B is a schematic representation of the random covalent structure of the first phase of the present invention dual-phase material.
- Figure 3 is an enlarged, cross-sectional view of the present invention tri-phase material.
- Figure 4 is a FTIR (Fourier Transform Infrared) spectrum obtained from a single phase SiCOH film deposited from a mixture of tetramethyltetracyclosiloxane (TMCTS) and He.
- TCTS tetramethyltetracyclosiloxane
- Figure 5 is a FTIR spectrum obtained from the present invention dual-phase material deposited from a mixture of TMCTS+He and 2,5-norbornadiene (also known as bicyclo [2.2.1] hepta-2,5-diene ).
- Figure 6 is an enlarged, cross-sectional view " ⁇ T a present invention electronic device having an intralevel dielectric layer and an interlevel dielectric layer formed of the multiphase material.
- Figure 7 is an enlarged, cross-sectional view of the present invention electronic structure of Figure 6 having an additional diffusion barrier dielectric cap layer deposited on top of the multiphase material film.
- Figure 8 is an enlarged, cross-sectional view of the present invention electronic structure of Figure 7 having an additional RTE hard mask/polish stop dielectric cap layer and a dielectric cap diffusion barrier layer deposited on top of the polish-stop layer.
- Figure 9 is an enlarged, cross-sectional view of the present invention electronic structure of Figure 8 having additional RIE hard mask/polish stop dielectric layers deposited on top of the multiphase material film.
- the present invention discloses a novel multiphase material that has a low dielectric constant, and a method for fabricating films of the material.
- the material disclosed in the preferred embodiment contains at least two phases, in which the first phase is a "host" matrix of a hydrogenated oxidized silicon carbon material (SiCOH) consisting of Si, C, O and H in a covalently bonded network and having a dielectric constant of not more than 3.6.
- the other phases of the material of the invention consist mainly of C and H atoms.
- the multiphase material may further contain molecular scale voids, i.e., approximately 0.5 to 20 nanometer in diameter.
- the present invention further discloses a method for fabricating a multiphase material in a parallel plate plasma enhanced chemical vapor deposition chamber.
- a first precursor gas containing Si, O, C and H and optionally molecules which have a ring structure, and a second precursor gas or gas mixture containing one or more types of molecules comprising carbon and hydrogen atoms, can be used for forming the multiphase film.
- the low dielectric constant multiphase film of the invention can further be heat treated at a temperature not less than 300°C for at least 0.5 hour to reduce the dielectric constant.
- the present invention discloses a method for preparing a material having two or more phases that has a low dielectric constant, i.e., lower than 3.2, which is suitable for integration in a BEOL wiring structure.
- the films can be prepared by choosing at least two suitable prified view of a PECVD reactor 10 for processing 200 mm wafers is shown.
- the gas precursors are introduced into reactor 10 through the gas distribution plate (GDP) 14, which is separated from the substrate chuck 12 by a gap and are pumped out through a pumping port 18.
- the RF power 20 is connected to the substrate chuck 12 and transmitted to the substrate 22.
- all other parts of the reactor are grounded.
- the substrate 22 thus acquires a negative bias, whose value is dependent on the reactor geometry and plasma parameters.
- the RF power 20 can be connected to the GDP 14, which is electrically insulated from the chamber, and the substrate chuck 12 is grounded.
- more than one electrical power supply can be used. For instance, two_power supplies can operate at the same RF frequency, or one may operate at a low frequency and one at a high frequency.
- the two power supplies may be connected both to the same electrode or to separate electrodes.
- the RF power supply can be pulsed on and off during deposition.
- Process variables controlled during deposition of the low-k films are RF power, precursor mixture and flow rate, pressure in reactor, and substrate temperature.
- TMCTS first precursor
- 2,5-norbornadiene also known as bicyclo [2.2.1] hepta-2,5-diene, or BCHD .
- the TMCTS precursor vapors were transported into the reactor by using He as a carrier gas.
- the films were heat treated at 400°C after deposition to reduce k.
- the first phase 31 is a "host" matrix which is a hydrogenated oxidized silicon carbon material (SiCOH) including Si, C, O and H in a covalently bonded network and has a dielectric constant of not more than 3.6.
- the covalently bonded network structure of the first phase is shown in Figure 2B.
- the dark lines represent covalent bonds between the Si, C, O and H atoms.
- This is a random network, so that no fundamental repeating unit exists for the structure.
- the hydrogen atoms are shown as “H” labeled 1.
- the oxygen atoms in the network are shown as “O” and are labeled 2.
- the carbon atoms in the network are represented by “C” and are labeled 3.
- the silicon atoms in the network are represented by the intersection of four lines and are labeled 4.
- the oxygen atoms, 2 lie between 2 atoms of either C or Si.
- the second phase 32 of the present invention material Located within the first phase is the second phase 32 of the present invention material.
- the second phase consists essentially of C and H atoms.
- the multiphase material further includes a multiplicity of pores of nanometer size, i.e., from 0.5 to 200 nanometer in diameter.
- the covalently bonded network structure of the first phase also called the "host” matrix, is shown in Figure 2
- the tri-phase material of the present invention is shown in an enlarged, cross-sectional view.
- the first phase 33 is a "host" matrix which is a hydrogenated oxidized silicon carbon material (SiCOH) consisting of Si, C, O and H in a covalently bonded network and having a dielectric constant of not more than 3.6.
- SiCOH hydrogenated oxidized silicon carbon material
- the structure of the first phase has been shown above in Figure 2B.
- the second phase 34 of the present invention material Located within the first phase is the second phase 34 of the present invention material and the third phase 35 of the present invention material.
- the second phase consists essentially of C and H atoms and a multiplicity of pores of a nanometer size, i.e., from 0.5 to 200 nanometer in diameter.
- the third phase 35 may be open regions in the matrix that are created by the presence of the "guest" molecules.
- the open regions may be voids that are induced by the presence of the guest molecules, which disrupt the random network ( Figure 2B) of the first phase of the multiphase material of this invention.
- the third phase consists of C and H atoms, and a multiplicity of pores of a nanometer size.
- the size of the pores may be larger than the pores in the dual-phase composition. Specifically, the size of the pores in the third phase is from 0.5 to 100 nanometer in diameter.
- a plasma was operated in a continuous mode during film deposition.
- the gas mixture consisted of a mixture of TMCTS+He at a flow rate of 30 seem and BCHD at a flow rate of 3 seem.
- the pressure in the reactor was maintained at 500 m Torr.
- the substrate was positioned on the powered electrode to which a RF power of 15 W was applied at a frequency of 13.56 MHZ.
- the substrate acquired a self negative bias of - 17 VDC.
- Figure 4 presents a Fourier transform infrared (FTIR) spectrum of a typical SiCOH film.
- the spectrum displays a strong Si-O absorption band at 1000-1100 cm 1 , a Si-CH 3 absorption peak at 1275 cm 1 , a Si-H absorption band at 2150-2250 cm” 1 and small C-H absorption peaks at 2900-3000 cm "1 .
- the relative intensities of the CH, SiH and SiCH3 peaks as compared to the SiO peak of the SiCOH film are presented in Table 1.
- Figure 5 presents the FTIR spectrum obtained from a multiphase film prepared from a mixture of (TMCTS+He)+BCHD.
- the spectrum displays the Si-O, Si-CH 3 , the Si-H, and C-H absorption peaks, as in Figure 4.
- the intensity of the C-H absorption band at 2900 ⁇ 3000 cm "1 is much stronger for the multiphase film than for the SiCOH film shown in Figure 4.
- the relative intensities of the CH, SiH and SiCH 3 peaks as compared to the SiO peak for this film are also shown in Table 1.
- the integrated area of C-H peak of the multiphase film is 40% of that of the Si-CH 3 peak, while it is only 2% of the Si-CH 3 peak in the SiCOH film.
- the multiphase film contains a significant amount of a secondary CHx (hydrocarbon) phase in addition to the SiCOH phase.
- Another indication of the secondary phase is provided by the splitting of the Si-O peak in the spectrum of the multiphase material seen in Figure 5.
- the plasma was operated in a continuous mode during film ' deposition.
- the gas mixture consisted of a mixture of TMCTS+He at a flow rate of 30 seem and BCHD at a flow rate of 1 seem.
- the pressure in the reactor was maintained at 500 m Torr.
- the substrate was positioned on the powered electrode to which a RF power of 6 W was applied at a frequency of 13.56 MHZ.
- the substrate acquired a self negative bias of - 25 VDC.
- Example 3 In this implementation example, the plasma was operated in a pulsed mode during film deposition, i.e., with a plasma-on time of 18 ms and a plasma-off time of 182 ms per cycle. The other conditions are maintained the same as in Example 2.
- a different precursor of trimethylsilane was used together with BCHD with the plasma operated in a continuous mode during film deposition.
- the pressure in the reactor was maintained at 200 mTorr.
- the substrate was positioned on the powered electrode to which a RF power of 9 W was applied at a frequency of 13.56 MHZ.
- the substrate acquired a self negative bias of - 200 VDC.
- the primary phase in the dual-phase film thus deposited consists of Si, C and H without O.
- a multiphase film is prepared by a method similar to the one described in Example 1 with the only difference that an additional noncyclic hydrocarbon of tertiary butyl ether (TBE) was added to the gas mixture.
- TBE tertiary butyl ether
- the resulting films consist of a SiCOH matrix, a CHx phase containing CH ring structures and a CHy phase containing linear CH structures. If the ring hydrocarbon precursors contains phenolic rings, the first CHx phase in the film will include aromatic CH structures.
- the present invention novel material consists of two or more phases.
- the first phase composition includes atoms of Si, C, O and H.
- a suitable concentration range can be advantageously selected from between about 5 and about 40 atomic percent of Si; between about 5 and about 45 atomic percent of C; between about 0 and about 50 atomic percent of O; and between about 10 and about 55 atomic percent of H.
- a composition of SiCH is produced which has properties similar to that of SiCOH and therefore, may also be suitably used as a present invention composition.
- Example 4 describes a film containing a first phase of SiCH with no oxygen.
- the SiCH film may be deposited by flowing a precursor gas containing Si, C and H into a plasma enhanced chemical vapor deposition chamber.
- the second phase composition includes atoms of C and H and optional F and O.
- a suitable concentration range can be advantageously selected from between about 90 and about 45 atomic percent of C and between about 10 and about 55 atomic percent of H.
- the present invention material further includes molecular size voids dispersed within the multiphase material.
- the present invention material composition may further include at least one element such as F, N or Ge while producing similarly desirable results.
- the films deposited as described above are characterized by FTIR spectrum similar to the one shown in Figure 5.
- the spectrum has strong Si-O absorption band at 1000-1100 cm “1 , a Si-CH 3 absorption peak at 1275 cm” 1 , a Si-H absorption band at 2150-2250 cm “1 and a very strong C-H absorption band at 2900-3000 cm “1 .
- the relative intensities of the CH, SiH and SiCH 3 peaks as compared to the SiO peak of the SiCOH film are presented in Table 1. The relative intensities of the peaks can change with changing deposition conditions and changing precursor gases.
- the SiO absorption band can be deconvoluted in two peaks at 1070 cm “1 and 1030 cm “1 with the first peak indicating the existence of a nanoporous, Si-O cage structure
- the large ratio of the integrated area of C-H peak to that of the Si-CH 3 peak (40%, see Table 1) compared to a ratio of only 2% of the SiCOH film is a clear indication that the multiphase film contains a significant amount of a secondary CHx (hydrocarbon) phase in addition to the SiCOH phase.
- a liquid precursor to the plasma reactor is by use of a liquid delivery system. Nitrogen, hydrogen, germanium, or fluorine containing gases can be added to the gas mixture in the reactor if needed to modify the low-k film properties.
- the multiphase films may thus contain atoms such as Ge, N and F.
- the deposited multiphase films may optionally be further modified before undergoing further integration processing to either evaporate the residual volatile contents and to dimensionally stabilize the films or just dimensionally stabilize the films.
- the stabilization process can be carried out in a furnace annealing step at between 300°C and 400°C for a time period between about 0.25 hours and about 4 hours.
- the stabilization process can also be performed in a rapid thermal annealing process at temperatures above 300°C.
- the dielectric constant of the multiphase films obtained according to the present invention novel process are not higher than 3.2.
- the thermal stability of the multiphase films obtained according to the present invention process is up to at least a temperature of 350°C.
- the multiphase films obtained by the present invention process are characterized by dielectric constants of k ⁇ 3.2, and are thermally stable for process integration in a BEOL interconnect structure which is normally processed at temperatures- ⁇ i up TO 4UirC Furthermore, the multiphase films have extremely low crack propagation velocities in water, i.e., below 10 9 m/s and may even be below 10" 11 m/s.
- the present invention novel material and process can therefore be easily adapted in producing multiphase films as intralevel and interlevel dielectrics in BEOL processes for logic and memory devices.
- an electronic device 30 built on a silicon substrate 32 is shown.
- an insulating material layer 34 is first formed with a first region of metal 36 embedded therein.
- a multiphase film 38 of the present invention is deposited on top of the first layer of insulating material 34 and the first region of metal 36.
- the first layer of insulating material 34 may be suitably formed of silicon oxide, silicon nitride, doped varieties of these materials, or any other suitable insulating materials.
- the multiphase film 38 is then patterned in a photolithography process and a conductor layer 40 is deposited thereon.
- a second layer of multiphase film 44 is deposited by a plasma enhanced chemical vapor deposition process overlying the first multiphase film 38 and the first conductor layer 40.
- the conductor layer 40 may be deposited of a metallic material or a nonmetallic conductive material. For instance, a metallic material of aluminum or copper, or a nonmetallic material of nitride or polysilicon.
- the first conductor 40 is in electrical communication with the first region of metal 36.
- a second region of conductor 50 is then formed after a photolithographic process on the second multiphase film layer 44 is conducted followed by a deposition process for the second conductor material.
- the second region of conductor 50 may also be deposited of either a metallic material or a nonmetallic material, similar to that used in depositing the first conductor layer 40.
- the second region of conductor 50 is in electrical communication with the first region of conductor 40 and is embedded in the second layer of multiphase insulator 44.
- the second layer of multiphase film is in intimate contact with the first layer of insulating material 38.
- the first layer of insulating material 38 of multiphase is an intralevel dielectric material
- the second layer of insulating material, i.e., the multiphase film 44 is both an intralevel and an interlevel dielectric. Based on the low dielectric constant of the multiphase film, superior insulating property can be achieved by the first insulating layer 38 and the second insulating layer 44.
- Figure 7 shows a present invention electronic device 60 similar to that of electronic device 30 shown in Figure 6, but with an additional dielectric cap layer 62 deposited between the first insulating material layer 38 and the second insulating material layer 44.
- the dielectric cap layer 62 can be suitably formed of a material such as silicon oxide, silicon nitride, silicon oxinitride, refractory metal silicon nitride with the refractory metal being Ta, Zr, Hf or W, silicon carbide, silicon carbo-oxide (SiCO), and their hydrogenated compounds.
- the additional dielectric cap layer 62 functions as a diffusion barrier layer for preventing diffusion of the first conductor layer 40 into the second insulating material layer 44 or into the lower layers, especially into layers 34 and 32.
- FIG 8. Another alternate embodiment of the present invention electronic device 70 is shown in Figure 8.
- two additional dielectric cap layers 72 and 74 which act as a RTE mask and CMP (chemical mechanical polishing) polish stop layer are used.
- the first dielectric cap layer 72 is deposited on top of the first multiphase insulating material layer 38 and used as a RTE mask.
- the function of the second dielectric layer 74 is to provide an end point for the CMP process utilized in planarizing the first conductor layer 40.
- the polish stop layer 74 can be deposited of a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxinitride, refractory metal silicon nitride with the refractory metal being Ta, Zr, Hf or W, silicon carbide, silicon carbo-oxide (SiCO), and their hydrogenated compounds.
- the top surface of the dielectric layer 72 is at the same level as the first conductor layer 40.
- a second dielectric layer 74 can be added on top of the second multiphase insulating material layer 44 for the same purposes.
- Still another alternate embodiment of the present invention electronic device 80 is shown in Figure 9.
- an additional layer 82 of dielectric material is deposited and thus dividing the second insulating material layer 44 into two separate layers 84 and 86.
- the intralevel and interlevel dielectric layer 44 formed of a multiphase material, shown in Figure 8, is therefore divided into an interlayer dielectric layer 84 and an intralevel dielectric layer 86 at the boundary between via 92 and interconnect 94.
- An additional diffusion barrier layer 96 is further deposited on top of the upper dielectric layer 74.
- the additional benefit provided by this alternate embodiment electronic structure 80 is that dielectric layer 82 acts as an RLE etch stop providing superior interconnect depth control.
- Still other alternate embodiments may include an electronic structure which has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure that includes a pre- processed semiconducting substrate which has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of the insulating material wherein the second layer of insulating material is in intimate contact with the first layer of insulating material, and the first region of conductor is in electrical communication with the first region of metal, a second region of conductor in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, wherein the third layer of insulating material is in intimate contact with the second layer of insulating material, a first dielectric cap layer between the second layer of insulating material and the third layer of insulating material, and a second dielectric cap layer on top of the third layer of insulating material, wherein the first and the second dielectric cap layers are formed of a material that includes atoms of Si, C, O
- Still other alternate embodiments of the present invention include an electronic structure which has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure that includes a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which is in intimate contact with the first layer of insulating material, the first region of conductor is in electrical communication with the first region of metal, a second region of conductor that is in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, the third layer of insulating material is in intimate contact with the second layer of insulating material, and a diffusion barrier layer formed of a multiphase material including atoms of Si, C, O and H deposited on at least one of the second and third layers of insulating material.
- Still other alternate embodiments include an electronic structure which has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure that includes a pre- processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which is in intimate contact with the first layer of insulating material, the first region of conductor is in electrical communication with the first region of metal, a second region of conductor in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, the third layer of insulating material is in intimate contact with the second layer of insulating material, a reactive ion etching (RIE) hard mask/polish stop layer on top of the second layer of insulating material, and a diffusion barrier layer on top of the RLE hard mask/polish stop layer, wherein the RLE hard mask/polish stop layer and the diffusion barrier layer are formed of a multiphase material including atoms of Si, C, O and H
- Still other alternate embodiments include an electronic structure which has layers of insulating materials as intralevel or interlevel dielectrics in a wiring structure that includes a pre- processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which is in intimate contact with the first layer of insulating material, the first region of conductor is in electrical communication with the first region of metal, a second region of conductor in electrical communication with the first region of conductor and is embedded in a third layer of insulating material, the third layer of insulating material is in intimate contact with the second layer of insulating material, a first RJE hard mask, polish stop layer on top of the second layer of insulating material, a first diffusion barrier layer on top of the first RLE hard mask/polish stop layer, a second RTE hard mask/polish stop layer on top of the third layer of insulating material, and a second diffusion barrier layer on top of the second RTE hard mask/polish stop
- Still other alternate embodiments of the present invention includes an electronic structure that has layers of insulating material as intralevel or interlevel dielectrics in a wiring structure similar to that described immediately above but further includes a dielectric cap layer which is formed of a multiphase material including atoms of Si, C, O and H situated between an interlevel dielectric layer and an intralevel dielectric layer.
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Abstract
L'invention concerne un matériau multiphase, à faible constante diélectrique, que l'on peut utiliser en tant que diélectrique d'interconnexion dans des puces à circuit imprimé; elle concerne également un procédé de fabrication d'un film multiphase, à faible constante diélectrique, consistant à utiliser une technique de dépôt chimique en phase vapeur activé par plasma. L'invention concerne encore des dispositifs électroniques contenant des couches isolantes de ces matériaux multiphase à faible constante diélectrique que l'on prépare à l'aide du procédé ci-dessus.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB008197970A CN1257547C (zh) | 2000-08-02 | 2000-08-02 | 多相低介电常数材料及其沉积方法与应用 |
KR1020037001345A KR100615410B1 (ko) | 2000-08-02 | 2000-08-02 | 저 유전 상수 다상 물질 및 그 증착 방법 |
JP2002516830A JP3882914B2 (ja) | 2000-08-02 | 2000-08-02 | 多相低誘電率材料およびその堆積方法 |
PCT/US2000/021091 WO2002011204A1 (fr) | 2000-08-02 | 2000-08-02 | Materiau multiphase a faible constante dielectrique et procede de depot |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2000/021091 WO2002011204A1 (fr) | 2000-08-02 | 2000-08-02 | Materiau multiphase a faible constante dielectrique et procede de depot |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002011204A1 true WO2002011204A1 (fr) | 2002-02-07 |
Family
ID=21741655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/021091 WO2002011204A1 (fr) | 2000-08-02 | 2000-08-02 | Materiau multiphase a faible constante dielectrique et procede de depot |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP3882914B2 (fr) |
KR (1) | KR100615410B1 (fr) |
CN (1) | CN1257547C (fr) |
WO (1) | WO2002011204A1 (fr) |
Cited By (13)
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EP1354980A1 (fr) * | 2002-04-17 | 2003-10-22 | Air Products And Chemicals, Inc. | Procédé de production d'un film en SiOCH poreux |
EP1420439A2 (fr) * | 2002-11-14 | 2004-05-19 | Air Products And Chemicals, Inc. | Procédé non-thermique pour la fabrication des couches à faible constante diélectrique |
EP1464726A2 (fr) * | 2003-04-01 | 2004-10-06 | Air Products And Chemicals, Inc. | Méthode CVD pour obtenir un film de SiCOH poreux à faible constante diélectrique |
US6846515B2 (en) | 2002-04-17 | 2005-01-25 | Air Products And Chemicals, Inc. | Methods for using porogens and/or porogenated precursors to provide porous organosilica glass films with low dielectric constants |
JP2005530363A (ja) * | 2002-06-19 | 2005-10-06 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 半導体デバイスの層内または層間誘電体としての超低誘電率材料 |
US7332445B2 (en) | 2004-09-28 | 2008-02-19 | Air Products And Chemicals, Inc. | Porous low dielectric constant compositions and methods for making and using same |
US7404990B2 (en) | 2002-11-14 | 2008-07-29 | Air Products And Chemicals, Inc. | Non-thermal process for forming porous low dielectric constant films |
US7422774B2 (en) * | 2002-05-08 | 2008-09-09 | Applied Materials, Inc. | Method for forming ultra low k films using electron beam |
JP2011014925A (ja) * | 2002-04-17 | 2011-01-20 | Air Products & Chemicals Inc | ポロゲン、ポロゲン化された前駆体及び低誘電率をもつ多孔質有機シリカガラス膜を得るためにそれらを使用する方法 |
JP2011082540A (ja) * | 2003-03-18 | 2011-04-21 | Internatl Business Mach Corp <Ibm> | 多相超低k誘電 |
US8293001B2 (en) | 2002-04-17 | 2012-10-23 | Air Products And Chemicals, Inc. | Porogens, porogenated precursors and methods for using the same to provide porous organosilica glass films with low dielectric constants |
US8951342B2 (en) | 2002-04-17 | 2015-02-10 | Air Products And Chemicals, Inc. | Methods for using porogens for low k porous organosilica glass films |
US9061317B2 (en) | 2002-04-17 | 2015-06-23 | Air Products And Chemicals, Inc. | Porogens, porogenated precursors and methods for using the same to provide porous organosilica glass films with low dielectric constants |
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JP2004253791A (ja) | 2003-01-29 | 2004-09-09 | Nec Electronics Corp | 絶縁膜およびそれを用いた半導体装置 |
US7049247B2 (en) * | 2004-05-03 | 2006-05-23 | International Business Machines Corporation | Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made |
US7892648B2 (en) | 2005-01-21 | 2011-02-22 | International Business Machines Corporation | SiCOH dielectric material with improved toughness and improved Si-C bonding |
JP5505680B2 (ja) * | 2008-09-01 | 2014-05-28 | 独立行政法人物質・材料研究機構 | 絶縁膜材料、この絶縁膜材料を用いた成膜方法および絶縁膜 |
CN104746045B (zh) * | 2013-12-26 | 2018-03-06 | 北京北方华创微电子装备有限公司 | 化学气相沉积方法和装置 |
CN108389782B (zh) * | 2018-03-06 | 2020-02-25 | 江苏欧特电子科技有限公司 | 一种形成超低k电介质层的方法 |
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JP3419745B2 (ja) * | 2000-02-28 | 2003-06-23 | キヤノン販売株式会社 | 半導体装置及びその製造方法 |
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- 2000-08-02 CN CNB008197970A patent/CN1257547C/zh not_active Expired - Lifetime
- 2000-08-02 JP JP2002516830A patent/JP3882914B2/ja not_active Expired - Lifetime
- 2000-08-02 WO PCT/US2000/021091 patent/WO2002011204A1/fr active Application Filing
- 2000-08-02 KR KR1020037001345A patent/KR100615410B1/ko active IP Right Grant
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US4824690A (en) * | 1984-03-03 | 1989-04-25 | Standard Telephones And Cables Public Limited Company | Pulsed plasma process for treating a substrate |
US5494712A (en) * | 1993-08-27 | 1996-02-27 | The Dow Chemical Company | Method of forming a plasma polymerized film |
US5559367A (en) * | 1994-07-12 | 1996-09-24 | International Business Machines Corporation | Diamond-like carbon for use in VLSI and ULSI interconnect systems |
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Cited By (25)
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US8293001B2 (en) | 2002-04-17 | 2012-10-23 | Air Products And Chemicals, Inc. | Porogens, porogenated precursors and methods for using the same to provide porous organosilica glass films with low dielectric constants |
JP2007204850A (ja) * | 2002-04-17 | 2007-08-16 | Air Products & Chemicals Inc | ポロゲン、ポロゲン化された前駆体および低誘電率をもつ多孔質有機シリカガラス膜を得るためにそれらを使用する方法 |
US8951342B2 (en) | 2002-04-17 | 2015-02-10 | Air Products And Chemicals, Inc. | Methods for using porogens for low k porous organosilica glass films |
US6846515B2 (en) | 2002-04-17 | 2005-01-25 | Air Products And Chemicals, Inc. | Methods for using porogens and/or porogenated precursors to provide porous organosilica glass films with low dielectric constants |
EP1354980A1 (fr) * | 2002-04-17 | 2003-10-22 | Air Products And Chemicals, Inc. | Procédé de production d'un film en SiOCH poreux |
JP2014150287A (ja) * | 2002-04-17 | 2014-08-21 | Air Products And Chemicals Inc | ポロゲン、ポロゲン化された前駆体、及び低誘電率を有する多孔質有機シリカガラス膜を得るためのそれらの使用 |
US9061317B2 (en) | 2002-04-17 | 2015-06-23 | Air Products And Chemicals, Inc. | Porogens, porogenated precursors and methods for using the same to provide porous organosilica glass films with low dielectric constants |
JP2011014925A (ja) * | 2002-04-17 | 2011-01-20 | Air Products & Chemicals Inc | ポロゲン、ポロゲン化された前駆体及び低誘電率をもつ多孔質有機シリカガラス膜を得るためにそれらを使用する方法 |
US7943195B2 (en) | 2002-04-17 | 2011-05-17 | Air Products And Chemicals, Inc. | Porogens, porogenated precursors and methods for using the same to provide porous organosilica glass films with low dielectric constants |
US7384471B2 (en) | 2002-04-17 | 2008-06-10 | Air Products And Chemicals, Inc. | Porogens, porogenated precursors and methods for using the same to provide porous organosilica glass films with low dielectric constants |
JP2012144738A (ja) * | 2002-04-17 | 2012-08-02 | Air Products & Chemicals Inc | 組成物 |
US7422774B2 (en) * | 2002-05-08 | 2008-09-09 | Applied Materials, Inc. | Method for forming ultra low k films using electron beam |
JP2011119770A (ja) * | 2002-06-19 | 2011-06-16 | Internatl Business Mach Corp <Ibm> | 半導体デバイスの層内または層間誘電体としての超低誘電率材料 |
JP2005530363A (ja) * | 2002-06-19 | 2005-10-06 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 半導体デバイスの層内または層間誘電体としての超低誘電率材料 |
US7404990B2 (en) | 2002-11-14 | 2008-07-29 | Air Products And Chemicals, Inc. | Non-thermal process for forming porous low dielectric constant films |
US7470454B2 (en) | 2002-11-14 | 2008-12-30 | Air Products And Chemicals, Inc. | Non-thermal process for forming porous low dielectric constant films |
EP2306499A3 (fr) * | 2002-11-14 | 2011-06-01 | Air Products and Chemicals, Inc. | Procédé non-thermique pour la fabrication des couches à faible constante diélectrique |
EP1420439A3 (fr) * | 2002-11-14 | 2006-04-26 | Air Products And Chemicals, Inc. | Procédé non-thermique pour la fabrication des couches à faible constante diélectrique |
EP1420439A2 (fr) * | 2002-11-14 | 2004-05-19 | Air Products And Chemicals, Inc. | Procédé non-thermique pour la fabrication des couches à faible constante diélectrique |
JP2011082540A (ja) * | 2003-03-18 | 2011-04-21 | Internatl Business Mach Corp <Ibm> | 多相超低k誘電 |
KR100767246B1 (ko) | 2003-04-01 | 2007-10-17 | 에어 프로덕츠 앤드 케미칼스, 인코오포레이티드 | 화학 증착 필름의 침착 속도를 강화시키는 방법 |
EP1795627A1 (fr) * | 2003-04-01 | 2007-06-13 | Air Products and Chemicals, Inc. | Méthode CVD pour obtenir un film de SiCOH poreux à faible constante diélectrique |
EP1464726A3 (fr) * | 2003-04-01 | 2006-02-01 | Air Products And Chemicals, Inc. | Méthode CVD pour obtenir un film de SiCOH poreux à faible constante diélectrique |
EP1464726A2 (fr) * | 2003-04-01 | 2004-10-06 | Air Products And Chemicals, Inc. | Méthode CVD pour obtenir un film de SiCOH poreux à faible constante diélectrique |
US7332445B2 (en) | 2004-09-28 | 2008-02-19 | Air Products And Chemicals, Inc. | Porous low dielectric constant compositions and methods for making and using same |
Also Published As
Publication number | Publication date |
---|---|
CN1257547C (zh) | 2006-05-24 |
JP3882914B2 (ja) | 2007-02-21 |
KR100615410B1 (ko) | 2006-08-25 |
JP2004534373A (ja) | 2004-11-11 |
CN1454394A (zh) | 2003-11-05 |
KR20040012661A (ko) | 2004-02-11 |
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