WO2002007321A1 - Appareil et procede de codage de signal numerique, appareil et procede de decodage de signal numerique, systeme d'emission de signal numerique - Google Patents
Appareil et procede de codage de signal numerique, appareil et procede de decodage de signal numerique, systeme d'emission de signal numerique Download PDFInfo
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- WO2002007321A1 WO2002007321A1 PCT/JP2001/006305 JP0106305W WO0207321A1 WO 2002007321 A1 WO2002007321 A1 WO 2002007321A1 JP 0106305 W JP0106305 W JP 0106305W WO 0207321 A1 WO0207321 A1 WO 0207321A1
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- signal
- data
- bit
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- digital signal
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/02—Delta modulation, i.e. one-bit differential modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
- H04L1/0063—Single parity check
Definitions
- the present invention relates to a digital signal encoding apparatus and method for encoding a delta-sigma modulated 1-bit signal
- the present invention relates to a digital signal decoding device and method for decoding an encoded signal encoded by a digital signal encoding device and method, and a digital signal transmission system.
- ⁇ 2 modulated high-speed 1-bit audio signal is a data format used in conventional digital audio, for example, a data format with a sampling frequency of 44.I kHz and a data word length of 16 bits.
- the transmission frequency is much higher and the data word length is shorter, for example, the sampling frequency is 64 times the frequency of 44.1 kHz and the data word length is 1 bit. It features a possible frequency band. Further, even with a 1-bit signal due to the ⁇ modulation, a high dynamic range can be secured in an audio band that is low with respect to an oversampling frequency of 64 times. Utilizing this feature, it can be applied to high-quality sound recorders and data transmission.
- the ⁇ modulation circuit itself is not a particularly new technology, and its circuit configuration is suitable for IC integration, and the accuracy of AD conversion can be obtained relatively easily. Circuit.
- the ⁇ modulated signal can be converted back to an analog audio signal by passing it through a simple analog mouth-to-pass filter.
- the present invention has been proposed in view of the above-mentioned circumstances, and suppresses a transmission rate when transmitting a modulated 1-bit digital signal and information data together.
- a digital signal encoding apparatus and method, and a digital signal decoding apparatus and method, and a digital signal decoding system and a digital signal transmission system that enable high-quality digital signal transmission by suppressing an audio signal band component of a transmission signal while maintaining It is intended to be provided.
- a digital signal encoding apparatus is a digital signal encoding apparatus that modulates one-bit signals of a plurality of n (n ⁇ 2) channels obtained by delta-sigma ( ⁇ ⁇ ) modulation, wherein the digital signal encoding apparatus is an original signal component.
- Phase modulation means for applying a phase modulation process to the 1-bit signal to add anti-phase component data, and a modulation output to which the phase modulation process is applied by the phase modulation device and to which the anti-phase component data is added, for n channels,
- the related information data of the 1-bit signal which is the original signal component, is Information data adding means for adding to the original signal component.
- the present invention attenuates signal components in the same transmission capacity as in phase modulation and in the audio band by arranging the order of the anti-phase signal components due to modulation in a 1-bit signal subjected to phase modulation. It is possible to embed information data as it is.
- This digital signal encoding apparatus provides, in addition to the addition of related information data, an area consisting of a plurality of samples at regular intervals on the modulation output subjected to the phase modulation processing by the phase modulation means.
- a phase modulating means and a synchronizing signal adding means for adding an independent synchronizing pattern which cannot be present in the information data adding means by converting the negative phase component data according to a 1-bit signal which is an original signal component are provided.
- a synchronization pattern a pattern that cannot be present in the rearranged one-bit signal is realized by changing only the reverse phase signal component by the phase modulation, and is periodically arranged. Therefore, in the digital signal decoding device described later, since the self-extraction of the synchronization signal becomes possible, the original signal and the information signal can be decoded from the modulated signal.
- the digital signal encoding method is a digital signal encoding method for modulating a 1-bit signal of a plurality of n (n ⁇ 2) channels obtained by Dell Sigma (S) modulation.
- the order of the related information of the 1-bit signal, which is the original signal component by rearranging the reversed-phase component data in units of m (n ⁇ m ⁇ 2) channels in the n-channel.
- the modulation output In addition to the addition of related information data to the modulation output that has been subjected to the phase modulation process in the information data addition process for the component and the phase modulation process, it consists of multiple samples at regular intervals.
- an independent synchronization signal that cannot exist in the phase modulation process and the information data addition process is provided.
- the difference between the number of “1” and “0” data in one bit data caused by the addition of the synchronization pattern in the synchronization signal addition step of adding In a certain region of, the inverse phase component in the same region is manipulated to make it zero, and within one cycle And a correction process for making the number of data of “1” and “0” the same.
- the digital signal decoding apparatus performs a phase modulation process on a 1-bit signal of a plurality of n (n ⁇ 2) channels obtained by delta-sigma ( ⁇ ⁇ ) modulation, and adds a negative-phase component Generates a signal and rearranges the reversed-phase component data in units of multiple m (n ⁇ m ⁇ 2) channels in n channels of the modulated signal, and related information on the 1-bit signal that is the original signal component
- a digital signal decoding device that decodes the 1-bit data sequence transmitted from the digital signal encoding device that outputs the data as a 1-bit data sequence in addition to the original signal component.
- the 1-bit data string transmitted from the encoding device is provided with an area consisting of a plurality of samples at regular intervals apart from the addition of related information data and the like.
- an independent synchronization pattern that cannot exist in the phase modulation processing and the information data addition processing is added, and synchronization is detected by detecting this synchronization pattern.
- Based on the synchronization signal detection means for self-extracting the signal and the synchronization signal detected by the synchronization signal detection means determine the embedding position of the anti-phase component data in the 1-bit data sequence transmitted from the digital signal encoding device.
- the information signal detecting means for detecting the related information data, and the synchronization signal detected by the synchronization signal detecting means.
- Signal data detecting means for judging components and detecting signal data every 2 * ⁇ samples from the head data of each channel;
- the digital signal decoding method performs a phase modulation process on a 1-bit signal of a plurality of ⁇ ( ⁇ 2) channels obtained by Delaware sigma ( ⁇ ) Generates a signal and rearranges the reversed-phase component data in units of multiple m (n ⁇ m ⁇ 2) channels in the ⁇ channel of the modulated signal to obtain information related to the original 1-bit signal component.
- a digital signal decoding method for decoding a 1-bit data sequence transmitted from a digital signal encoding device which outputs data as a 1-bit data sequence by adding to an original signal component.
- an area consisting of a plurality of samples is provided at regular intervals apart from the addition of related information data.
- phase component data By converting the phase component data according to the 1-bit signal that is the original signal component, an independent synchronization pattern that cannot exist in the phase modulation process and the process of adding the information data is added.
- a synchronization signal detection step of self-extracting the synchronization signal by detecting the signal; and a negative-phase component data in a 1-bit data string transmitted from the digital signal encoder based on the synchronization signal detected in the synchronization signal detection step.
- An information data detecting step of determining the embedding position of the data and detecting the related information data, and, based on the synchronization signal detected in the synchronization signal detecting step, in the 1-bit data sequence transmitted from the digital signal encoding device. Judgment of the original signal component and detection of signal data every 2 * n samples from the first data of each channel. And a degree.
- the digital signal transmission device performs a phase modulation process on a 1-bit signal of a plurality of n (n ⁇ 2) channels obtained by Delaware sigma ( ⁇ ⁇ ) modulation, and generates a modulated signal to which antiphase component data is added. Generates and rearranges the negative-phase component data in units of multiple m (n ⁇ m ⁇ 2) channels in n channels of the modulated signal to obtain related information data of the 1-bit signal as the original signal component , A digital signal encoding device that outputs a 1-bit data sequence in addition to the original signal component, a phase modulation process and an information data included in the 1-bit data sequence transmitted from the digital signal encoding device.
- the synchronization signal is self-extracted by detecting an independent synchronization pattern that cannot be present in the additional processing in the evening, and based on the synchronization signal, the digital signal encoding device
- the position of embedding of the inverse phase component data in the transmitted 1-bit data sequence is determined, the related information data is detected and decoded, and the original signal component in the 1-bit data sequence is decoded based on the synchronization signal.
- a digital signal decoding device that judges and decodes the signal every 2 ⁇ n samples from the head data of each channel and decodes it.
- FIG. 1 is a block diagram showing a configuration of a digital I / O encoder device to which a digital signal encoding device according to the present invention is applied.
- FIG. 2 is a diagram showing a frame configuration of serial transmission data output by the digital I / B code device shown in FIG.
- FIG. 3 is a diagram showing an example of the SYNC pattern having the frame configuration shown in FIG.
- FIG. 4 is a diagram schematically illustrating a correction process in the SYNC correction region having the frame configuration illustrated in FIG.
- FIG. 5 is a flowchart of a correction process in the SYNC correction region having the frame configuration shown in FIG.
- FIG. 6 is a diagram showing a process in the information data embedding region having the frame configuration shown in FIG.
- FIG. 7 is a flowchart of the information data embedding process shown in FIG.
- FIG. 8 is a block diagram showing a configuration of a digital I / O decoding device to which the digital signal decoding device according to the present invention is applied.
- FIG. 9 is a flowchart showing a process of detecting information data performed by the digital I / O decoding device shown in FIG.
- FIG. 10 is a modulation spectrum characteristic diagram of serial transmission data according to the present invention.
- BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.
- the digital signal encoding device shown here is a digital I / O encoding device 1 shown in FIG. 1 for encoding a two-channel, one-bit audio signal of L and R obtained by ⁇ modulation.
- the digital I / 0 encoder 1 includes a phase modulator 7 for performing a phase modulation process on a 1-bit audio signal, and, out of the phase output of the phase modulator 7, the anti-phase component data in units of two channels.
- An information data adding unit 11 for rearranging and adding related information data of the 1-bit audio signal.
- the digital I / O encoder 1 is a 1-bit digital A scrambler L4 that scrambles the L channel audio signal data At, a scrambler R5 that scrambles the R channel audio signal data A supplied from the input terminal 3, and a scrambler output of the scrambler L4 And a channel combiner 6 for combining the scramble output of the scrambler R5.
- the phase modulator 7 subjects the combined output of the channel combiner 6 to phase modulation.
- the digital I / O encoder device 1 includes a SYNC signal addition & correction processing unit 8 between the phase modulator 7 and the information data addition processing unit 11.
- the SYNC signal addition & correction processing unit 8 receives the SYNC timing signal generated by the SYNC timing generator 9 and embeds a SYNC signal in the modulation output of the phase modulator 7 to generate a synchronization pattern. Generate and correct the synchronization pattern.
- the digital I / O encoding device 1 scrambles the audio signal, and then adds related information data related to the audio signal, so that the 1-bit L-channel audio signal data At, And 1-bit R-channel audio signal data are scrambled by a scrambler L 4 and a scrambler R 5, and then a 1-bit stereo audio signal of L and R alternates by a channel synthesizer 6 and a phase modulator 7.
- the data is converted to data, and the data is converted to a phase-modulated signal having an anti-phase component for each data.
- the related information data is information data on properties of the audio signal and the like.
- auxiliary data of an audio signal and copyright protection information 0 and 1 representing the related information data are represented by rearranging the above-described inverse phase component data.
- FIG. 2 shows not only the phase modulated signal obtained through the channel synthesizer 6 and the phase modulator 7 but also the 1-bit data output from the digital I / 0 encoding device 1—sequence, ie, serial data.
- 3 shows a configuration of a transmission frame. The case of two channels is shown. The 1-bit L channel data LI, L 2, L 3... And the 1-bit R channel data R 1, R 2, R 3... Are converted by the scrambler L 4 and the scrambler 5. After being scrambled, the channel combiner 6 forms a 1-bit stereo data—an evening train, which is alternately rearranged into L1, R1, L2, R2. Then, the phase modulator 7 applies a phase modulation to this data overnight.
- the four data “L 1, XL 1, R l, XR 1” are set as one stereo sample unit, and 64 stereo samples are set as one frame.
- One frame is composed of a phase modulation area (1 stereo sample), a SYNC pattern area (2 stereo samples), a SYNC correction area (13 stereo samples), and an information data embedding area (48 stereo samples).
- the negative-phase component data in the region is further converted.
- the SYNC signal addition & correction processing section 8 receives the SYNC timing signal generated by the SYNC timing generator 9 and embeds a SYNC pattern described later for each frame period. .
- FIG. 3 is an example specifically showing a phase modulation area and a SYNC pattern area in the frame shown in FIG.
- the first sample is a signal in which the normal phase modulation is maintained, and the anti-phase components XL ⁇ and XR 0 are determined by the audio signal data L O and R 0.
- the S YNC pattern area is a data sample in units of two samples, and as shown in the figure, 16 combinations of four data L 1, R 1, L 2, and R 2 in the audio signal component data It is converted into one of sixteen SYNC patterns.
- These 16 types of SYNC pattern data are independent synchronization patterns that cannot exist as the phase modulation output and the related information data. By detecting this synchronization pattern, the digital signal decoding apparatus described later can detect the head of the frame shown in FIG.
- the SYNC signal addition & correction processing unit 8 performs a SYNC correction process described later for the SYNC pattern.
- FIG. 4 is an example specifically showing the processing of the SYNC correction region in the frame shown in FIG. In the 16 NC patterns shown in Fig. 3 above, the number of 1's and 0's in each of the eight patterns is not equal. Assuming that the increase / decrease number of “1” is ((number of “1”) one (number of “0”)) / 2, the increase / decrease number of “1” in the SYNC pattern is +2 to ⁇ 2. In the SYNC correction area, the number of 1s and 0s in the combined area of the SYNC pattern area and the SYNC correction area (total of 60 data) is equal. This is an area for correction so as to make it easier.
- step S1 The algorithm of the SYNC correction process performed by the SYNC signal addition & correction processing unit 8 is shown in the flowchart of FIG.
- step S2 two data cards s [l, 0] or [0, 1] are sequentially provided from the top of the SYNC pattern. Is determined. If it is determined in step S2 that the above two data are [1, 0] or [0, 1] (YE S), the process proceeds to step S3, where the correction processing is performed in the S YNC correction area. .
- the signal data is [0]
- the phase modulation data is [0, 1].
- step S4 By converting this data into [0, 0], the increase / decrease number of “1” is reduced by 1, One correction process is performed. Then, the process shifts to the next two data in step S4, and returns to step S1. If it is determined in step S2 that the above-mentioned 2 days is not [1, 0] or [0, 1] (NO), the process proceeds to step S4.
- step S 1 If it is determined in step S 1 that the subtraction number of “1” is 1, the process proceeds to step S 5, and the first two SYNC patterns are [1, 0] or [0, 1] in order from the top of the SYNC pattern. Judge. If it is determined in step S2 that the above two data are [1, 0] or [0, 1] (YE S), the process proceeds to step S6, where + correction processing is performed in the SYNC correction area. When the signal demodulation is [1], the phase modulation data is [1, 0]. By converting this data to [1, 1], the increase / decrease of “1” is + 1 and + correction process. Then, in step S4, the process shifts to the next two data, and returns to step S1. If it is determined in step S5 that the above two data is not [1, 0] or [0, 1] (NO), the flow proceeds to step S4.
- the information data addition processing section 11 distributes the information data I supplied from the input terminal 10 for each SYNC evening signal generated by the SYNC signaling generator 9 and embeds the information data. Embed in the area and generate serial transmission data DT.
- the information data embedding process by the information data addition processing unit 11 will be described with reference to FIGS.
- Figure 6 shows the information data embedded in the frame shown in Figure 2 above.
- FIG. 7 is a specific example specifically showing the processing of the limited area, and FIG. 7 is a flowchart of the processing.
- step S 11 in FIG. 7 four types of patterns based on a combination of two audio signal component data L and R in one stereo sample (two phase modulation units) are obtained.
- step S11 the process shifts to the next 4 data.
- [L, R] [0, 1] or [1, 0] in step S11
- the process proceeds to step S13, where the related information data is set to “0” or “1”.
- the related information is “1”
- [L, XR, R, XL] [0, 1, 1, 1, 0]
- This embodiment decodes serial transmission data DT output from the digital I / O encoding device 1 shown in FIG. 1 and transmitted via the transmission path 12 as shown in FIG. / O decoding device 20.
- the digital I / O decoding device 20 has a SYNC signal detector 22 for self-extracting a synchronization signal from the serial transmission data DT input via the input terminal 21 and a SYNC signal detector 22 for self-extraction.
- An information data detector 23 for detecting the related information data from the serial transmission data DT based on the extracted synchronization signal;
- a signal data detector 24 for detecting audio signal data from the serial transmission data D ⁇ based on the synchronization signal.
- the digital I / O decoding device 20 includes: an error detector 25 for detecting whether or not the number of 1s and 0s in one frame of the serial transmission data D is equal to each other, and detecting an error during transmission; A mask circuit 26 for preventing erroneous detection of the SYNC signal by the signal detector 22 and scrambling applied to the L channel audio signal in the audio signal data detected by the signal data detector 24 A descrambler L28 to unscramble, a descrambler R29 to descramble the scramble applied to the audio signal of the R channel of the audio signal data, an error processor L30, and an error processor R3 And 1.
- the serial transmission data DT passing through the transmission path 12 is transmitted to the SYNC signal detector 22, the information data detector 23, the signal data detector 24, and the error detector 2 Supplied to 5.
- the SYNC signal detector 22 detects the SYNC pattern shown in FIG. 3 from the serial transmission data DT and generates a SYNC signal for specifying a frame cycle. After the detection of the SYNC signal, the section of the SYNC correction area is masked by the mask circuit 26 'to prevent erroneous detection of the SYNC signal.
- the information data detector 23 receives the SYNC signal from the SYNC signal detector 22 and performs the processing shown in FIG. 9 to be described later from the beginning of the information data embedding area of the serial transmission data DT to the end of the frame. Detects information data and outputs it as output information I from output terminal 27 at a time.
- FIG. 9 is a flowchart for detecting the information data I embedded in the digital signal encoding device 1 by the information data detector 23. First, it reads every four data (one stereo sample) from the top of the information data embedding area. Then, in step S21, it is determined whether or not the frame is at the end. If it is not the end (NO), the process proceeds to step S22, and the process branches according to the read four data. Here, if the four data read out is [0, 0, 1, 1, 1] or [1, 1, 0, 0,], the process proceeds to step S23, and the related information data is read out. Judge as "1".
- step S22 the four data read out above is [0, 1, 1, 0,] or [1, [0, 0, 1], the process proceeds to step S24, and it is determined that the related information data is "0". Further, if the four data read out in step S22 is [0, 1, 0, 1] or [1, 0, 1, 0], the process proceeds to step S25, and it is determined that there is no information data.
- step S23, S24, or S25 proceed to step S26 to read out the next four data, return to step S21, and continue until the frame end is detected. Is repeated.
- the signal data detector 24 determines the frame of the frame determined from the SYNC signal detected by the SYNC signal detector 22 from the serial transmission data DT . By simply extracting the signal every other data from the beginning, it is possible to detect the entire audio signal.
- the detected audio signal data is separated into L channel and R channel by alternately allocating every other data, and scrambled by descrambler L28 and descrambler R29 respectively.
- the signal is output and output from the output terminals 33 and 34 as 1-bit L-channel audio signal data At and 1-bit R-channel audio signal data A through the error processor L30 and the error processor R31. You.
- the error detector 25 receives the SYNC signal from the SYNC signal detector 22, detects whether the number of 1s and 0s in one frame of the serial transmission data DT is equal or not, and is not equal.
- the error processor L 3 ⁇ and the error processor R 31 are controlled as error data in which an error has occurred during transmission on the transmission line 12, and the audio signal data is subjected to a mu-process. Further, continuous detection of the same data is performed, and if continuous data of 7 or more is detected, mute processing is similarly performed as error data due to disconnection of the transmission line 12 or the like.
- Fig. 10 shows an example of the spectrum of modulated serial transmission data, where A in the figure is random scrambled, and B in the figure is an example of modulation using this modulation method.
- a digital signal transmission system can be constituted by the digital I / O encoder 1 shown in FIG. 1 and the digital I / O decoder 20 shown in FIG. INDUSTRIAL APPLICABILITY According to the present invention, by embedding and transmitting information data by rearranging the order of reverse-phase signals by phase modulation, the data bandwidth within the audio band of the transmitted signal can be doubled. It realizes high-quality serial transmission that can transmit additional information data while attenuating components.
- the original signal data can be decoded by sequential simple processing because the original signal data exists continuously for each fixed sample. It is possible to eliminate the impact on
- the information data Since the information data is randomized and embedded, it has no spectrum specific to the information signal.
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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DE60116497T DE60116497T2 (de) | 2000-07-19 | 2001-07-19 | Verfahren und vorrichtung zur kodierung und dekodierung eines digitalen signals, und digitales uebertragungssystem |
US10/088,179 US7113118B2 (en) | 2000-07-19 | 2001-07-19 | Digital signal encoding apparatus and method, digital signal decoding apparatus and method, and digital signal transmission system |
EP01951953A EP1304809B1 (en) | 2000-07-19 | 2001-07-19 | Digital signal encoding apparatus and method, digital signal decoding apparatus and method, and digital signal transmission system |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2000219507A JP2002043945A (ja) | 2000-07-19 | 2000-07-19 | ディジタル信号符号化装置及び方法、ディジタル信号復号装置及び方法、並びにディジタル信号伝送システム |
JP2000-219507 | 2000-07-19 |
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WO2002007321A1 true WO2002007321A1 (fr) | 2002-01-24 |
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PCT/JP2001/006305 WO2002007321A1 (fr) | 2000-07-19 | 2001-07-19 | Appareil et procede de codage de signal numerique, appareil et procede de decodage de signal numerique, systeme d'emission de signal numerique |
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US (1) | US7113118B2 (ja) |
EP (1) | EP1304809B1 (ja) |
JP (1) | JP2002043945A (ja) |
KR (1) | KR100780268B1 (ja) |
CN (1) | CN1166070C (ja) |
DE (1) | DE60116497T2 (ja) |
WO (1) | WO2002007321A1 (ja) |
Cited By (1)
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US7413754B2 (en) | 2001-09-19 | 2008-08-19 | Bionorica Ag | Use of extracts of the genus Cimicifugaas organoselective medicines for treating diseases of the genitourinary system caused by sex hormones |
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JP2010263496A (ja) * | 2009-05-08 | 2010-11-18 | Sony Corp | 信号処理装置、及び誤り訂正方法 |
JP2010273307A (ja) * | 2009-05-25 | 2010-12-02 | Canon Inc | 信号伝送装置 |
KR20220151484A (ko) * | 2021-05-06 | 2022-11-15 | 삼성전자주식회사 | 확장된 대역폭에서 자원들을 재사용하기 위한 장치 및 방법 |
CN113259083B (zh) * | 2021-07-13 | 2021-09-28 | 成都德芯数字科技股份有限公司 | 一种调频同步网相位同步方法 |
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US5319735A (en) * | 1991-12-17 | 1994-06-07 | Bolt Beranek And Newman Inc. | Embedded signalling |
US5574453A (en) * | 1994-03-03 | 1996-11-12 | Sony Corporation | Digital audio recording apparatus |
JP3465455B2 (ja) * | 1995-12-28 | 2003-11-10 | ソニー株式会社 | 信号伝送装置 |
ID25532A (id) * | 1998-10-29 | 2000-10-12 | Koninkline Philips Electronics | Penanaman data tambahan dalam sinyal informasi |
BR9907017A (pt) * | 1998-11-17 | 2000-10-17 | Koninkl Philips Electronics Nv | "processo e arranjo para embutir dados suplementares em um sinal de informação, processo e arranjo para extrair dados suplementares de um sinal de informação, sinal de informação tendo amostras de dados suplementares embutidas em posições predeterminadas do sinal, e, meio de armazenagem." |
JP3624829B2 (ja) * | 2000-12-26 | 2005-03-02 | 日産自動車株式会社 | 車両の走行制御装置 |
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- 2000-07-19 JP JP2000219507A patent/JP2002043945A/ja not_active Ceased
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2001
- 2001-07-19 KR KR1020027003122A patent/KR100780268B1/ko not_active IP Right Cessation
- 2001-07-19 WO PCT/JP2001/006305 patent/WO2002007321A1/ja active IP Right Grant
- 2001-07-19 US US10/088,179 patent/US7113118B2/en not_active Expired - Fee Related
- 2001-07-19 EP EP01951953A patent/EP1304809B1/en not_active Expired - Lifetime
- 2001-07-19 DE DE60116497T patent/DE60116497T2/de not_active Expired - Fee Related
- 2001-07-19 CN CNB018020976A patent/CN1166070C/zh not_active Expired - Fee Related
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JPH1098799A (ja) * | 1996-09-19 | 1998-04-14 | Yamaha Corp | ミキシング装置及びそれを用いたオーディオシステム |
JPH10233687A (ja) * | 1997-02-20 | 1998-09-02 | Sharp Corp | 信号伝送装置 |
Non-Patent Citations (1)
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7413754B2 (en) | 2001-09-19 | 2008-08-19 | Bionorica Ag | Use of extracts of the genus Cimicifugaas organoselective medicines for treating diseases of the genitourinary system caused by sex hormones |
Also Published As
Publication number | Publication date |
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EP1304809A1 (en) | 2003-04-23 |
CN1166070C (zh) | 2004-09-08 |
US7113118B2 (en) | 2006-09-26 |
CN1386326A (zh) | 2002-12-18 |
US20020171501A1 (en) | 2002-11-21 |
DE60116497T2 (de) | 2006-09-07 |
KR20020035590A (ko) | 2002-05-11 |
KR100780268B1 (ko) | 2007-11-28 |
DE60116497D1 (de) | 2006-03-30 |
EP1304809A4 (en) | 2004-08-18 |
EP1304809B1 (en) | 2006-01-04 |
JP2002043945A (ja) | 2002-02-08 |
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