WO2001087023A1 - Carte a circuits imprimes multicouche et son procede de production - Google Patents

Carte a circuits imprimes multicouche et son procede de production Download PDF

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Publication number
WO2001087023A1
WO2001087023A1 PCT/JP2000/008104 JP0008104W WO0187023A1 WO 2001087023 A1 WO2001087023 A1 WO 2001087023A1 JP 0008104 W JP0008104 W JP 0008104W WO 0187023 A1 WO0187023 A1 WO 0187023A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
multilayer circuit
outermost
insulating layer
printed circuit
Prior art date
Application number
PCT/JP2000/008104
Other languages
English (en)
Japanese (ja)
Inventor
Takashi Kariya
Original Assignee
Ibiden Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co., Ltd. filed Critical Ibiden Co., Ltd.
Publication of WO2001087023A1 publication Critical patent/WO2001087023A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination

Definitions

  • the present invention relates to a multilayer circuit board and a method for manufacturing the same.
  • Various electronic components are mounted on the outermost surface of the multilayer circuit board.
  • a method of mounting electronic components on the multilayer circuit board first, a predetermined conductor circuit is formed on the outermost surface of the multilayer circuit board. A component hole for inserting the terminal of the electronic component and a connection land having a slightly larger diameter than the component hole are formed at predetermined positions on the conductor circuit.
  • the lead part of the electronic component is connected by soldering, or cream solder is applied to the land formed at a predetermined position in the conductor circuit, and the terminal of the electronic component is
  • a surface mount method is used in which electronic components are connected by placing the part in contact with the cream solder and reflowing.
  • the first invention for solving the above-mentioned problem is that one of the front and back surfaces of the insulating layer or Is a multilayer circuit board in which a plurality of printed boards having conductor layers formed on both surfaces are laminated, and at least one of the pair of outermost surfaces on the front and back of the multilayer circuit board has an outermost insulating layer A hole penetrating in the thickness direction is provided in the outermost insulating layer, and a conductive bump is provided in the hole so as to protrude from the surface of the outermost insulating layer. It is characterized that it is.
  • a second invention is a method of manufacturing a multilayer circuit board in which a plurality of printed circuit boards each having a conductor layer formed on one or both of the front and back surfaces of an insulating layer,
  • the outermost insulating layer is disposed on at least one of the outermost surfaces of the front and back surfaces of the multilayer circuit board, and the outermost insulating layer has A hole penetrating in the thickness direction is provided, and a conductive bump is provided in the hole so as to protrude from the surface of the outermost insulating layer.
  • the conductive bump can be used directly for connecting components and the like, it is not necessary to form a land on the conductor circuit. Therefore, the pitch between the conductive bumps can be reduced as compared with the case where lands are provided, and the density of mounting electronic components can be increased.
  • FIG. 1 is a cross-sectional view (1) showing a process for manufacturing a multilayer circuit board according to the first embodiment.
  • FIG. 2 is a cross-sectional view (2) showing a step of manufacturing the multilayer circuit board in the first embodiment.
  • FIG. 3 is a cross-sectional view showing a step of manufacturing the multilayer circuit board in the second embodiment.
  • FIG. 4 is a cross-sectional view when an adhesive layer is applied to a single-sided copper-clad laminate on which conductive bumps are formed according to the second embodiment.
  • FIG. 5 shows a copper foil laminated on a single-sided copper-clad laminate coated with an adhesive layer according to the second embodiment. It is sectional drawing at the time of attaching.
  • FIG. 6 is a cross-sectional view when circuit boards according to the second embodiment are stacked.
  • FIG. 7 is a cross-sectional view of the multilayer circuit board according to the second embodiment.
  • the multilayer circuit board 1 of this embodiment (see FIG. 2H) is formed by laminating a plurality of single-sided printed boards 2, and one outermost surface (the uppermost surface in FIG. 2) has an outermost insulating substrate 4 A. (Corresponding to the outermost insulating layer of the present invention), and a via hole 6 (corresponding to a hole of the present invention) penetrating in the thickness direction of the outermost insulating substrate 4A is provided. A conductive bump 8 is provided therein.
  • the starting material of the single-sided printed circuit board 2 forming the multilayer circuit board 1 is a single-sided copper-clad laminate 3.
  • the single-sided copper-clad laminate 3 is made of, for example, a copper foil 5 (the conductive layer of the present invention) on one surface (the lower surface in FIG. 1) of an insulating substrate 4 formed of, for example, a plate-like glass cloth epoxy resin. Is a well-known structure (Fig. 1A).
  • Laser irradiation is performed at a predetermined position on the single-sided copper-clad laminate 3 from the insulating substrate 4 side to form a via hole 6 that penetrates in the thickness direction of the insulating substrate 4 and reaches the copper foil 5 (FIG. 1).
  • Laser processing can be performed by, for example, a pulse oscillation type carbon dioxide gas laser processing apparatus.
  • the pulse energy is 2.0 to 100 mJ
  • the pulse width is 1 to 100 s
  • the pulse is It is desirable to form under the condition that the interval is 0.5 ms or more and the number of shots is 3 to 50.
  • the desmear treatment can be performed by, for example, potassium permanganate treatment, oxygen plasma discharge, corona discharge treatment, or the like.
  • a plating conductor is formed in the via hole 6 by an electroplating method using the copper foil 5 as one electrode.
  • Form 7 (Fig. 1C).
  • the filling amount of the plated conductor 7 is preferably such that the upper surface thereof is slightly lower than the surface of the insulating substrate 4.
  • Metsu Copper is most preferred as the metal to be plated, but any metal that can be plated, such as tin, silver, solder, copper / tin, or copper silver, may be used.
  • the conductive bumps 8 are filled so as to slightly protrude from the upper surface of the insulating substrate 4 (FIG. 1D).
  • the protective film is peeled off from the copper foil 5
  • the copper foil 5 is etched by a well-known etching technique to form a conductor circuit 9 (FIG. 1E).
  • thermosetting adhesive 10 for example, epoxy resin can be used
  • a roll coating method (FIG. 1). F).
  • the plurality of single-sided printed circuit boards 2 thus formed are aligned and superposed (FIG. 2G).
  • the outermost printed circuit board 2A of the uppermost layer has the outermost insulating substrate 4A, on which the conductive bumps 8 are projected, on the outer side (upper side in FIG. 2G), and the conductor circuit 9 side on the inner side (see FIG. 2G). 2 G).
  • Each of the single-sided printed circuit boards 2 located thereunder is arranged such that the insulating substrate 4 side is directed upward and the conductive circuit 9 side is directed downward, and the conductive bumps 8 are disposed on the single-sided printed circuit board 2 which is directly overlaid. They are laminated so that they can be connected to the provided conductor circuit 9.
  • the adhesive 10 is hardened, and the multilayer circuit board 1 on which the single-sided printed boards 2 are completely integrated is formed (see FIG. 2H)
  • the tip of the conductive bump 8 of the single-sided printed circuit board 2 is in contact with the conductive circuit 9 of the adjacent single-sided printed circuit board 2, and the electrical connection between the conductive circuits 9 of the adjacent single-sided printed circuit board 2 is established.
  • a conductive bump 8 protrudes from the upper surface of the outermost insulating substrate 4A to enable connection of electronic components and the like.
  • a land is formed at a predetermined position on the conductor circuit 9 on the lowermost side of the multilayer circuit board 1, and a pin 11 for connecting the multilayer circuit board 1 to another member or a solder pole ( (Not shown).
  • the outermost insulating substrate 4A is disposed on the uppermost surface of the multilayer circuit board 1, and the via holes 6 penetrating in the thickness direction of the outermost insulating substrate 4A are provided.
  • a conductive bump 8 is provided in the via hole 6 so as to project from the surface of the outermost insulating substrate 4A. Since the conductive bumps 8 can be used directly for connecting components and the like, it is not necessary to form lands for connecting components on the conductor circuit. Therefore, the pitch between the conductive bumps 8 can be reduced as compared with the case where lands are provided, and the density of mounting electronic components can be increased.
  • the multilayer circuit board 1 of the present embodiment only the conductive bumps 8 are formed on the surface of the outermost insulating substrate 4A, and the conductive circuit 9 is not formed. Therefore, when connecting components and the like to the multilayer circuit board 1, there is no need to apply a solder resist for soldering work. Therefore, there is no need to consider wiring displacement errors during solder resist printing, and it is possible to increase the density of electronic component mounting.
  • the multilayer circuit board 21 of the present embodiment has a double-sided printed circuit board 23 having conductor circuits 34 formed on both sides as a core wiring board, and a single-sided printed circuit having conductor circuits 34 formed on one side on both sides thereof.
  • the multilayered circuit board 21 is provided with an outermost insulating substrate 24 (corresponding to the outermost insulating layer of the present invention) on one side (the uppermost surface in FIG. 7) of the multilayer circuit board 21.
  • the conductive bumps 29 are provided so as to protrude from both the front and back surfaces of the outermost insulating substrate 24.
  • the single-sided printed circuit board 22 is formed in the same manner as the single-sided printed circuit board 2 of the first embodiment, the description is omitted.
  • a double-sided printed circuit board 23 serving as a core wiring board is formed.
  • the starting material of the double-sided printed circuit board 23 is a single-sided copper-clad laminate 25.
  • the single-sided copper-clad laminate 25 is formed, for example, on one surface (a lower surface side in FIG. 3) of an insulating substrate 26 formed of a plate-like glass cloth epoxy resin, with a copper foil 31 (the present invention).
  • This is a well-known structure with a conductive layer ( Figure 3A).
  • Via holes 27 are formed at predetermined positions on the insulating substrate 26 in the same manner as in the first embodiment (FIG. 3B).
  • a plating conductor 28 is formed by an electroplating method (FIG. 3C), and the conductive bump 29 is insulated so as to overlap the plating conductor 28. From the top of the flexible substrate 26 (Fig. 3D).
  • thermosetting adhesive 30 is applied to the surface of the single-sided copper-clad laminate 25 on which the conductive bumps 29 are formed, and is superposed on the copper foil 32 and hot-pressed.
  • a double-sided copper-clad laminate 33 in which the copper foil 32 is also laminated on the surface of the single-sided copper-clad laminate 25 opposite to the copper foil 31 is obtained (FIG. 5).
  • the heating press conditions at this time are, for example, when the thickness of the copper foil 32 is 1 2 / xm, the heating temperature is 180 ° C, the heating time is 70 minutes, and the pressure is 1.96 X 1 Desirably, the pressure is 0—2 Pa and the degree of vacuum is 20 Torr.
  • the copper foils 31 and 32 of the double-sided copper-clad laminate 33 are etched by a well-known etching method to form a conductor circuit 34.
  • a single-sided printed circuit board 22 is laminated on each of the upper and lower sides of the double-sided printed circuit board 23 (FIG. 6).
  • Each single-sided printed circuit board 22 is arranged so that the conductive bump 29 faces inward and the conductive circuit 34 faces outward, and the conductive bump 29 faces the conductive circuit 34 of the double-sided printed board 23. Are laminated so that they can be connected to each other.
  • the outermost insulating substrate 24 is aligned and overlaid on the outermost surface.
  • a via hole 27 is provided at a predetermined location on the outermost insulating substrate 24, and the via conductor 27 is filled with a plated conductor 28, which is to be superposed on both sides of the plated conductor 28.
  • the conductive bumps 29 are provided so as to slightly protrude from the surface of the outermost insulating substrate 24. Therefore, the outermost insulating substrate 24 has a structure in which conductive bumps 29 are protruded on both surfaces thereof. Then, the conductive bumps 29 on the inner surface are laminated so as to be connectable to the conductor circuit 34 of the adjacent single-sided printed circuit board 22.
  • the adhesive 30 is cured, and the single-sided printed circuit board 22, the double-sided printed circuit board 23, and the outermost insulating substrate 24 are completely completed.
  • the integrated multilayer circuit board 21 is formed (FIG. 7).
  • the tips of the conductive bumps 29 of the single-sided printed circuit board 22 are in contact with the conductor circuit 34 of the double-sided printed circuit board 23, and the adjacent single-sided printed circuit board 22 and the double-sided printed circuit board 23 Are electrically connected to each other.
  • the outermost insulating substrate A conductive bump 29 protrudes from the surface of 24 to enable connection of electronic components and the like.
  • a land is formed at a predetermined position on the lowermost conductive circuit 34 of the multilayer circuit board 21, and pins 35 for connecting the multilayer circuit board 21 to other members are provided.
  • pins 35 for connecting the multilayer circuit board 21 to other members are provided.
  • solder poles (not shown).
  • the conductive bump 29 is protruded from the surface of the multilayer circuit board 21. Therefore, similarly to the first embodiment, the conductive bumps 29 can be directly used for connecting components and the like, and there is no need to form connection lands. Therefore, it is possible to increase the density of mounting electronic components. Also in this embodiment, only the conductive bumps 29 are formed on the surface of the outermost insulating substrate 24, and the conductor circuit 34 does not exist. This eliminates the need to apply solder resist during the soldering operation, so that it is not necessary to consider wiring misalignment errors during solder resist printing, and it is possible to increase the density of electronic component mounting.
  • the lamination was performed after the conductive bumps 8 and 29 were formed on the outermost insulating substrates 4A and 24.
  • the conductive bumps are not necessarily required. It is not necessary to form the conductive bumps first, and after the lamination, conductive bumps may be formed on the outermost insulating substrate.
  • one single-sided printed circuit board 22 is laminated on both sides of the double-sided printed circuit board 23, but according to the present invention, one single-sided printed circuit board is required. Instead, a plurality of single-sided printed circuit boards may be stacked.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

L'invention concerne une carte à circuits imprimés multicouche et son procédé de production. Une surface extrême (2A) de la carte (1) à circuits imprimés présente une couche d'isolation extrême formée de trous (6) la traversant dans le sens de la largeur. Ces trous (6) possède des bosses (8) électriquement conductrices saillant de la surface de la couche d'isolation extrême. Cette disposition permet d'utiliser les bosses électriquement conductrices pour relier directement des éléments et rend la formation de zones de contact inutile. En conséquence, comparé cas où l'on préparait des zones de contact, le pas entre lesdites bosses peut être réduit, ce qui rend possible d'augmenter la densité de câblage et d'emballage d'éléments électroniques.
PCT/JP2000/008104 2000-05-10 2000-11-16 Carte a circuits imprimes multicouche et son procede de production WO2001087023A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000137081A JP2001320169A (ja) 2000-05-10 2000-05-10 多層回路基板およびその製造方法
JP2000-137081 2000-05-10

Publications (1)

Publication Number Publication Date
WO2001087023A1 true WO2001087023A1 (fr) 2001-11-15

Family

ID=18644920

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/008104 WO2001087023A1 (fr) 2000-05-10 2000-11-16 Carte a circuits imprimes multicouche et son procede de production

Country Status (2)

Country Link
JP (1) JP2001320169A (fr)
WO (1) WO2001087023A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4002117B2 (ja) * 2002-02-21 2007-10-31 古河電気工業株式会社 多層基板及びその製造方法
JP7259942B2 (ja) * 2019-03-29 2023-04-18 株式会社村田製作所 樹脂多層基板、および樹脂多層基板の製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410696A (ja) * 1990-04-27 1992-01-14 Nitto Denko Corp 多層配線基板の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3059568B2 (ja) * 1992-01-23 2000-07-04 古河電気工業株式会社 多層プリント回路基板の製造方法
JPH06283866A (ja) * 1993-03-30 1994-10-07 Nitto Denko Corp 多層回路基板およびその製造方法
JP3944921B2 (ja) * 1996-04-05 2007-07-18 日立化成工業株式会社 多層配線板の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410696A (ja) * 1990-04-27 1992-01-14 Nitto Denko Corp 多層配線基板の製造方法

Also Published As

Publication number Publication date
JP2001320169A (ja) 2001-11-16

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