Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
  • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
  • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/16—Modifications for eliminating interference voltages or currents
  • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
  • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
  • H03K17/166—Soft switching
  • H03K17/167—Soft switching using parallel switching arrangements
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
  • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
  • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Definitions

• the present invention relates generally to output buffers, and more specifically to load capacitance compensating output buffers.
• Slew rates for an unregulated buffer will vary based upon load capacitance.
• Load dependence of slew rate can be controlled by using a feedback path from the driver output to control the input of the driver and by using layout techniques such as snaked gates.
• Transient effects such as transmission line effect reflections, cross talk between nodes, and overshoot/ringing, are reduced by using feedback to control the slew rate of individual output nodes.
• slew rates may be controlled by connecting a capacitor between a controlling voltage and an output signal of an output stage.
• the capacitor is used to provide feedback which is necessary to moderate the output transient.
• One disadvantage associated with an output stage of this type of circuit is that large capacitors are required to drive an output pull-up and/or pull-down gate while overcoming the drive current of the pre-driver.
• a series precision resistor which typically requires special processing can be used.
• Another slew rate control implementation uses switched differential amplifiers to compare the output signal to a signal generated by a transistor pulling one terminal of a reference capacitor.
• Such an implementation utilizes a single driver having its output based upon the relationship of the output signal of the driver and the signal associated with the reference capacitor. Because one leg of the amplifier from each differential pair will directly drive a final output transistor of a pull-up or pull-down driver, large switched amplifiers are often needed. Such large switched amplifiers have the disadvantage of low speed.
• Conventional slew rate controllers respond to a signal transition at a predetermined value of the time derivative of voltage (dN/dt) and act to limit dN/dt thereafter.
• dN/dt time derivative of voltage
• slew rate controllers typically affect the slew rate by controlling dN/dt
• slew rate controllers do little to directly control the time derivative of current (dl/dt).
• the initial component of dl/dt waveforms for different loads are substantially identical and take the form of a pulse which has already occurred by the time conventional slew rate controllers respond to dN/dt.
• dN/dt is controlled by conventional solutions, the initial pulse in dl/dt is substantially unaffected because the increase in dl/dt precedes the increase in the magnitude of dN/dt.
• the similarity of the initial dl/dt components indicates that they are substantially independent of the loading, unlike dN/dt which is load dependent.
• a dN/dt waveform for a relatively large load e.g., 30 ⁇ F in one embodiment
• a dN/dt waveform for a relatively small load e.g., 5pF in one embodiment
• the initial dl/dt is chiefly a function of the current drive of the output transistor and the rate at which the controlling voltage of the output transistor crosses the turn-on threshold.
• the dl/dt during a signal transition for each of a set of conventional drivers on an integrated circuit typically peaks at substantially the same instant in time and is of a magnitude that is substantially load independent.
• the total initial dl/dt generated is the sum of the initial dl dt for each of the drivers. This total dl/dt is often the key factor responsible for electromagnetic interference (EMI) and other undesirable transient effects.
• EMI electromagnetic interference
• FIG. 1 illustrates, in schematic and block form, an embodiment of a portion of a driver in accordance with the present invention
• FIG. 2 illustrates, in block form, a driver in accordance with the present invention
• FIG. 3 illustrates, in block form, a portion of the driver of FIG. 2 in greater detail
• FIG. 4 illustrates, in schematic and block form, the portions of FIG. 2 and 3 in greater detail
• FIGs. 5, 6, and 8 illustrate, in graphical form, curves associated with the voltage, the current and the time derivative of current in accordance with an embodiment the present invention
• FIG. 7 illustrates, in flow diagram form, a method in accordance with the present inventions.
• FIG. 9 illustrates, in block diagram form, an alternate embodiment of driver in accordance with the present invention.
• a primary driver is activated to drive an output signal in response to an input signal.
• a reference signal is generated in response to the input signal.
• the output signal is compared to the reference signal.
• an auxiliary driver is activated.
• an apparatus such as an integrated circuit, microprocessor, wireless communications device, computer system, etc., includes a driver circuit for driving an output signal on an output terminal.
• the output signal corresponds to an input signal received at an input of the driver circuit.
• the driver circuit includes primary and auxiliary drivers, and a slew rate control circuit.
• the primary driver is coupled to the driver circuit input and the output terminal.
• the slew rate control is circuit coupled to the driver circuit input.
• the auxiliary driver is coupled to the slew rate control circuit and the output terminal.
• the slew rate control circuit controls activation of the auxiliary driver.
• the slew rate control circuit may include circuitry to activate the auxiliary driver after activation of the primary driver (e.g., depending on a comparison of a reference signal and the output signal, for further example, wherein the reference signal differs from the output signal by at least a signal magnitude and/or time lag threshold).
• the slew rate control circuit may further include circuitry for augmenting the transition of the output signal to a degree depending upon a magnitude of difference between the output signal and the reference signal.
• the slew rate control circuit may further include circuitry for determining (e.g., advancing or delaying) the deactivation time of the auxiliary driver.
• an apparatus in another embodiment, includes primary and secondary drivers and a voltage change measurement circuit.
• the voltage change measurement circuit is coupled to provide a control signal depending upon a change in voltage with respect to time of an output of the primary driver.
• the secondary driver is coupled to the voltage change measurement circuit and the primary driver, the secondary driver being activated depending on the control signal.
• a method of driving an output signal using auxiliary drive capability when required includes the following operations: activating a primary driver to drive an output signal responsive to receiving an input signal; generating a reference signal responsive to receiving the input signal; comparing the output signal with the reference signal; and activating an auxiliary driver if the output signal lags the reference signal by a lag threshold.
• a method of driving an output signal using conditional auxiliary drive capability includes the following operations: initiating driving a transition of an output signal responsive to receiving an input signal by a primary driver; and augmenting driving the transition of the output signal by an auxiliary driver responsive to the output signal.
• FIG. 2 illustrates a system 201 comprising a load capacitance compensated buffer 205 in accordance with the present invention.
• the system 201 can be a discrete buffer component, a portion of a microprocessor, or a portion of computer system incorporating such a buffer.
• the illustrated embodiment of the buffer 205 includes pre-drivers 210 and 230, pull-up driver 220, pull-down driver 240, and terminal 250.
• the pre-drivers 210 and 230 When buffer 205 is enabled for output to terminal 250, the pre-drivers 210 and 230 will be configured to receive a common signal or similar signals (not illustrated) and provide signals labeled INI and IN2 on nodes 211 and 231 respectively.
• the INI signal is received by pull-up driver 220, which in turn drives terminal 250.
• the IN2 signal is received by pulldown driver 240, which in turn drives terminal 250.
• the pre-drivers 210 and 230 are used to condition the common signal for use by drivers 220 and 240 respectively. Included in the pre-driver conditioning is timing control, to assure the pull-up and pull-down drivers 220 and 240 are not simultaneously activated, and conditioning of the voltage and current levels of the signals INI and IN2 to assure proper interface with the components internal to the drivers 220 and 240.
• the pull-up driver 220 controls slew rate (dN/dt) and dl/dt of a signal at terminal 250 during a pull-up transition.
• the pull-up driver 220 includes a primary driver and an auxiliary driver.
• the primary driver provides an initial dl/dt having relatively stable peak magnitude relative to loading at the terminal 250.
• the auxiliary driver provides an initial dl/dt having a peak in magnitude delayed from the peak of the dl/dt of the primary driver (see, e.g., positive portions of waveforms in FIG. 6), however, the initial dl/dt peak of the auxiliary driver may vary based upon the capacitance of the load at terminal 250.
• the pull- down driver 240 provides a primary and auxiliary driver.
• the initial dl/dt is partitioned over time based upon capacitive loading and the magnitude of dl/dt varies based on the load. Therefore, the peak of the initial dl/dt for each buffer is reduced. Also, when a number of I/O drivers are switched simultaneously on an integrated circuit, the magnitude of the total initial dl/dt of the integrated circuit is reduced as compared to the total initial dl/dt of conventional circuits.
• FIG. 3 illustrates a more detailed view of the pull-down driver 240 of FIG. 2.
• Pulldown driver 240 includes slew rate control 320, optional filter 350, auxiliary driver 340, and primary driver 360.
• FIG. 3 illustrates the terminal 250, which is driven by the pull-down driver 240.
• a corresponding pull-up driver 220 may exist having similar and/or complementary components and functions to those illustrated in FIG. 3 and discussed herein.
• the terminal 250 is driven by the primary driver 360 and the auxiliary driver 340.
• the primary driver 360 receives the I ⁇ 2 signal from the pre-driver. In response, the primary driver 360 drives the terminal 250.
• the slew rate control 320 receives the signal TN2, and a representation of the output terminal 250. Based upon these two signals, the slew rate control 320 provides a control signal to the auxiliary driver 340, which in tum also drives the terminal 250.
• the signal at terminal 250 is received by the optional filter 350 which conditions the output signal for use by the slew rate control 320.
• the signal IN2 is used to generate a slew reference signal that is an idealized representation of the output signal due to the primary driver 360.
• An idealized representation of the output signal due to primary driver 360 refers to a time varying reference signal generated by the slew reference generator 322 based upon the signal IN2, which also controls the primary driver 360. Furthermore, the representation is considered idealized because it is not subject to load variations. Based upon the slew reference signal and the signal from the output terminal 250, the slew rate control 320 controls whether or not the auxiliary driver is to be activated.
• the auxiliary driver is activated if the output signal voltage lags by some ' predefined difference amount or "delta" which can be fixed. If so, it is an indication that the slew rate of the output signal at the terminal 250 can benefit from additional drive. Therefore, a control signal is generated by slew rate control 320 to drive the gate of the auxiliary driver, thereby augmenting the preliminary driver 360.
• the slew rate control 320 includes an off delay portion 326, and a comparator 324.
• the comparator 324 receives a representation of the output signal from terminal 250, which may be filtered by an optional filter 350, and a slew reference signal from the slew reference generator 322.
• a control signal drives the auxiliary driver through the off delay portion 326.
• the off delay 326 extends, or holds, the control signal of the auxiliary driver asserted after the comparator stops driving it.
• the combination of slew reference generator 322 and comparator 324 delay generation of the control signal as compared to the slew reference signal.
• the delay is the result of a threshold voltage associated with comparator 326.
• the delay can be generated prior to the comparator 324, for example, by the slew reference generator.
• the amount of delay generated defines how much time separation exists between the initial dl/dt spikes of the primary and auxiliary output drivers. This helps to reduce the magnitude of the total dl dt through the combined sources of the primary and auxiliary output transistors.
• FIG. 5 illustrates curves representing the voltage at terminal 250 and the control signal voltage at the auxiliary driver 340 for various capacitance values.
• curves 520 represent voltage at terminal 250 for loads of 5pF, 20pF, 35pF, and 50pF.
• the curves 510 represent the voltage of the signals driving the gate of the auxiliary driver 340 for the various load capacitances.
• the curves 510 illustrate that for lower capacitance loads, the gate of the auxiliary driver 340 is not asserted as fully as for higher capacitance loads.
• the terminal voltage represented by curves 520 is modified by the auxiliary driver.
• the slope of each curve in group 520 is substantially similar, indicating similar slew rates.
• FIG. 6 illustrates curves representing dl/dt of the signal at terminal 250.
• the dl/dt curves are associated with the curves 520 of FIG. 5.
• Curves 610 have a substantially similar dl/dt magnitude at location 615 which is the initial dl/dt of the primary driver 360.
• the initial dl/dt curve of the primary driver does not vary significantly based upon the capacitance of the load.
• the initial dl/dt component associated with the auxiliary driver 340 does vary based upon the capacitance of the load.
• the initial dl dt of the auxiliary driver is offset from the dl/dt component of the primary driver (e.g., by approximately Ins). This is the delay influenced by the slew reference generator 322 and comparator 324. Also, the initial dl dt magnitude of the auxiliary driver depends upon the load capacitance at terminal 250.
• the initial dl/dt component attributable to the auxiliary driver 340 has been observed to be approximately 28MN/s (mega-amperes per second); for a 35pF load the initial dl/dt component attributable to the auxiliary driver 340 has been observed to be approximately 20MNs; for a 20pF load the initial dl/dt of the auxiliary driver 340 has been observed to be approximately 18MN/s; and for a 5pF load, the initial dl/dt component has been observed to be negligible as compared to the components provided by the primary driver 360.
• Delaying generation of the auxiliary driver current is advantageous because it allows the total dl dt associated with the driver 240 to be distributed over a longer period of time, thereby reducing the magnitude of dl dt.
• allowing the initial dl/dt of the auxiliary driver to vary with capacitance prevents overdriving. This is advantageous over some conventional designs which drive all output terminals with a dl/dt characteristic based upon a maximum expected load and maximum allowed propagation delay. Such designs thus fail to regulate the EMI associated with dl/dt.
• FIG. 4 illustrates one embodiment of the blocks of FIG. 3 in greater detail.
• FIG. 4 includes circuit and block diagram components to illustrate a specific embodiment of FIG. 3.
• FIG. 7 illustrates a flow diagram for a method related to the functionality of the circuit described herein. The discussion of FIG. 4 will reference steps in FIG. 7.
• the signal IN is received by an inverting level shifter 410 and a pre- driver 405.
• the pre-driver 230 of FIG. 2 is analogous to the pre-driver 405 in FIG. 4.
• the level shifter 410 is optional, and is generally used to provide an interface between a core positive supply voltage and a different, generally higher, positive supply voltage associated with the driver 240 (IO-NDD). In this example, the level shifter is used to assure the p-type MOSFET 424 can be completely turned off.
• the output of the pre- driver 405 drives the control electrode of n-type transistor 460 which is the primary driver (see step 720 of FIG. 7), and the control electrode of n-type transistor 420 of slew reference generator 422. Transistor 420 thus serves as a current mirror of transistor 460.
• slew reference generator 422 is analogous to slew reference generator 322 of FIG. 3.
• Slew reference generator 422 includes an n-type transistor 420 which mirrors the primary driver transistor 460, a p-type transistor 424, and a capacitor 430.
• the mirror transistor 420 has a control electrode coupled to the pre-driver 405, a first current electrode, and a second current electrode coupled to a voltage reference of Nss.
• the p-type transistor 424 has a first current electrode coupled to a fixed voltage reference of the pull-down driver 240 (IO-NDD), a second current electrode coupled to the first current electrode of the transistor 420, and a control electrode coupled to the inverting level shifter 410.
• Capacitor 430 includes a first electrode coupled to IO-NDD, and a second electrode coupled to the first electrode of the transistor 420.
• the transistor 420 of slew reference generator 422 provides a current that mirrors the primary transistor 460. (See also step 730 of FIG. 7.)
• transistor 420 is approximately one-tenth the gate width of the primary driver 460.
• the mirrored current causes a time varying signal to be generated at electrode 425.
• the signal from the electrode 425 is provided to a control electrode of transistor 429 which acts as a comparator of the signal from the electrode 425 output by slew reference generator 422 and the signal at terminal 250.
• the transistor 429 has a first current electrode coupled to terminal 250, and a second current electrode coupled to provide a control signal.
• the off delay portion 426 is analogous to the off delay 326 of FIG. 3, and includes capacitor 427 and resistive element 428.
• the capacitor 427 has a first electrode coupled to the second current electrode of the transistor 429, and a second electrode coupled to Nss.
• the resistive element 428 has a first electrode coupled the first electrode of the capacitor 427, and a second electrode coupled to Nss.
• the capacitor 427 of off delay 426 is charged when comparator transistor 429 is on.
• the control electrode of auxiliary driver 440 is driven for a predetermined amount of time after the transistor 429 has shut off.
• Transistor 440 is analogous to the auxiliary driver 340 of FIG. 3.
• Transistor 440 has a first current electrode coupled to the terminal 250, a second current electrode coupled to Nss, and a control electrode coupled to the first node of the capacitor 427.
• the transistor 429 operates as a voltage difference measurement circuit that determines when the voltage delta ( ⁇ ) between the voltage of the terminal 250 and the voltage of the slew reference signal at node 425 is greater than a predetermined DELTA ( ⁇ ).
• DELTA is equal to the threshold voltage of transistor 429.
• the transistor 429 turns on causing the auxiliary transistor 440 to actively drive the terminal 250. (See step 750 of FIG. 7.)
• the output signal from transistor 429 is delayed from the slew reference signal received at its gate based upon the threshold voltage of transistor 429. Once activated, transistor 429 causes the current drive of the output signal to be augmented. (See step 760 of FIG. 7).
• the resistive element 428 will generally be selected to be an active device. By using an active device, variations in process, temperature, and voltages, can be minimized, in that the active device can be chosen to generally track the variances associated with the auxiliary driver 440. As a result, it is possible for relatively uniform current performance to be maintained across the various process and operating conditions. Furthermore, by using active devices for the element 428, special processes for manufacturing high precision resistors are not necessary.
• FIG. 9 illustrates an alternate embodiment of the present invention, whereby multiple auxiliary drivers 940 and 941 are used.
• Such an implementation allows the EMI and other effects of dl/dt to be further controlled and diminished. For example, by further delaying the generation of the driver current to allow the total dl/dt associated with the driver to be distributed over a longer period of time, the magnitude of dl/dt is thereby reduced.
• FIG. 1 illustrates another embodiment of the present invention in which a primary driver is activated to drive an output signal in response to an input signal, and an auxiliary driver is activated to drive the output signal in response to a similar but phase shifted (e.g., delayed) representation of the input signal.
• the auxiliary driver receives the delayed signal in the presently discussed embodiment, the primary driver may receive the delayed signal in another embodiment.
• the auxiliary driver When the output signal is pulled to a predefined threshold, the auxiliary driver is deactivated.
• the IO-NDD and core NDD are substantially the same positive supply voltage.
• the signal IN is received by a pre-driver 1010.
• the output of the pre- driver 1010 drives the control electrode of the primary pull-down driver 1030.
• Delay circuit 1050 produces IN2D, a representation of the IN signal delayed with respect to IN by a predetermined time interval.
• the signal IN2D is in turn received by auxiliary pre-driver 1020.
• the output of the auxiliary pre-driver 1020 drives the control electrode of the auxiliary pull-down driver 1040.
• the pre-driver 405 in FIG. 4 is analogous to pre-driver 1010 in FIG. 1.
• the primary pull-down driver 460 in FIG. 4 is analogous to primary pull-down driver 1030 in FIG. 1. Slew reference generator 422 and comparator 429 in FIG 4.
• delay portion 1050 are replaced in this embodiment by delay portion 1050, and the p-type transistors in the pre-driver 1020 in FIG. 1.
• Off delay portion 426 in FIG. 4 is replaced in this embodiment by inverter 1070 and the n-type transistors in the pre-driver 1020 in FIG. 1.
• the input of an inverter 1070 receives a representation of the output signal from terminal 1090, which may be filtered by an optional filter 1060.
• the n-type and p-type transistors in the inverter 1070 are sized such that the trip point of the inverter 1070 is approximately a p-MOSFET threshold below NDD.
• the output of the inverter 1070 deactivates auxiliary pre-driver 1020, which in turn deactivates the auxiliary pull-down driver 1040.
• the turning off of the auxiliary pull-down driver 1040 occurs some total feedback delay after primary pull-down driver 1030 begins pulling the output terminal 1090.
• This total feedback delay may be described, for convenience, as consisting of a first delay and a second delay.
• the first delay is an output slew delay attributable to the pulling of the output terminal 1090 to a threshold below NDD.
• a second delay is a signal propagation delay through the inverter 1070 and the auxiliary pre-driver 1020.
• the output slew delay is substantial compared to the propagation delay through the inverter 1070 and the auxiliary pre-driver 1020.
• the duty time of auxiliary pull-down driver 1040 varies based substantially upon the output slew delay, which varies based upon the load on terminal 1090.
• resistive and capacitive elements may be active devices.
• other implementation using transistors of different types than those described herein may be utilized to implement other embodiments of the present invention.
• transistors having a control electrode and current electrodes other terms such as control and current terminals, current handling terminals, current nodes, and the like can be used.
• insulated gate FETs are commonly referred to as MOSFET devices (which literally is an acronym for "Metal-Oxide-Semiconductor Field Effect Transistor"), even though the gate material may be polysilicon or some material other than metal, and the dielectric may be oxynitride, nitride, or some material other than an oxide.
• MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
• the claim reads on the apparatus or method regardless of whether the apparatus or method includes another such similar feature.
• This use of the word "a” as a nonlimiting, introductory article to a feature of a claim is adopted herein by Applicants as being identical to the interpretation adopted by many courts in the past, notwithstanding any anomalous or precedential case law to the contrary that may be found.
• a claim element is described in the claims below as including or comprising an aforementioned feature (e.g., "the” feature), it is intended that that element not be limited to one and only one of the feature described.
• each example presented herein is a nonlimiting or nonexclusive example, whether or not the terms nonlimiting, nonexclusive or similar terms are contemporaneously expressed with each example.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Computing Systems (AREA)
• General Engineering & Computer Science (AREA)
• Mathematical Physics (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Electronic Switches (AREA)
• Logic Circuits (AREA)
• Tests Of Electronic Circuits (AREA)
• Amplifiers (AREA)

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• 2000
  • 2000-03-20 US US09/528,857 patent/US6313664B1/en not_active Expired - Lifetime
• 2001
  • 2001-03-02 AU AU2001247259A patent/AU2001247259A1/en not_active Abandoned
  • 2001-03-02 WO PCT/US2001/006759 patent/WO2001071915A2/en not_active Ceased
  • 2001-03-02 CN CNB018082157A patent/CN1223089C/zh not_active Expired - Lifetime
  • 2001-03-02 JP JP2001569972A patent/JP4903340B2/ja not_active Expired - Fee Related
  • 2001-03-02 KR KR1020027012436A patent/KR100714668B1/ko not_active Expired - Lifetime
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