AU2001247259A1 - Load capacitance compensated buffer, apparatus and method thereof - Google Patents

Load capacitance compensated buffer, apparatus and method thereof

Info

Publication number
AU2001247259A1
AU2001247259A1 AU2001247259A AU4725901A AU2001247259A1 AU 2001247259 A1 AU2001247259 A1 AU 2001247259A1 AU 2001247259 A AU2001247259 A AU 2001247259A AU 4725901 A AU4725901 A AU 4725901A AU 2001247259 A1 AU2001247259 A1 AU 2001247259A1
Authority
AU
Australia
Prior art keywords
load capacitance
compensated buffer
capacitance compensated
buffer
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001247259A
Other languages
English (en)
Inventor
Geoffrey B. Hall
Pedro Ovalle
Dzung T. Tran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU2001247259A1 publication Critical patent/AU2001247259A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching
    • H03K17/167—Soft switching using parallel switching arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Amplifiers (AREA)
AU2001247259A 2000-03-20 2001-03-02 Load capacitance compensated buffer, apparatus and method thereof Abandoned AU2001247259A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/528,857 US6313664B1 (en) 2000-03-20 2000-03-20 Load capacitance compensated buffer, apparatus and method thereof
US09528857 2000-03-20
PCT/US2001/006759 WO2001071915A2 (en) 2000-03-20 2001-03-02 Load capacitance compensated buffer, apparatus and method thereof

Publications (1)

Publication Number Publication Date
AU2001247259A1 true AU2001247259A1 (en) 2001-10-03

Family

ID=24107476

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001247259A Abandoned AU2001247259A1 (en) 2000-03-20 2001-03-02 Load capacitance compensated buffer, apparatus and method thereof

Country Status (7)

Country Link
US (1) US6313664B1 (enExample)
JP (1) JP4903340B2 (enExample)
KR (1) KR100714668B1 (enExample)
CN (1) CN1223089C (enExample)
AU (1) AU2001247259A1 (enExample)
TW (1) TW523988B (enExample)
WO (1) WO2001071915A2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003337640A (ja) * 2002-05-21 2003-11-28 Mitsubishi Electric Corp バス制御装置
US6842058B2 (en) * 2002-11-12 2005-01-11 Lsi Logic Corporation Method and apparatus for slew control of an output signal
KR100510515B1 (ko) 2003-01-17 2005-08-26 삼성전자주식회사 공정의 변화에 따라서 클럭신호의 듀티 사이클을 보정하는듀티 사이클 보정회로를 구비하는 반도체 장치
DE10355509A1 (de) * 2003-11-27 2005-07-07 Infineon Technologies Ag Schaltung und Verfahren zum verzögerten Einschalten einer elektrischen Last
JP5239976B2 (ja) * 2009-03-19 2013-07-17 富士通セミコンダクター株式会社 入力回路および半導体集積回路
WO2013017913A1 (en) * 2011-08-01 2013-02-07 Freescale Semiconductor, Inc. Signalling circuit, processing device and safety critical system
TW201535975A (zh) 2014-03-10 2015-09-16 Chunghwa Picture Tubes Ltd 閘極驅動電路
US9584104B2 (en) 2014-03-15 2017-02-28 Nxp Usa, Inc. Semiconductor device and method of operating a semiconductor device
US9202584B1 (en) 2014-05-08 2015-12-01 Freescale Semiconductor, Inc. Power supply slew rate detector
JP6195393B1 (ja) * 2016-03-23 2017-09-13 ウィンボンド エレクトロニクス コーポレーション 出力回路
KR102598741B1 (ko) * 2018-07-17 2023-11-07 에스케이하이닉스 주식회사 데이터 출력 버퍼

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58121610A (ja) * 1982-10-05 1983-07-20 Taamo:Kk 係合具
US4567378A (en) * 1984-06-13 1986-01-28 International Business Machines Corporation Driver circuit for controlling signal rise and fall in field effect transistor processors
JPH04154314A (ja) * 1990-10-18 1992-05-27 Nec Ic Microcomput Syst Ltd 出力回路
JPH04274615A (ja) * 1991-02-28 1992-09-30 Nec Corp 出力バッファ回路
JP3251661B2 (ja) 1991-10-15 2002-01-28 テキサス インスツルメンツ インコーポレイテツド 制御されたスルー・レートを有するｃｍｏｓバッファ回路
JPH05327443A (ja) * 1992-05-15 1993-12-10 Nec Corp バッファ回路
US5619247A (en) * 1995-02-24 1997-04-08 Smart Vcr Limited Partnership Stored program pay-per-play
US5598119A (en) * 1995-04-05 1997-01-28 Hewlett-Packard Company Method and apparatus for a load adaptive pad driver
US5739715A (en) * 1995-10-31 1998-04-14 Hewlett-Packard Co. Digital signal driver circuit having a high slew rate
US5986489A (en) * 1996-04-03 1999-11-16 Cypress Semiconductor Corp. Slew rate control circuit for an integrated circuit
JP3339311B2 (ja) * 1996-07-16 2002-10-28 富士電機株式会社 自己消弧形半導体素子の駆動回路
KR100226491B1 (ko) * 1996-12-28 1999-10-15 김영환 반도체 메모리에서 비트라인 감지 증폭기의 풀업/풀다운 전압제 공을 위한 디바이스 및 그 구성 방법
US6184703B1 (en) * 1997-06-06 2001-02-06 Altera Corporation Method and circuit for reducing output ground and power bounce noise
US6118324A (en) * 1997-06-30 2000-09-12 Xilinx, Inc. Output driver with reduced ground bounce
US5949259A (en) * 1997-11-19 1999-09-07 Atmel Corporation Zero-delay slew-rate controlled output buffer
US6181156B1 (en) * 1999-03-31 2001-01-30 International Business Machines Corporation Noise suppression circuits for suppressing noises above and below reference voltages
FR2945413B1 (fr) * 2009-05-15 2011-05-06 Aplix Sa Element d'accrochage pour former la partie male d'un auto-agrippant
JP5949259B2 (ja) * 2012-05-25 2016-07-06 三菱電機株式会社 液晶表示装置
JP5986489B2 (ja) * 2012-11-21 2016-09-06 株式会社ハーマン グリル

Also Published As

Publication number Publication date
CN1425220A (zh) 2003-06-18
US6313664B1 (en) 2001-11-06
WO2001071915A3 (en) 2002-02-14
JP4903340B2 (ja) 2012-03-28
KR20030014370A (ko) 2003-02-17
JP2003528525A (ja) 2003-09-24
CN1223089C (zh) 2005-10-12
TW523988B (en) 2003-03-11
WO2001071915A2 (en) 2001-09-27
KR100714668B1 (ko) 2007-05-07

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