WO2001041198A1 - Dispositif a circuit integre a semi-conducteurs et procede de fabrication de ce dernier - Google Patents

Dispositif a circuit integre a semi-conducteurs et procede de fabrication de ce dernier Download PDF

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Publication number
WO2001041198A1
WO2001041198A1 PCT/JP2000/008466 JP0008466W WO0141198A1 WO 2001041198 A1 WO2001041198 A1 WO 2001041198A1 JP 0008466 W JP0008466 W JP 0008466W WO 0141198 A1 WO0141198 A1 WO 0141198A1
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Prior art keywords
circuit
pattern
cells
semiconductor wafer
data
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PCT/JP2000/008466
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English (en)
Japanese (ja)
Inventor
Takahiro Oga
Toshio Yamada
Masakazu Aoki
Kazumasa Yanagisawa
Osamu Suga
Hiroshi Kawamoto
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Hitachi, Ltd
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Publication of WO2001041198A1 publication Critical patent/WO2001041198A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Definitions

  • the present invention relates to a semiconductor integrated circuit device and a manufacturing technology of the semiconductor integrated circuit device, and particularly to a technology effective when applied to a pattern exposure technology using an energy beam such as an electron beam.
  • Exposure technology using an electron beam or the like is a technology that exposes a target pattern by irradiating an electron beam photosensitive resist film with an appropriately squeezed electron beam instead of light as an exposure light source to cause a chemical change. Because of its high resolution, deep depth of focus, and highly flexible alignment function, it is promising for further miniaturization of patterns.
  • the so-called variable shaped beam method in which exposure is performed while controlling the size of the exposure surface of the electron beam, is the mainstream for both mask and reticle production and direct wafer writing.
  • variable shaped beam method after the electron beam emitted from the electron gun is shaped by the aperture of the first shaped aperture plate, the relative planar positional relationship between the shaped electron beam and the second shaped aperture plate Is adjusted by using a deflection system dedicated to molding, whereby the planar shape of the pattern exposed to the resist film is molded into the target shape and dimensions.
  • a predetermined pattern or pattern group is formed in advance in the second forming aperture plate (partial blanket exposure mask), and the predetermined pattern or pattern is formed. This is a technology for transferring a group to a resist film on a semiconductor wafer at one time. By using this method, the pattern exposure time can be significantly reduced.
  • This partial batch exposure method is described in, for example, USP 5 3 3 4 8 by Wakabayashi. 45 (registered Aug. 8, 1994), a first opening formed with a first pattern, a second opening formed with a second pattern repeating the first pattern, and a rectangular pattern
  • an exposure technique of a pattern for exposing a wafer by irradiating the wafer with a beam that has passed through a mask substrate having a third opening in which a pattern is formed For example, Sakitani et al., J. Vac. Sci. Tecnho 1. B10 (6), Nov / Dec 1992, p 2759-p 2763, describe the partial batch exposure method as AS IC. It is disclosed when applied to the manufacture of (Application Specific IC). 44 (1995), No. 2, p. 85-90 by Mizuno et al. Describes the case where the partial batch exposure method is applied to the manufacture of DRAM (Dynamic Random Access Memory). Is disclosed.
  • the present inventors have found that the partial batch exposure technique has the following problems.
  • An object of the present invention is to provide a technique capable of shortening a manufacturing time of a semiconductor integrated circuit device.
  • Another object of the present invention is to provide a technique capable of improving the throughput in manufacturing a semiconductor integrated circuit device.
  • a circuit cell is configured to have a plurality of sub-cells that can be used in common by a plurality of circuit cells, and a surplus pattern exists in a sub-cell constituting one circuit cell. It is.
  • the present invention provides a circuit cell having a configuration having a plurality of sub-cells which can be used in common for the plurality of circuit cells, and, when transferring an entire pattern of the circuit cell, a partial batch exposure for each pattern of each sub-cell. It has a step of performing processing.
  • FIG. 1 is a plan view of an inverter cell, which is one type of circuit cell.
  • FIG. 2 is an explanatory diagram schematically showing the sizes of various circuit cells.
  • FIG. 3 is an explanatory diagram of a composite gate circuit.
  • FIG. 4 is an explanatory diagram when the composite gate circuit of FIG. 3 is disassembled.
  • FIG. 5 is an explanatory diagram of a rising edge trigger flip-flop circuit.
  • FIG. 6 is an explanatory diagram when the composite gate circuit of FIG. 5 is disassembled.
  • FIGS. 7A to 7H are plan views of specific examples of the layout data of the subcell in the semiconductor integrated circuit device manufacturing technique according to an embodiment of the present invention.
  • 8 (a) to 8 (e) are plan views showing each layout layer of the subcell of FIG. 7 (a).
  • FIGS. 9 (a) and 9 (e) are plan views showing each layout layer of the subcell of FIG. 7 (b).
  • FIGS. 10 (a) to 10 (e) are plan views showing each layout layer of the subcell of FIG. 7 (c).
  • FIGS. 11A to 11E are plan views showing each layout layer of the subcell of FIG. 7D.
  • FIGS. 12A and 12E are plan views showing each layout layer of the subcell of FIG. 7E.
  • FIGS. 13 (a) to 13 (e) are plan views showing each layout layer of the subcell of FIG. 7 (f).
  • FIGS. 14 (a) to (e) are plan views showing each layout layer of the subcell of FIG. 7 (g).
  • FIGS. 15A to 15E are plan views showing each layout layer of the subcell of FIG. 7H.
  • FIG. 16 is a plan view of a pattern layout when the rising edge trigger flip-flop circuit shown in FIGS. 5 and 6 is configured using the subcell of FIG.
  • FIG. 17 is a plan view of a pattern layout when a falling edge trigger flip-flop circuit is formed by changing the combination of subcells used in FIG.
  • FIG. 18 is an explanatory diagram of a manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention.
  • FIG. 19 is an explanatory diagram of an example of an electron beam exposure apparatus used in a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.
  • FIG. 20 is an explanatory diagram of a partial batch exposure technique of the electron beam exposure apparatus of FIG.
  • FIG. 21 is an explanatory diagram of a variable shaping exposure technique of the electron beam exposure apparatus of FIG.
  • FIG. 22 is a plan view of a mask for partial batch exposure of the electron beam exposure apparatus of FIG.
  • FIG. 23 is an enlarged plan view of a main part of the partial batch exposure mask of FIG.
  • FIG. 24 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention during the manufacturing steps thereof.
  • FIG. 25 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG.
  • FIG. 26 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG.
  • FIG. 27 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG.
  • FIG. 28 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG.
  • FIG. 29 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG.
  • FIG. 30 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG.
  • FIG. 31 is an overall plan view of a semiconductor chip constituting a semiconductor integrated circuit device manufactured by a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
  • FIG. 32 is an enlarged plan view of a main part of the semiconductor integrated circuit device of FIG.
  • FIG. 33 is a cross-sectional view of a principal part of the semiconductor integrated circuit device of FIGS. 28 and 29.
  • FIG. 34 is an explanatory diagram of a circuit cell used in this specification.
  • FIG. 35 is an explanatory diagram of the library used in this specification. BEST MODE FOR CARRYING OUT THE INVENTION
  • Circuit cell A generic term for standard cells, macro cells, etc. registered in one or more libraries (see Figures 34 and 35).
  • Standard cell A plurality of, for example, several hundred standard unit logic circuits or signal processing circuits registered in the library as circuit cells. Internal wiring is connected by the lowermost metal wiring, and is classified into normal standard cells that do not use upper metal wiring, etc., and other special standard cells (see Figures 34 and 35).
  • the standard cell can be decomposed into one or a plurality of subcells, and each subcell corresponds to a unit shot of electron beam partial batch direct writing (EB cell projection). Adjacent sub-cells in the same normal standard cell are electrically connected to each other by at least one bottom layer wiring.
  • EB cell projection electron beam partial batch direct writing
  • Macrocell Generally compared to the functional circuit or system circuit designed beforehand, ie, CPU (Central Processing Unit), RAM (Random Access Memory), DSP (Digital Signal Processor) or above standard cell. And large-scale random logic (see Figures 34 and 35).
  • CPU Central Processing Unit
  • RAM Random Access Memory
  • DSP Digital Signal Processor
  • the macro cell region has a non-standard cell portion that cannot be reduced to the standard cell, and can further have a standard cell portion that can be reduced to the standard cell.
  • Cell-based integrated circuits Semi-custom ICs that design standard cell layout areas by extracting standard cells from libraries as appropriate.
  • Partial batch direct writing An energy beam, such as an electron beam (including ion beam or laser direct writing), is applied to the first opening (for example, 25 times the size of the pattern on the semiconductor wafer) and the second opening.
  • a variable rectangular beam (other shapes are possible) is formed with the opening (for example, 25 times the size of the pattern on the semiconductor wafer), and a cell pattern group corresponding to a plurality of predetermined circuit patterns in the second opening.
  • Semiconductor wafer A substrate for forming semiconductor integrated circuit devices, which is generally made of silicon single crystal. Includes substrates that form integrated circuits by forming epitaxy layers and other semiconductor layers and insulating layers on insulators and semiconductor substrates. For example, on an insulating layer Includes SOI (Silicon Icon On Insulator) substrates with semiconductor layers for device formation and epitaxy wafers with epitaxy layers formed on the surface of semiconductor substrates.
  • SOI Silicon Icon On Insulator
  • a semiconductor integrated circuit device refers not only to a device formed on a semiconductor or an insulator substrate such as a silicon wafer or a sapphire substrate but also to a TFT (TFT), unless otherwise specified.
  • TFT TFT
  • STN thin-film-transistor
  • STN super-twisted-element
  • a common figure is an opening figure or island figure (or linear figure) that constitutes a predetermined process layer of a subcell.
  • the subcell has a common figure of a plurality of layout layers, and has mutual relation information such as a plane position coordinate and an electrical connection state between the common figures of the different layout layers.
  • the layout layers are divided into those that are formed at the same formation / exposure step or at the same processing height. Specifically, active layer, gate layer, contact hole, There is a hole layer such as a through hole or a wiring layer such as a bottom wiring.
  • the bottom wiring is the wiring that electrically connects the elements and electrodes in the standard cell, and is the lowest metal wiring pattern. Usually, they are in direct contact with and electrically connected to the semiconductor regions (for example, source / drain regions) constituting the device.
  • an integrated circuit pattern (also simply referred to as a pattern) constituting a cell-based integrated circuit (semiconductor integrated circuit device) is exposed (transferred) using an exposure technique using a partial batch exposure method.
  • a p-channel type MISFET Metal Insulator Semiconductor Field Effect Transistor
  • nMIS n-channel type MISFET
  • FIG. 1 shows an example of a plan layout diagram of the data in the cell library of the Inverter cell INVC, a type of circuit cell.
  • This inverter cell INVC is, for example, a CMIS (Complementary Metal Insulator Semiconductor) circuit.
  • the active regions LP and LN has active regions LP and LN, a gate portion G, a hole C0NT, and a lowermost layer wiring M0.
  • LP a source / drain of pMIS is formed
  • LN a source / drain of nMIS is formed.
  • the gate portion G is a planar band-shaped pattern forming the gate electrodes of the pMIS and the nMIS, and is disposed so as to cross the active regions LP and LN of both the pMIS and the nMIS.
  • the hole C0NT is a hole pattern connecting different layers, and is formed near the both sides of the gate portion G in a position where the active region LP, LN overlaps in a plane and the gate portion G and the lowermost layer wiring M02 overlap in a plan view. Have been.
  • the lowermost wiring MO (M01, M02) is a wiring that electrically connects the elements and electrodes in the standard cell, and is the lowest metal wiring pattern.
  • the bottom wiring M01 is connected to the active areas LP and LN through the hole C0NT and serves as the output of the CMIS inverter circuit.
  • the bottom wiring M02 is connected to the gate section G through the hole C0NT and serves as the input of the CMIS inverter circuit.
  • the size of this INVA overnight cell INVC is expressed in units of pitch.
  • the height of the Inverter cell INVC (the longitudinal dimension of the Inverter cell INVC) h is 12 pitches
  • the width (the width dimension of the Inverter cell INVC in the width direction) w is 3 pitches.
  • one wiring is equivalent to one pitch.
  • the height h of the INVA overnight cell INVC is 12 pitches, which is 4.8 m.
  • the dimension can be set within one shot in the partial batch exposure of the exposure apparatus used in the present embodiment.
  • FIG. 2 is an explanatory diagram schematically showing the sizes of various circuit cells.
  • the vertical axis represents an example of the cell type, and the horizontal axis represents the cell width.
  • the partial collective exposure cell area CA indicates the area that can be exposed in one shot of the partial collective exposure method, and the partial batch non-exposureable cell area NCA must be exposed in one shot of the partial collective exposure method. Indicates an impossible area.
  • logic LSIs which are cell-based integrated circuits, are designed based on a cell library with a large number of standard cells, such as inverter circuits, NAND circuits, and latch circuits, and by combining the standard cells. It is becoming. Usually, circuit cells are of uniform height. Larger circuit cells have longer widths.
  • the composite gate circuit, flip-flop circuit, and the like have a 12 ⁇ 12 pitch that can be exposed in one shot of the partial batch exposure method (on a semiconductor wafer). About 5 X 5 tm).
  • FIG. 3 shows a composite gate circuit and its size.
  • This composite gate circuit consists of three 3-input AND circuits and one 3-input NOR circuit, and the output of each 3-input AND circuit is electrically connected to the input of the 3-input NOR circuit.
  • the size (height h x width w) of the composite gate circuit is, for example, 12 pitches x 11 to 18 pitches, and can be exposed by one shot of the partial batch exposure method. It doesn't fit on the pitch. Therefore, in the present embodiment, the circuit cell (composite gate circuit) shown in FIG. 3 is divided into subcells SC1 and SC2 each composed of a basic figure which fits in a 12 ⁇ 12 pitch as shown in FIG. .
  • the subcell SC1 has, for example, three 3-input AND circuits and one 3-input OR circuit, and has a width wl of 12 pitches.
  • the subcell SC2 has, for example, one inverter circuit, and its width w2 is 3 to 6 pitches. Since the sub-cells SCI and SC2 can be subjected to partial batch exposure, the entire composite gate circuit can be exposed by performing partial batch exposure for each of the sub-cells SC1 and SC2.
  • FIG. 5 shows a rising edge trigger flip-flop circuit and its size.
  • This rising edge trigger flip-flop circuit is composed of two inverter circuits, four two-input AND circuits, four two-input NOR circuits, and a buffer circuit.
  • the size (height h x width w) of the rising edge trigger flip-flop circuit is, for example, 12 pitches x 15 to 17 pitches, and can be exposed by one shot of the partial batch exposure method. Does not fit in a 12 x 12 pitch. Therefore, in the present embodiment, as shown in FIG. 6, the circuit cell of FIG. 5 is decomposed into subcells SC3, SC4, and SC5 each having a basic figure that fits in a 12.times.12 pitch.
  • the subcell SC6 has, for example, an inverter circuit, two two-input AND circuits, and two two-input NOR circuits, and has a width wl of, for example, 9 pitches.
  • the subcell SC4 has, for example, two inverter circuits, two two-input AND circuits, and two two-input NOR circuits, and has a width w2 of, for example, 9 pitches.
  • Subcells SC3 and SC4 are large The circuit configurations of both circuits are the same except that the output of the inverter circuit is connected to the input of the upper AND circuit in Fig. 6 (SC4) or not (SC3).
  • the circuit configuration of the subcell SC5 is the same as that of the subcell SC2 in FIG.
  • the width w3 is, for example, three pitches. Since the subcells SC3 to SC5 can be subjected to partial batch exposure, the entire rising edge trigger flip-flop circuit can be exposed by performing partial batch exposure for each of the subcells SC3 to SC5. .
  • the sub-cell should be a figure (pattern) that can be used as common as possible (as much as possible) as a component of multiple circuit cells. This allows one subcell to be used for exposure of multiple circuit cells.
  • the subcells vary depending on the arrangement (connection) and combination of two or more subcells or the arrangement (connection) and combination of two or more subcells with standard cells and macrocells.
  • a plurality of circuit cells can be expressed by variously changing the combination method even with a small number of subcells.
  • the present embodiment it is possible to transfer a pattern in one or more types of semiconductor integrated circuit devices as compared with a case where a circuit cell is simply disassembled to constitute a subcell.
  • the number of partial batch exposure patterns (subcells) required for one partial batch exposure mask can be extremely reduced. That is, at the time of pattern exposure of one or more types of semiconductor integrated circuit devices, it becomes possible to expose all or most of the patterns by partial batch exposure processing. Therefore, the exposure time of all the patterns in the semiconductor integrated circuit device can be significantly reduced. did Therefore, the development period and manufacturing time of the semiconductor integrated circuit device can be significantly reduced. Further, the throughput of the semiconductor integrated circuit device can be greatly improved.
  • the mask for the partial batch exposure of the partial batch electron beam exposure apparatus requires only about 1Z4 to 1Z5 of the mask of the exposure apparatus using an excimer laser beam as a light source, the manufacturing cost of the semiconductor integrated circuit device can be reduced. It can be promoted. These effects can be obtained for the transfer of a pattern on a photomask.
  • FIGS. 7 to 15 show specific examples of the layout data in the cell library of such a subcell.
  • (B) to (e) of FIGS. 8 to 15 show the respective figures (a) separated into respective layout layers. 8 to 15 show the X and Y coordinates so that the relative planar positional relationship between the patterns of each layout layer can be understood.
  • the sub-cell SC A is a layout representation of the sub-cells SC 2 and SC 5, and includes an active region LPA, LNA, a gate portion GA, a plurality of holes C0NTA, and two lowermost-layer wirings MOA (M0A1, M0A). 2)
  • the subcell SCB has the same configuration as the above-mentioned CMIS inverter cell INVC, and has an active area LPB (LP), LNB (LN), a gate GB (G), a hole C0NTB (C0NT), and a lowermost layer.
  • Wiring MOB (MOB1, MOB2, M0).
  • the subcell SCB has a longer dimension in the longitudinal direction of the subcell SCB of the active regions LPB and LNB than the subcell SCA. Other than that, it is the same as the subcell SCA.
  • active area LPB, LNB, gate part GB,? L C0NTB and the bottom layer wiring MOB (MOB1, MOB2) are respectively the active area of the CMIS inverter cell INVC.
  • the subcell SCC has active regions LPC and LNC, two gate parts GC, a hole CNTC, and two bottom wirings MOC (M0C1, M0C2). Active areas LPC and LNC are the same as active areas LPB and LNB of subcell SCB. Gate GC is arranged in two parallels across the active area LP LNC. I have.
  • the hole CONK is a region for connecting different layers, and is arranged near the gate portion GC so as to overlap the active regions LPC and LNC.
  • the bottom wiring M0C1 is arranged between the two gates GC and has information electrically connected to the active regions LPC and LNC through the hole C0NTC. What is the bottom wiring M0C2? It has information that is electrically connected to the two gates GC through LC0NTC.
  • the subcell SCD has active regions LPD and LND, a gate portion GD, a hole C0NTD, and a lowermost layer wiring MOD (MOD1, MOD2).
  • This subcell SCD differs from the subcell SCA in the position of the lowermost layer wiring MOD2, the position of the wide portion of the gate portion GD, and the position of the hole C0NTD connecting them. The rest is the same as the subcell SC A.
  • the subcell SCE has active regions LPE and LNE, a gate GE, a hole C0NTE, and a lowermost wiring MOE (M0E1, M0E2).
  • the dimension in the Y-axis direction of the active regions LPD and LND of the subcell SCE is wider than that of the subcell SCD. Otherwise, it is the same as the subcell SCD.
  • the subcell SCF has active regions LPF and LNF, two gate portions GF, a hole CONTF, and a lowermost wiring MOF (M0F1, M0F2).
  • the position of the lowermost layer wiring M0F2 of the subcell SCF, the position of the wide portion of the gate GF, and the position of the hole C0NTF connecting them are different from those of the subcell SCC. Otherwise, it is the same as the subcell SCC.
  • the sub-cell SCG is a layout representation of the above-described sub-cell SC3 (see FIG. 6), and includes active regions LPG and LNG, a plurality of gates GG, a plurality of holes C0NTG, and a plurality of lowermost wirings M0G. ing.
  • the sub-cell SCH is a layout representation of the above-described sub-cell SC4 (see FIG. 6), and has an active region LPH, LNH, a plurality of gate portions GH, a plurality of holes C0NTH, and a plurality of lowermost wiring lines M0H. are doing.
  • These subcells SCA to SCH are not independent ones, but can be combined appropriately to form a predetermined circuit cell.
  • the state (for example, plane position coordinates and dimensions) of the patterns (for example, the gate section and the lowermost layer wiring) constituting the cells SCA to SCH are designed to have relevance and commonality.
  • the heights of the subcells SCA to SCH are all equal, for example, 12 pitches.
  • the cell width of the subcells SCA to SCF is, for example, 3 pitches.
  • the cell width of the subcells SCG and SCH is, for example, 9 pitches.
  • the active regions LPA to LPH are regions where the source and drain of pMIS are formed, and the active regions LNA to LNH are regions where the source and drain of nMIS are formed.
  • the gate portions GA to GH are regions where a MIS gate electrode is formed. Holes CONTA to C0NTH are hole patterns connecting different layers.
  • the lowermost wirings M0A to M0H are wirings for electrically connecting elements and electrodes in the circuit cell, and are the lowermost metal wiring patterns. Here, all the wirings in the subcells SCA to SCH are performed by the lowermost wirings M0A to M0H.
  • FIG. 16 is a plan view of the pattern layout over time when the rising edge trigger flip-flop circuit shown in FIGS. 5 and 6 is configured using the subcells SCC, SCG, and SCH. I have.
  • Subcell SCH is arranged at the subsequent stage of subcell SCG, and subcell SCC is arranged at the subsequent stage.
  • the rising edge trigger flip-flop circuit is configured by electrically connecting the subcells SCC, SCG, and SCH by the lowermost wirings M0C, MOG, and M0H.
  • Each subcell SCC, SCG, SCH fits in a 12 x 12 pitch as described above, so each subcell SCC, SCG, SCH has its own layout layer.
  • Exposure can be performed by one shot partial exposure.
  • FIG. 17 is a plan view of a pattern layout on data when a falling edge trigger flip-flop circuit is configured using the same subcells SCC, SCG, and SCH as described above.
  • the falling edge trigger flip-flop circuit is also formed by electrically connecting the subcells SCC, SCG, and SCH with the bottom wiring M0C, MOG, and M0H.
  • the layout configuration of the falling edge trigger flip-flop circuit is configured by replacing the arrangement order of the subcells SCG and SCH with the rising edge trigger flip-flop circuit. ing. In other words, different circuits can be expressed simply by changing the combination (arrangement) of the subcells SCG and SCH.
  • FIGS. 16 and 17 show the layout data, the pattern actually transferred onto the semiconductor wafer / photomask has almost the same planar shape.
  • flip-flop circuits there are two types: trigger (positive edge (rising edge), negative edge (falling edge)), output polarity (Q, Q), and output driver parity.
  • sub-cells SC having commonality and mutual combination as in this embodiment it is possible to expose 12 types of flip-flop circuits with eight exposure figures. Therefore, the number of patterns (partial batch exposure patterns, ie, sub-cell patterns) formed on the mask for partial batch exposure can be significantly reduced.
  • the shape of the pattern of each part in the subcells SCA to SCH may be the same.
  • the gate portions GA and GB of the subcells SCA and SCB, the holes C0NTA and C0NTB, and the lowermost wirings MOA and MOB have the same pattern shape. So, in such a case, it is also possible to form only one pattern of the same shape on the mask for partial batch exposure and use that pattern for exposing the pattern of a plurality of subcells. That is, the mask pattern formed on the partial batch exposure mask can be used for exposing a pattern of a plurality of subcells. Thus, the number of patterns required for the partial batch exposure mask can be further reduced. As described above, when a common pattern exists in a subcell, information such as exposure using a predetermined pattern of another subcell when exposing the pattern is described as information of the subcell.
  • a pattern portion that does not directly contribute to the circuit configuration in the subcell is used. Part
  • a portion of the lowermost-layer wirings M0G and M0H is an excess pattern portion MS (the output terminal side of the subcell, etc.).
  • This surplus pattern portion MS is interrupted at the end without being connected to other components and is interrupted on the way to become a free end, and a rising edge trigger flip-flop circuit and a falling edge trigger flip-flop circuit are provided.
  • FIG. 18 shows an example of the process.
  • the register transfer level is a level that clearly defines the signal transfer (data transfer) during the register operation in the operation of the semiconductor integrated circuit device (step 101).
  • a logic synthesis is performed using the cell library CL (Step 102) to create a gate-level netlist (Step 103).
  • the cell library CL a plurality of circuit cells (standard cells, macro cells, etc.) in a certain generation process are stored as data.
  • each circuit cell in the library CL has common graphic information that can be used in common by a plurality of circuit cells (see FIG. 7).
  • Subcells SCA to SCH, etc.) and their combination information (see FIGS. 16 and 17).
  • the information of the common figure is stored in the file FA
  • the combination information is stored in the file FB.
  • cells that are not decomposed into common figures such as ROM (Read Only Memory) and RAM (Random Access Memory), may be arranged in the cell library CL.
  • the netlist is design data representing the connection relation of the logic circuits of the semiconductor integrated circuit device, and is in a format that can be processed by a computer. In general, connection relations are described hierarchically to make data compact.
  • a stream format is created by laying out the gate-level netlist using a layout tool (step 104) (step 105).
  • the stream format of the cell library CL or the information of the external shape and terminal is required.
  • electron beam (EB; Electron Beam) exposure data conversion is performed using the stream format (step 106).
  • the portion composed of the circuit cells becomes the exposure data DA for partial batch using the common figure (sub-cell) and the combination information, and the other portion becomes the exposure data DB for variable shaping.
  • EB exposure is performed using the exposure data DA for partial batch and the exposure data DB for variable shaping (step 107).
  • Partial batch EB exposure technology is to create a plurality of partial batch exposure patterns in an area (unit deflection area) that can be exposed by beam deflection in the forming aperture plate (aperture) of an electron beam exposure apparatus, and This technology transfers the exposure pattern to the resist film on the semiconductor wafer in one shot.
  • the EB exposure apparatus can directly expose a predetermined pattern on an electron beam resist film (hereinafter simply referred to as a resist film) on a semiconductor wafer, and can use a photomask, a reticle, or a phase shift mask. It is also possible to expose a pattern on a resist film on a mask substrate such as that described above.
  • the mask substrate is a substrate for an optical mask for transferring a predetermined pattern onto a photoresist film on a semiconductor wafer by a normal light projection exposure technique.
  • FIGS. FIG. 19 shows an EB exposure optical system
  • FIG. 20 is an explanatory diagram of partial batch EB exposure
  • FIG. 21 is an explanatory diagram of variable-shaped EB exposure.
  • a semiconductor wafer 2 having the above-described resist film applied to the main surface is set on the processing table.
  • the semiconductor wafer 2 is made of, for example, silicon (Si) single crystal having a substantially circular shape in a plane, and a cutout portion 2a is formed in a part thereof for the purpose of alignment or the like.
  • the first formed aperture plate 1C1 has a rectangular opening (aperture) API.
  • the first forming aperture plate 1C1 is movable in a first direction parallel to the plane and in a second direction parallel to the plane and intersecting the first direction.
  • the second forming aperture plate 1C2 corresponds to the partial batch exposure mask.
  • a plurality of types of openings (unit deflection areas) AP2 are formed in the second formed aperture plate 1C2. In the center of each opening AP 2 is an opening AP for normal variable shaping exposure
  • the opening AP3 for variable shaping exposure is an opening used for normal variable shaping exposure.
  • the partial collective exposure pattern area PA is an opening for forming the partial collective exposure pattern.
  • the second formed drawn plate 1C2 will be described later.
  • the rectangular opening AP1 of the first forming diaphragm plate 1C1 is moved by the mechanical movement of the second forming diaphragm plate 1C2 and the forming lens 1D1 to form the second forming diaphragm plate 1C1.
  • An image is selectively formed on a predetermined opening AP2 of C2, and further, one of a plurality of partial collective exposure graphic areas PA in the selected opening AP2 is selected by beam deflection. It is to be transferred to a resist film on the semiconductor wafer 2.
  • the EB exposure apparatus 1 can expose a plurality of types of figures of about 5 ⁇ 5 m (converted on the semiconductor wafer 2) by beam deflection.
  • the second shaping plate is provided in a range where an exposure area can be selected by beam deflection (that is, in each opening AP2). It is possible to perform high-speed partial batch exposure of multiple figures (partial batch exposure figures) of 1C2. Therefore, by using the EB exposure apparatus 1 of the present embodiment, the exposure time can be significantly reduced. In addition, throughput can be improved.
  • the variable shaping exposure process the planar shape of the opening AP1 of the first shaping diaphragm 1C1 and the opening AP3 within the predetermined opening AP2 of the second shaping diaphragm 1C2. The rectangular pattern formed in the overlapping region is transferred to the resist film on the semiconductor wafer 2.
  • the EB irradiation position on the partial batch exposure pattern area PA and the opening AP3 in the rectangular openings AP1 and AP2 is selected by a transfer deflection system so that a figure beam and a variable rectangular beam are formed.
  • a transfer deflection system so that a figure beam and a variable rectangular beam are formed.
  • the variable shaped beam In the case of, the beam is deflected by variable rectangular deflection according to the exposure data of the EB exposure apparatus 1, and in the case of a figure beam, the figure selection deflection (deflector 1E1) and the return deflection (deflector) 1 E3) is linked to deflect the beam.
  • the shaped beam is reduced to, for example, about 125 to LZ100 by the reduction lenses 1D4 and 1D6, and projected onto the exposure surface of the resist film of the semiconductor wafer 2 by the objective deflection system.
  • the exposure position of the variable rectangular beam is specified by the sum of the main deflection, the sub deflection, and the sub sub deflection of the polarizer 1E4.
  • the structure is such that the relative position of the figure beam to the variable rectangle is added to the sub deflection.
  • one figure beam is defined in one sub-sub deflection area. Therefore, even when two types of figure beams are exposed in the vicinity, they are processed as different sub-sub deflection regions.
  • the first and second aligners 1F1, 1F2 are arranged for axis adjustment of the variable rectangle.
  • the axis correction when shifting from the variable rectangle to each figure beam is performed by finely adjusting the swingback deflection.
  • Rotating lenses 1D2 and 1D5 for correcting rotation of the first and second forming diaphragm plates 1C1 and 1C2 are arranged in the molded lenses 1D1 and 1D3 and the reduction lenses 1D4 and 1D6. Magnification correction can be performed without rotating the two-stage reduction lens with reverse excitation and adjusting the current intensity equally.
  • BA indicates the beam forming / deflecting direction
  • BB indicates the beam reducing / deflecting direction.
  • reference symbol SA denotes a partial batch shot by partial batch EB exposure
  • reference symbol SB denotes a variable shaping shot by variable shaping EB exposure.
  • FIGS. 22 and 23 show plan views of the second formed aperture plate 1C2 of the EB exposure apparatus 1.
  • the second formed aperture plate 1C2 is formed mainly of, for example, silicon (Si) formed in a square shape in a plane.
  • the opening AP3 for example, one opening AP3 for variable shaping exposure is arranged.
  • the opening AP3 for example, a pattern (for variable molding) having a rectangular planar shape is arranged.
  • a plurality of the partial batches for the partial batch exposure are provided around the central opening AP3.
  • the exposure figure area PA is arranged.
  • the thickness of the second formed aperture plate 1 C 2 is partially reduced, and a predetermined pattern is formed in the reduced area.
  • the movement of the exposure target area between the openings AP2 indicated by the movement direction MA is performed by mechanical movement of the second forming aperture plate 1C2.
  • the plane dimension of the opening AP2 for partial batch exposure is set to a dimension that allows pattern exposure by beam deflection of the EB exposure apparatus 1.
  • the plurality of partial batch exposure graphic areas PA in each opening AP2 are regularly arranged at predetermined intervals so as to be spread in the vertical and horizontal directions of FIG. ing.
  • the plane dimension of each partial exposure pattern area PA is a dimension that can be exposed by one-shot exposure, and is set, for example, to be about 5 ⁇ 5 m when converted on a semiconductor wafer.
  • the reduction ratio of the EB exposure apparatus 1 is 1 Z 25
  • the plane dimension of the partial batch exposure pattern area PA is about 125 ⁇ 125.
  • the common pattern pattern (pattern or pattern group of the predetermined layer of the subcell) is formed in the partial batch exposure pattern area PA.
  • the movement between adjacent partial collective exposure graphic areas P A can be controlled by the beam deflection B.
  • the first opening AP2 from the upper left of FIG. 22 is an area for transferring the active area of the semiconductor integrated circuit device, and the second opening on the right side thereof AP 2 is assigned to each layout layer of the semiconductor integrated circuit device, such as a region for forming a gate portion of the semiconductor integrated circuit device.
  • the first partial collective exposure graphic area PA from the upper left of FIG. 23 is the pattern of the active area shown in FIG.
  • the collective exposure pattern area PA patterns of the same layout layer of different cells (circuit cells and subcells) are formed, as in the pattern of the active area in FIG.
  • the exposure pattern is the same (for example, in FIGS. 7 (a) and 7 (b)).
  • the gate section GA, GB a pattern of a plurality of different subcells can be exposed using the pattern of one partial batch exposure pattern area PA.
  • FIG. 24 is a cross-sectional view of a principal part of the semiconductor wafer 2 during a manufacturing process of the semiconductor integrated circuit device according to the present embodiment.
  • the semiconductor substrate 2S constituting the semiconductor wafer 2 is made of, for example, a p-type Si single crystal, and has, for example, an n-well 3n and a p-well 3p on its main surface.
  • phosphorus or As is introduced into the n-well 3 n
  • boron is introduced into the p-well 3 p, for example.
  • a trench-type isolation portion (trench isolation) 4 is formed on the main surface of the semiconductor substrate 2S.
  • the isolation portion 4 is formed by burying an insulating film made of, for example, a silicon oxide film in a groove dug in the thickness direction of the semiconductor substrate 2S.
  • the separation section 4 may be formed of a field insulating film formed by a LOCOS (Local Oxidization of Silicon) method or the like.
  • pMl SQp and nM I SQn are formed, respectively.
  • a pair of semiconductor regions 6 for source and drain of p MISQ p are set to be p-type by introducing boron, for example, and a pair of semiconductor regions 7 for source and drain of nM I SQn are doped with, for example, phosphorus or arsenic. Is set to n-type.
  • the semiconductor regions 6 and 7 of nMI 3 ⁇ 311 and 1 ⁇ I SQp have an LDD (Lightly Doped Drain) structure.
  • the source / drain semiconductor region 6 of the pM ISQ p has a low-concentration region 6a and a high-concentration region 6b.
  • the semiconductor region 7 of nM I SQn has a low concentration region 7a and a high concentration region 7b.
  • the low concentration regions 6a and 7a have a relatively low impurity concentration and are provided on the channel side.
  • the high-concentration regions 6b and 7b have a relatively high impurity concentration and are formed at positions separated from the channel by a low-concentration region 6a and 7a in the horizontal direction with respect to the main surface of the semiconductor substrate 2S. ing. Further, on the upper surfaces of the semiconductor regions 6 and 7, for example, tungsten silicide or contact silicide is used.
  • nM I SQn and pM I SQp have semiconductor regions 9 p and 9 n for a punch-through stopper.
  • the semiconductor region 9p is formed, for example, by introducing boron, and is formed near the channel-side end of the semiconductor region 7 of nM I SQn.
  • the semiconductor region 9 n is formed by introducing, for example, phosphorus or arsenic, and is formed near the channel-side end of the semiconductor region 6 of pMISQp.
  • These semiconductor regions 9 n and 9 p have a function of suppressing or preventing the short channel effect of nM I SQn and pM I SQp, thereby suppressing or preventing the punch-through phenomenon occurring between the source and the drain.
  • the gate insulating film 10 of nM I 3 ⁇ 311 and 1 ⁇ 1 SQp is made of, for example, a silicon oxide film, and is formed by a thermal oxidation method or the like.
  • nitrogen may be segregated at the interface between the gate insulating film 10 and the semiconductor substrate 2S.
  • the gate electrodes 11 G of the nM I SQn and the pM I S Qp are each provided with a silicide layer 8 such as tantalum silicide or cobalt silicide on a single film of low-resistance polysilicon.
  • the gate electrode 11 G may be composed of, for example, a single film of a low-resistance polysilicon film, or may be made of tungsten or the like via a barrier layer such as titanium nitride / tungsten nitride on the low-resistance polysilicon film.
  • a so-called poly-metal structure provided with such a metal film may be used.
  • a sidewall 12 made of, for example, a silicon oxide film or a silicon nitride film is formed on the side surface of the gate electrode 11G.
  • an interlayer insulating film 13a is formed on the main surface of the semiconductor substrate 2S.
  • the interlayer insulating film 13a is made of, for example, a silicon oxide film, and its upper surface is subjected to a flattening process.
  • the chemically amplified resist film 14a is deposited by a spin coating method.
  • the resist film 14a is exposed to a pattern for forming a connection hole by batch exposure.
  • the connection hole pattern of the plurality of semiconductor chips of the semiconductor substrate 2S is combined with the plurality of partial portions in the opening AP2 of the hole (C0NT) layer of the second forming aperture plate 1C2 of the EB exposure apparatus 1.
  • Exposure is performed on the resist film 14a with a pattern in the exposure pattern formation area PA.
  • the partial batch exposure pattern area PA is selected by beam deflection, and exposure (drawing) is performed while transferring the hole pattern group in each partial batch exposure area PA in one shot.
  • the semiconductor wafer 2 is subjected to a development processing to form a resist pattern on the semiconductor substrate 2S as shown in FIG. Form 1 4 a 1.
  • the resist pattern 14a1 is formed so that, for example, a connection hole forming region having a substantially circular planar shape is exposed, and the other portions are covered.
  • the semiconductor substrate 2S is subjected to an etching treatment, so that, as shown in FIG. Drill multiple contact holes 15a.
  • the silicide layer 8 is exposed from the bottom of the contact hole 15a.
  • a conductor film made of, for example, tungsten or the like is polished by a CMP (Chemical Mechanical Polish) method or the like, thereby forming the contact hole 1 as shown in FIG.
  • the conductive film 16 is embedded in 5a.
  • the conductive film 16 is electrically connected to the semiconductor regions 6 and 7.
  • a conductor film 17 made of, for example, aluminum, aluminum-copper-silicon alloy or tungsten is deposited on the semiconductor substrate 2S by a sputtering method or the like, and a chemically amplified type
  • the above resist film 14b is applied by a spin coating method or the like.
  • the semiconductor wafer 2 is carried into the EB exposure apparatus 1 again, and the resist film 14b is exposed to the pattern for forming the lowermost wiring on the resist film 14b by the partial batch exposure process described above.
  • the pattern of the wiring layer of the lowermost wiring in the plurality of semiconductor chips of the semiconductor wafer 2 is The resist film 14b is exposed with the pattern of the plurality of partial exposure pattern forming areas PA in the opening AP2 for the lowermost wiring layer (M0) of the strip 1C2.
  • the partial batch exposure pattern area PA is selected by beam deflection, and the exposure (drawing) is performed while transferring the wiring pattern group in each partial batch exposure area PA with one shot.
  • the semiconductor wafer 2 is subjected to a development processing so that a resist is formed on the semiconductor substrate 2S as shown in FIG.
  • the pattern 1 4 b 1 is formed.
  • the resist pattern 14 b 1 covers, for example, a wiring formation region, and the other portions are exposed.
  • the semiconductor wafer 2 is subjected to an etching process, and the conductive film 17 exposed from the resist pattern 14b1 is removed by etching.
  • the lowermost wiring 17 M0 is formed on the interlayer insulating film 13 a.
  • the lowermost wiring 17 M0 is electrically connected to the conductor film 16.
  • the circuit cell described above is formed.
  • the pattern of the same layout layer of a plurality of semiconductor wafers for manufacturing the same type of semiconductor integrated circuit device can be continuously exposed.
  • the same layout layer pattern of a plurality of semiconductor wafers for manufacturing different types of semiconductor integrated circuit devices can be continuously exposed.
  • Such an exposure process is the same when exposing a pattern on a photomask instead of a semiconductor wafer.
  • the semiconductor chip 2C is made of a small piece such as a silicon single crystal having a plane square shape cut out from the semiconductor wafer 2, and its main surface is not particularly limited.
  • an encoder, a decoder, or a codec may be used.
  • a predetermined semiconductor integrated circuit such as described above is formed.
  • a logic circuit area 18, a memory circuit area 19, and an analog circuit area 20 are arranged on the main surface of the semiconductor chip 2C, and input / output is performed along the outer periphery of the semiconductor chip 2C so as to surround these circuit areas.
  • the circuit area 21 is arranged.
  • the present invention is for a circuit cell, it can be applied to the logic circuit area 18, the logic circuit area 19 a in the memory circuit area 19, and the logic circuit area 20 a in the analog circuit area 20.
  • the memory circuit area 19 includes, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), or a flash EEPROM.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • flash EEPROM flash EEPROM
  • An M Electrical Erasable Programmable Read Only Memory
  • an input circuit In the input / output circuit area 21, an input circuit, an output circuit, and an input / output bidirectional circuit are formed.
  • a plurality of bonding pads BP are arranged along the outer periphery.
  • the bonding pad BP is an electrode for drawing out the terminal of the semiconductor integrated circuit in the semiconductor chip 2C to the outside, and is electrically connected to the internal circuit via the input / output circuit area 21.
  • FIG. 32 and 33 are a plan view and a cross-sectional view of a main part of the logic circuit region, respectively.
  • FIG. 32 is an actual pattern layout plan view of the rising edge trigger flip-flop circuit on the semiconductor chip 2C.
  • the planar shape of the pattern is the same as that shown in FIG.
  • the active region 5 LP constitutes the source and drain of pMI SQp! ) Type semiconductor region 6 is formed.
  • an n-type semiconductor region 7 constituting the source / drain of the nM I SQn is formed in the active region 5LN.
  • 17MS of the lowermost wiring 17M0 is a portion where the above-mentioned surplus pattern portion is transferred.
  • FIG. 33 is a sectional view of a principal part of a semiconductor chip constituting the semiconductor integrated circuit device of FIGS. 31 and 32.
  • a cross-sectional view of pMI SQp is illustrated.
  • the buried n-well 22 formed in the semiconductor substrate 2S is formed to have an n-type by introducing, for example, phosphorus or arsenic, and is formed so as to surround the periphery of the n-well 3n.
  • Noise from other elements and circuits formed in It has a function to suppress or prevent intrusion (propagation) of noise.
  • the n + type semiconductor region 23 is set to the n + type by introducing, for example, phosphorus or arsenic at a higher concentration than the impurity concentration of the n + 3 n, and the p + potential to the n + 3 n It is an area to supply.
  • the silicide layer 8 is formed on the upper surface of the n + type semiconductor region 23, the silicide layer 8 is formed.
  • Second to fourth layer wirings 17M1 to 17M3 are formed above the lowermost wiring 17M0.
  • the second to fourth layer wirings 17 M 1 to 17 M 3 are made of a conductor such as aluminum or aluminum-copper-silicon alloy, for example, on a single film of titanium or titanium nitride or a laminated film thereof. A single film of, for example, titanium or titanium nitride or a laminated film thereof is formed via a film. Between these wiring layers, interlayer insulating films 13b to 13d made of, for example, silicon oxide are formed. The wiring layers are electrically connected by through holes 15b to 15d.
  • the insides of the circuit cells are electrically connected by the lowermost layer wiring 17M0, and the different circuit cells are electrically connected by the second layer wirings 17M1 to 17M3.
  • the circuit cells are configured by the above-described combinations and the like while securing the degree of freedom of the wiring between the circuit cells. Except for this, the description is omitted because it is the same as FIG.
  • the present invention is not limited to this, and various applications are possible.
  • the present invention can also be applied to a method for manufacturing a semiconductor integrated circuit device having the above or a method for manufacturing a semiconductor integrated circuit device in which a bipolar transistor and an MISFET are provided on the same semiconductor substrate.
  • the present invention is not limited to this.
  • the present invention can be applied to a semiconductor integrated circuit device having a logic circuit such as a microprocessor.
  • the number of partial batch exposure patterns (subcells) required for one partial batch exposure mask is greatly increased as compared with a case where circuit cells are simply disassembled to form subcells. Can be reduced.
  • the subcell can be commonly used for a plurality of circuit cells.
  • the semiconductor integrated circuit device and the method of manufacturing the semiconductor integrated circuit device according to the present invention are applicable to, for example, an encoder, a decoder, a codec, a microprocessor, a logic LSI, or a semiconductor integrated circuit device having a memory circuit and a logic circuit. It is an effective technology to apply.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

Pour réduire le temps de fabrication d'un dispositif à circuit intégré à semi-conducteurs, chaque cellule de circuit est réalisée tout en haut d'une pluralité de sous-cellules (SCC, SCG, SCH) utilisées couramment par une pluralité de cellules de circuit et le motif de la cellule de circuit est transféré par exposition de chaque motif de sous-cellules (SCC, SGC, SCH) au moyen de l'exposition partielle par lot. Une sous-cellule peut être utilisée pour l'exposition partielle par lot d'une pluralité de cellules de circuit. Comparativement à une structure dans laquelle les sous-cellules sont formées simplement par décomposition d'une cellule de circuit, le nombre de motifs pour l'exposition partielle par lot (sous-cellules) nécessaire pour un masque d'exposition partielle par lot peut être réduit significativement.
PCT/JP2000/008466 1999-11-30 2000-11-30 Dispositif a circuit integre a semi-conducteurs et procede de fabrication de ce dernier WO2001041198A1 (fr)

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JP34035999 1999-11-30
JP11/340359 1999-11-30

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007128932A (ja) * 2005-11-01 2007-05-24 Nuflare Technology Inc 荷電粒子線描画データの作成方法及び荷電粒子線描画データの変換方法
JP2007128933A (ja) * 2005-11-01 2007-05-24 Nuflare Technology Inc 荷電粒子線描画データの作成方法及び荷電粒子線描画データの変換方法
JP2007281488A (ja) * 2000-06-13 2007-10-25 Toshiba Corp 回路パターンの設計方法及び回路パターンの設計システム

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513313A (ja) * 1991-07-05 1993-01-22 Fujitsu Ltd 露光装置
JPH06267834A (ja) * 1993-03-15 1994-09-22 Toshiba Corp 荷電ビーム描画方法
JPH1174482A (ja) * 1997-06-27 1999-03-16 Nippon Steel Corp 半導体装置及びその製造方法
JPH11121636A (ja) * 1997-10-16 1999-04-30 Toshiba Corp 読み出し専用記憶装置
JPH11163286A (ja) * 1997-11-21 1999-06-18 Nec Corp 半導体記憶装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513313A (ja) * 1991-07-05 1993-01-22 Fujitsu Ltd 露光装置
JPH06267834A (ja) * 1993-03-15 1994-09-22 Toshiba Corp 荷電ビーム描画方法
JPH1174482A (ja) * 1997-06-27 1999-03-16 Nippon Steel Corp 半導体装置及びその製造方法
JPH11121636A (ja) * 1997-10-16 1999-04-30 Toshiba Corp 読み出し専用記憶装置
JPH11163286A (ja) * 1997-11-21 1999-06-18 Nec Corp 半導体記憶装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007281488A (ja) * 2000-06-13 2007-10-25 Toshiba Corp 回路パターンの設計方法及び回路パターンの設計システム
JP2007128932A (ja) * 2005-11-01 2007-05-24 Nuflare Technology Inc 荷電粒子線描画データの作成方法及び荷電粒子線描画データの変換方法
JP2007128933A (ja) * 2005-11-01 2007-05-24 Nuflare Technology Inc 荷電粒子線描画データの作成方法及び荷電粒子線描画データの変換方法

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