WO2001039275A1 - Transistor mos et procede de fabrication - Google Patents

Transistor mos et procede de fabrication Download PDF

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Publication number
WO2001039275A1
WO2001039275A1 PCT/DE2000/004215 DE0004215W WO0139275A1 WO 2001039275 A1 WO2001039275 A1 WO 2001039275A1 DE 0004215 W DE0004215 W DE 0004215W WO 0139275 A1 WO0139275 A1 WO 0139275A1
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WO
WIPO (PCT)
Prior art keywords
depth
doped region
substrate
source
region
Prior art date
Application number
PCT/DE2000/004215
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German (de)
English (en)
Inventor
Erhard Landgraf
Franz Hofmann
Original Assignee
Infineon Technologies Ag
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Publication date
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Publication of WO2001039275A1 publication Critical patent/WO2001039275A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Definitions

  • MOS transistor MOS transistor and method for its production.
  • the invention relates to a MOS transistor and a method for its production.
  • Such a MOS transistor is described, for example, in German patent application 198 07 213.9.
  • a trench is arranged in a substrate and has a widening in the region of a surface of the substrate.
  • An insulating structure is arranged in the expansion. Highly doped regions of two source / drain regions of the MOS transistor adjoin the expansion. Among the highly doped areas are low-doped areas of the two source
  • the recess is provided with a gate dielectric.
  • a cylindrical gate electrode is arranged in the recess.
  • a channel region of the MOS transistor is consequently U-shaped.
  • an insulation graph is first created in the substrate with the aid of a first mask and is filled with insulating material. Then, using a second mask, a further trench is created, which is arranged within the isolation trench and extends deeper than the isolation trench. Remaining parts of the insulating material in the isolation trench form the insulating structures. The isolation grave forms, together with the further trench, the depression which has the widening in the area of the isolation trench.
  • the MOS transistor is suitable as a so-called embedded MOS transistor, which is integrated in a circuit arrangement with transistors of another technology.
  • the MOS transistor has a high
  • the second mask of the first Mas ⁇ ke is the insulating structure in the region of a source / dram region configured differently than in the region of the other source / dram Geb ⁇ ets, so that carriers m the source / dram region on average have a greater distance to the channel area than charge carriers in the other source / dram area.
  • Such a MOS transistor is asymmetrical in terms of the locations of the source / dram regions with respect to the gate electrode.
  • the invention is based on the object of specifying a MOS transistor which, with a high voltage stability and a small space requirement at the same time, can be nernered so that an asymmetry with regard to the positions of source / dram areas with respect to a gate electrode of the MOS transistor is excluded.
  • the object is achieved by a MOS transistor with a first source / dram region and a second source / drain region, which are arranged in a substrate, adjoin a horizontal surface of the substrate and extend to a first depth. Between the first source / dram device and the second source / dram device, a recess is arranged in the substrate which adjoins the first source / dram device and the second source / dram device and is deeper than that first depth is enough.
  • the depression is delimited laterally by vertical surfaces of the substrate, which run essentially perpendicular to the horizontal surface of the substrate and extend from the horizontal surface of the substrate to a bottom of the recess.
  • a gate electrode of the transistor is arranged in the depression and extends from the bottom of the depression to substantially the first depth.
  • the recess is provided with a gate dielectric such that the gate electrode is separated from the substrate.
  • a contact is arranged on the gate electrode. Between the contact and the first source / dram area and between the contact and the second source / dram device is arranged at least one insulating structure which is arranged in the depression, extends from the gate electrode to at least the horizontal surface of the substrate and is thicker than the gate dielectric.
  • the insulating structure Since the insulating structure is thicker than the gate dielectric, it increases the dielectric strength of the MOS transistor.
  • the source / dram areas are spaced apart from the contact by the insulating structure.
  • the insulating structure lowers a capacitance that is formed by the contact and the source / dram regions.
  • the depression Since the vertical surfaces of the substrate, which extend from the bottom of the depression to the horizontal surface of the substrate / laterally delimit the depression, the depression has no widening, so that the MOS transistor can have a particularly small space requirement.
  • the recess has no widening, which is configured differently in the area of the first source / dram area than in the area of the second source / dram area.
  • the transistor is consequently symmetrical with respect to the positions of the source / dram regions with respect to the gate electrode.
  • the source / dram areas are preferably configured identically.
  • the channel area is U-shaped because the first depth, up to the source / dram areas, is above the bottom of the
  • the channel length of the MOS transistor is particularly large in comparison to a planar MOS transistor, with the same space requirement. Due to the large channel length, the MOS transistor can have a particularly high dielectric strength. In the following, a method for producing such a MOS transistor is described, which also accomplishes the task.
  • a depression is created in a suostrate such that the depression is laterally delimited by vertical surfaces of the substrate which are substantially perpendicular to a horizontal surface of the substrate and extend from the horizontal surface of the substrate to a bottom of the depression.
  • a first source / dram region and a second source / dram region are produced in the substrate in such a way that they adjoin the horizontal surface of the substrate and the depression and extend to a first depth that is more honorable than the floor the depression.
  • the bottom of the depression and the vertical surfaces of the substrate are provided with a gate dielectric.
  • a gate electrode is generated in the depression, which extends from the bottom of the depression to the first depth.
  • a contact is created on the gate electrode.
  • At least one insulating structure which is arranged in the recess, extends from the gate electrode to at least the horizontal surface of the substrate between the contact and the first source / dram device and between the contact and the second source / dram device extends and is thicker than the gate dielectric.
  • the contact can be made before or after the insulating structure is created.
  • the depression can be produced, for example, by anisotropic etching of the substrate. Since the indentation has no widening, the indentation can be produced in a single etching step, so that the MOS transistor can be produced with little outlay on the process.
  • the insulating structure is created within the depression, which is delimited by the vertical surfaces, so that the shape of the isolating structure does not affect the shape of the source / dram regions.
  • the deepening is at Every source / dram package is configured identically, since the vertical surfaces extend from the top to the bottom of the recess.
  • the source / dram areas can be generated in a self-aligned manner adjacent to the recess.
  • a doped layer is generated by implantation or by msitu doped epitaxy.
  • the doped layer is structured by producing at least the depression, so that the source / dram regions are formed from the doped layer.
  • the depression is first produced and then an implantation is carried out, so that the source / dram regions are produced in a self-aligned manner adjacent to the depression.
  • the gate electrode can be self-adjusted in the recess.
  • conductive material is deposited and etched back to the first depth.
  • the first source / dram device consists of a first highly doped region un ⁇ consists of a first lightly doped region
  • the second source / drain region consists of a second highly doped region and a second lightly doped region.
  • the first highly doped region and the second highly doped region each extend from a second depth that lies above the first depth to the horizontal sheet of the substrate.
  • the first low-doped region and the second low-doped region each extend from the first depth to the second depth.
  • the first highly doped area and the first low doped area border aneman ⁇ er r- O on.
  • the second highly doped region and the second low doped region are adjacent to one another.
  • the highly doped geoietes can, for example, be generated by an implantation with a first implantation energy.
  • the low-eared areas can be generated, for example, by implantation with a second implantation energy that is greater than the first implantation energy.
  • the highly doped regions and the low-doped regions can alternatively also be generated by msitu doped epitaxy.
  • the first still doped region is separated from the rest of the substrate by the first low-doped region, and the second highly doped region is separated by the second low-doped region is separated from the rest of the substrate.
  • the first lightly doped region surrounds the first highly doped region and the second lightly doped region surrounds the second highly doped region.
  • the first lightly doped region has a vertical part which adjoins and deviates from one of the vertical surfaces of the substrate extends from the first depth to the second depth.
  • the first lightly doped region has a horizontal part that laterally adjoins the vertical part of the first lightly doped region and extends from a third depth that lies between the first depth and the second depth to the second depth.
  • the second lightly doped region also has a vertical part which adjoins another of the vertical surfaces of the substrate and extends from the first depth to the second depth.
  • the second low doped area has a horizontal part, which laterally adjoins the vertical part of the second lightly doped region and extends from the third depth to the second depth.
  • an oblique implantation is carried out after producing the gate electrode but before producing the insulating structure and the contact such that parts of the vertical surfaces of the Be implanted substrate.
  • the source / dram areas are generated such that they hit the source / dram areas and the gate electrode at the same, namely at the first depth.
  • the oblique implantation adapts the source / drain regions to the depth of the gate electrode.
  • the horizontal parts of the low-doped regions are produced with a depth less than the first depth, so that they are not deeper than the gate electrode and the source / drain regions can be adapted to the depth of the gate electrode by the oblique implantation.
  • the contact contains metal.
  • the contact oestent for example, from a metal, such as AI, or from a metal silicide, e.g. WSi.
  • the contact can also consist of doped polysilicon.
  • the gate electrode is preferably made of doped polysilicon.
  • the contact can be generated, for example, as follows:
  • an insulating layer is produced which fills the depression.
  • a contact hole m in the insulating layer is opened by masked etching and extends to the gate electrode. In the contact loc a contact is created. Remaining parts of the insulating layer of the m Vertie ⁇ Fung can form the insulating structure. In this case, the opening m of the mask that is used in masked etching of the contact is smaller than the depression.
  • the insulating structure In order to avoid a short circuit between the contact and the source / drain sensors by using the mask with respect to the recess, it is advantageous to produce the insulating structure as follows: after the gate electrode has been produced, insulating material is deposited and jerked, so that the insulating structure in the form of a spacer is produced. The contact is created according to the insulating structure. Naer. Generation of the insulating structure, but before the contact is made, the insulating layer can be deposited. The contact hole to the gate electrode can be opened by masked etching selective to the insulating structure.
  • the opening of the mask used can be misaligned with respect to the recess and the insulating structure can overlap without a short circuit between the contact and the source / dram regions.
  • the contact is produced immediately after the insulating structure has been created in the depression.
  • the spacer-shaped insulating structure is just as thick in the area of the first source / dram device as in the area of the second source / dram device. A distance between the contact and the first source / dram device is consequently equal to a distance between the contact and the second source / dram device.
  • the MOS transistor can have a high dielectric strength, it is suitable as a high-voltage transistor.
  • the MOS transistor is suitable as an embedded transistor, which is arranged, for example, in the periphery of a memory cell arrangement, such as an EEPROM.
  • the insulating layer can, for example, be an intermediate oxide which is deposited on the EEPROM.
  • the gate dielectric can line the entire recess, so that both the gate electrode and the insulating structure adjoin the gate dielectric.
  • only the gate electrode is adjacent to the gate dielectric.
  • the gate dielectric is arranged only at the bottom of the depression and on parts of the vertical surfaces of the substrate which are arranged between the bottom of the depression and the first depth.
  • FIG. 1 shows a cross section through a substrate after a first doped layer and a second doped layer have been produced.
  • FIG. 2 shows the cross-section from FIG. 1, including a mask, a depression, a first highly doped region of a first source / dram device, a non-central part of a first low-doped geoiet of the first source / dram device a second highly doped area of a second source / dram area and a horizontal part of a second low doped area of the second source / dram area.
  • FIG. 3 shows the cross-section from FIG. 2, after a gate element, a gate electrode, a vertical part of the first lightly doped region and a vertical part of the second lightly doped region were generated.
  • FIGURE -. shows the Querscnmtt from Figure 3, after a ⁇ iso-regulating structure, an insulating layer and a Konta ⁇ t were produced.
  • a substrate 1 made of silicon is provided as the starting material, which in the area of a horizontal surface H has a dopant concentration of approximately 10! cm -3 is p-doped.
  • An implantation with n-doping ions at an implantation energy of approx. 50 keV produces a approx. 200 nm deep first rotated area S1, which adjoins the horizontal plane H of the substrate 1 (see FIG. 1).
  • a further implantation with n-doping ions at an implantation energy of approx. 200 keV produces an approx. 300 nm thick second doped layer S2 in the substrate 1, which is adjacent to the first ⁇ oped layer S1 (see FIG. 1).
  • S1O2 m is deposited with a thickness of approximately 400 nm and structured by a photolithographic process.
  • the substrate 1 is anisotropically etched to a depth of approximately 800 nm using the mask M (see FIG. 2).
  • a horizontal cross section of the depression V is rectangular with a first side length of approximately 1 ⁇ m and a second side length of approximately 500 nm.
  • the first doped layer S1 and the second doped layer S2 are structured by the recess V.
  • a first highly doped region H1 of a first source / drain region S / Dl and a second highly doped region H2 of a second source / dram region S / D2 of a MOS transistor are formed from the first doped layer S1, between which the recess V is arranged and which adjoin the recess V (see Figure 2).
  • a horizontal part of a first lightly doped region N1 of the first source / dram unit S / D1 and a horizontal part of a second lightly doped region N2 of the second source / dram unit S / D2 are generated, which are among the highly doped ones Areas Hl, H2 are arranged. Furthermore, a part of a vertical part of the first lightly doped region N1 and a part of a vertical part of the second lightly doped region N2 are produced from the second doped layer S2, which laterally adjoin and to the horizontal parts of the lightly doped regions N1, N2 Adjacent depression V.
  • msitu-doped polysilicon is deposited to a thickness of approximately 200 nm and etched back.
  • the gate electrode GA extends from a bottom of the depression V to a first depth T1, which is approximately 600 nm below the horizontal surface H of the substrate 1 (see FIG. 3).
  • the low-doped regions N1, N2 each extend from the first depth T1 to a second depth T2, which is approximately 200 nm below the horizontal surface H of the substrate 1.
  • the horizontal parts of the low-doped regions N1, N2 each extend from a third depth T3, which is approximately 500 nm below the horizontal plane H of the substrate 1 lies to the second depth T2.
  • the vertical parts of the low-doped regions Nl, N2 each range from which it ⁇ most Tl depth to the second depth T2.
  • the vertical parts of the low-doped regions N1, N2 each have an aomeasure perpendicular to the vertical surface of the substrate 1 to which they adjoin, which is approximately 100 nm.
  • insulating structures I silicon oxide is deposited to a thickness of approximately 50 nm and etched back until mask M is exposed (see FIG. 4).
  • the insulating structures I range from the second depth T1 to approximately 350 nm above the horizontal surface H of the substrate 1.
  • the insulating structure I is arranged on the gate electrode GA and adjoins the gate dielectric GD.
  • Masked etching creates an approximately 800 nm deep isolation trench (not shown) that surrounds the MOS transistor.
  • S1O2 is deposited in a thickness of approximately 1000 nm. This fills the isolation trench with S1O2.
  • Masked etching opens a contact hole m in the insulating layer IS, which extends as far as the gate electrode GA.
  • S1O2 is selectively etched to silicon oxide so that the insulating structure I is not attacked.
  • Al is deposited in a thickness of approximately 400 nm and removed until the insulating one
  • the distance of the contact K from the source / Dra regions S / Dl, S / D2 is approximately 70 nm due to the insulating structure I.
  • the second source / Dra area S / D2 is arranged and adjoins the depression V, is suitable as a channel area.
  • the method produces a MOS transistor which, because of the depression V, has a large channel length with a small space requirement. Because of the subdivision of the source / dram regions S / Dl, S / D2, the highly doped regions Hl, H2 and the low-doped regions Nl, N2, the dielectric strength of the MOS transistor is particularly high. Because of the insulating structure I, the dielectric strength between the contact K and the source / dram areas S / Dl, S / D2 is high. The MOS transistor is symmetrical with respect to the positions of the source / dram areas S / Dl, S / D2 with respect to the gate electrode GA.
  • the source / dram areas S / Dl, S / D2 can be p-doped instead of n-doped.
  • the substrate 1 is n-doped.
  • the insulating structures I can also be produced in such a way that, instead of separating silicon t ⁇ d, the insulating layer IS is immediately molded off and the contact K is generated therein. Remaining parts of the isolating layer IS within the depression V in this case form the insulating structure I.

Abstract

Selon l'invention, une cavité (V) est disposée entre une première zone source/drain (S/D1) et une deuxième zone source/drain (S/D2) ayant toutes deux une première profondeur (T1), la cavité étant plus profonde que la profondeur (T1). La cavité (V) comporte un diélectrique de porte (GD). Une électrode de porte (GA) est disposée dans la cavité (V) et s'étend du fond de la cavité (V) jusqu'à la première profondeur (T1). Une structure isolante (I) est disposée sur l'électrode de porte (GA), cette structure permettant d'espacer des zones source/drain (S/D1, S/D2) un contact (K) vers l'électrode de porte (GA) disposé dans la cavité (V). Les zones source/drain (S/D1, S/D2) peuvent être réparties en zones à dopage important (H1, H2) et en zones à dopage faible (N1, N2). Pour la production auto-ajustée des zones source/drain (S/D1, S/D2) par rapport à l'électrode de porte (GA), certaines parties au moins des zones source/drain (S/D1, S/D2) peuvent être produites par implantation oblique après production de l'électrode de porte (GA) et avant production de la structure isolante (I) et du contact (K).
PCT/DE2000/004215 1999-11-29 2000-11-27 Transistor mos et procede de fabrication WO2001039275A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1999157303 DE19957303B4 (de) 1999-11-29 1999-11-29 MOS-Transistor und Verfahren zu dessen Herstellung
DE19957303.4 1999-11-29

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Publication number Priority date Publication date Assignee Title
KR20110052226A (ko) * 2009-11-12 2011-05-18 삼성전자주식회사 Ｒｃｔ 소자 및 그 ｒｃｔ 소자를 포함하는 디스플레이 장치
CN112601966B (zh) 2019-08-01 2022-09-13 深圳市汇顶科技股份有限公司 电容检测电路、触摸检测装置和电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2103013A (en) * 1981-07-31 1983-02-09 Secr Defence Method for producing a MISFET and a MISFET produced thereby
JPS6269562A (ja) * 1985-09-20 1987-03-30 Mitsubishi Electric Corp 電界効果トランジスタ装置およびその製造方法
JPH0385766A (ja) * 1989-08-30 1991-04-10 Matsushita Electron Corp 半導体装置
JPH03241870A (ja) * 1990-02-20 1991-10-29 Oki Electric Ind Co Ltd 半導体装置
US5142640A (en) * 1988-06-02 1992-08-25 Seiko Epson Corporation Trench gate metal oxide semiconductor field effect transistor
WO1999043029A1 (fr) * 1998-02-20 1999-08-26 Infineon Technologies Ag Transistor mos a grille et tranchee, son utilisation dans des systemes de memoires mortes programmables effaçables electriquement, et son procede de production

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2103013A (en) * 1981-07-31 1983-02-09 Secr Defence Method for producing a MISFET and a MISFET produced thereby
JPS6269562A (ja) * 1985-09-20 1987-03-30 Mitsubishi Electric Corp 電界効果トランジスタ装置およびその製造方法
US5142640A (en) * 1988-06-02 1992-08-25 Seiko Epson Corporation Trench gate metal oxide semiconductor field effect transistor
JPH0385766A (ja) * 1989-08-30 1991-04-10 Matsushita Electron Corp 半導体装置
JPH03241870A (ja) * 1990-02-20 1991-10-29 Oki Electric Ind Co Ltd 半導体装置
WO1999043029A1 (fr) * 1998-02-20 1999-08-26 Infineon Technologies Ag Transistor mos a grille et tranchee, son utilisation dans des systemes de memoires mortes programmables effaçables electriquement, et son procede de production

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 011, no. 265 (E - 535) 27 August 1987 (1987-08-27) *
PATENT ABSTRACTS OF JAPAN vol. 015, no. 261 (E - 1085) 3 July 1991 (1991-07-03) *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 027 (E - 1158) 23 January 1992 (1992-01-23) *

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TW483169B (en) 2002-04-11
DE19957303A1 (de) 2001-06-07

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