TW483169B - MOS-transistor and its production method - Google Patents

MOS-transistor and its production method Download PDF

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Publication number
TW483169B
TW483169B TW89124919A TW89124919A TW483169B TW 483169 B TW483169 B TW 483169B TW 89124919 A TW89124919 A TW 89124919A TW 89124919 A TW89124919 A TW 89124919A TW 483169 B TW483169 B TW 483169B
Authority
TW
Taiwan
Prior art keywords
depth
region
source
substrate
notch
Prior art date
Application number
TW89124919A
Other languages
Chinese (zh)
Inventor
Franz Hofmann
Erhard Landgraf
Original Assignee
Infineon Technologies Ag
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Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Application granted granted Critical
Publication of TW483169B publication Critical patent/TW483169B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Between the 1st source-/drain-region (S/D1) and the 2nd source-/drain-region (S/D2), which arrives a 1st depth (T1), is arranged a recess (V), which is deeper than the 1st depth (T1). The recess (V) is provided with a gate-dielectric (GD). A gate-electrode (GA) is arranged in the recess (V) and extends from the bottom of the recess (V) to the 1st depth (T1). On the gate- electrode (GA) is arranged an isolating structure (1), due to which a contact-area (K) t the gate-electrode (GA) in the recess (V) is located in a distance from the source-/drain-regions (S/D1, S/D2). The source-/drain-regions (S/D1, S/D2) can be divided into high doped regions (H1, H2) and into low doped regions (N1, N2). In order to generate self-adjusted the source-/drain-regions (S/D1, S/D2) relative to the gate-electrode (GA), at least some parts of the source-/drain-regions (S/D1, S/D2) can be generated by an inclined implantation after the generation of the gate-electrode (GA) and before the generation of the isolating structure (1) and the contact-area (K).

Description

483169 A7 B7 五、發明說明（1 ) 本發明涉及MOS電晶體及其製造方法。 此種 MOS電晶體例如已描述在德國專利文件 19807213.9中。在基板中配置一個溝渠，此溝渠在基板 表面之區域中具有一個擴大區。在擴大區中配置一種隔 離結構。此Μ 0 S電晶體之二個源極/汲極區之高摻雜 區鄰接於該擴大區。高摻雜區下方配置此二個源極/汲 極區之低摻雜區，其到達一種深度，此深度是介於凹口 底部和凹口之擴大區之間。此凹口中設有鬧極介電質。 此凹口中配置一種圓柱形之閘極電極。MOS電晶體之通 道區因此是U形的。 經濟部智慧財產局員工消費合作社印製 爲了產生MOS電晶體’首先藉助於第一'遮罩而在基 板中產生一種隔離溝渠且以絕緣材料塡入。然後藉助於 第二遮罩而產生另一溝渠，其配置在該隔離溝渠內部且 較該隔離溝渠還深。該隔離溝渠中絕緣材料之其餘部份 形成各隔離結構。該隔離溝渠與另一溝渠一起形成該凹 口，此凹口在隔離溝渠之區域中具有該擴大區。此M〇S 電晶體適合以所謂埋入式MOS電晶體構成，其積體化 於一種以其它技術構成之電晶體所形成之電路配置中。 此種M0S電晶體具有一種很高之電壓強度而適合用作 高電壓電晶體。 在第二遮罩相對於第一遮罩而對準時，此隔離結構在 一個源極/汲極區中之構造是與另一源極/汲極區中者 不同的，使電荷載體在一個源極/汲極區中至通道區之 平均距離較在另一個源極/汲極區中至通道區者還大。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 483169 A7 B7 五、發明說明（2 ) 此種MOS電晶體就源極/汲極區相對於閘極電極之位 置而言是不對稱的。 本發明之目的是提供一種MOS電晶體，其可以較高 之電壓強度及較小之空間需求而製成，此MQS 電晶體 之源極/汲極區相對於閘極電極之位置上之不對稱性可 被排除。 經濟部智慧財產局員工消費合作社印製 此目的是藉由一種具有第一源極/汲極區和第二源極 /汲極區之MOS電晶體來達成，其配置在基板中，鄰 接於基板之水平表面且到達第一深度。在第一源極/汲 極區和第二源極/汲極區之間於基板中配置一個凹口， 此凹口鄰接於第一和第二源極/汲極區且較第一深度還 深。此凹口在側面是以此基板之垂直面爲界，這些垂直 面垂直於基板之水平面而延伸且由基板之水平面延伸至 凹口之底部。此電晶體之閘極電極配置於凹口中且由凹 口之底部延伸至第一深度。凹口須設有閘極介電質，使 閘極電極與基板相隔開。在閘極電極上配置一個接觸 區。在接觸區和第一源極/汲極區之間以及接觸區和第 二源極/汲極區之間配置至少一個隔離結構，此隔離結 構配置在凹口中，由閘極電極延伸到至少此基板之水平 表面且較閘極介電質還厚。 由於此隔離結構較閘極介電質還厚，其可使MOS電 晶體之電壓強度增大。源極/汲極區藉由該隔離結構而 與接觸區相隔開。此隔離結構使此種由接觸區和源極/ 汲極區所形成之電容變小。 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 483169 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 由於基板之垂直各面（其由凹口底部到達基板之水平 表面）在側面圍繞此凹口，此凹口因此不具有上述之擴 大區，使此MOS電晶體可具有特別小之空間需求。 此凹口特別是不具有該擴大區，此擴大區在第一源極 /汲極區中之構造不同於第二源極/汲極區中者。此電 晶體就源極/汲極區相對於閘極電極之位置而言因此是 對稱的。各源極/汲極區之構造最好相同。 二個源極/汲極區之間配置此MOS電晶體之通道 區，其鄰接於該凹口。通道區是U形的，這是因爲源極 /汲極區所到達之第一深度是在該凹口底部上方。由於 此通道區是U形的，則此MOS電晶體之通道長度在和 平面式MOS電晶體比較之情況下在空間需求相同時是 特別大的。由於此種較大之通道長度，則此Μ 0 S電晶 體可具有一種特別大之電壓強度。 以下將描述此種MOS電晶體之產生方法，其同樣是 本發明之目的。 在基板中須產生一個凹口，使此凹口側面以此基板之 是垂直於基板之水平表面而延 伸至凹口之底部。在基板中須 產生第一源極/汲極區和第二源極/汲極區，使它們鄰 垂直面爲界，這些垂直面 伸且由基板之水平表面延 接於基板之水平表面且鄰接於凹口而到達第一深度，第 一深度較凹口之底部還高 都設有閘極介電質。在凹 。凹口之底部和基板之垂直面 口中產生閘極電極，其由凹口 之底部延伸至弟一'ί朱度。在聞極電極上產生一種接觸 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 背 © 之 注 意 事 項 再 重麵 頁i 吕丁 線 經濟部智慧財產局員工消費合作社印製 483169 A7 B7___ 五、發明說明（4 ) 區。在接觸區和第一源極/汲極區之間以及接觸區和第 二源極/汲極區之間產生至少一個隔離結構，其配置在 凹口中，由閘極電極延伸到至少此基板之水平表面且較 閘極介電質還厚。 此接觸區在該隔離結構產生之前或之後產生。 該凹口例如藉由基板之非等向性蝕刻而產生。由於此 凹口不具備該擴大區，則此凹口可以唯一之蝕刻步驟而 產生，使此MOS電晶體能以較小之製程費用製成。 該隔離結構產生於凹口內部，此凹口以垂直面爲邊 界，使隔離結構之形式不會影響源極/汲極區之形式。 此凹口在每一源極/汲極區中之構造是相同的，這是因 爲各垂直面由凹口之上端延伸至底部。 各源極/汲極區以自我對準之方式鄰接於此凹口而產 生。藉由植入或藉由同次（in suit)摻雜之嘉晶（Epitaxy)而 產生一種摻雜層。藉由產生至少一個凹口而使此摻雜層 被結構化，以便由此摻雜層形成源極/汲極區。另一方 式是首先產生此凹口，然後進行一種植入，使源極/汲 極區以自我對準之方式鄰接於此凹口而產生。 閘極電極以自我對準之方式產生於凹口中。因此須沈 積一種導電材料且回（back)蝕刻至第一深度。 爲了簡化製程，則有利之方式是首先產生該隔離結 構，然後產生該接觸區^ 爲了使第一源極/汲極區和第二源極/汲極區之間以 及各源極/汲極區和閘極電極之間的電壓強度提高，具 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再本頁) 訂： 經濟部智慧財產局員工消費合作社印製 483169 Α7 Β7 五、發明說明（5 ) 則有利之方式是：第一源極/汲極區由第一高摻雜區及 第一低摻雜區所構成，且第二源極/汲極區由第二高摻 雜區及第二低摻雜區所構成。第一高摻雜區和第二高摻 雜區分別由第二深（其位於第一深度上方）延伸至基板 之水平表面。第一低摻雜區和第二低摻雜區分別由第一 深度延伸至第二深度。第一高摻雜區和第一低摻雜區互 相鄰接。第二高摻雜區和第二低摻雜區相鄰。 各高摻雜區例如可利用此種具有第一植入能量之植入 法來產生。各低摻雜區例如可利用此種具有第二植入能 量（其大於第一植入能量）之植入法來產生。各高摻雜 區及低摻雜區亦可以另一方式而由同次摻雜之磊晶來產 生。 爲了使源極/汲極區和基板之間的電壓強度增大，則育 利之方式是：第一高摻雜區藉由第一低摻雜區而與其餘 之基板相隔開，第二高摻雜區藉由第二低摻雜區而與其 餘之基板相隔開。在基板內部中，第一低摻雜區圍繞第 一*局ί爹雜區且弟—*低慘雑區圍繞第二局慘雜區。 閘極電極和源極/汲極區相對於第一深度以自我對準 之方式而產生’右弟一低搶雑區具有一*種垂直部份（其 鄰接於基板之各垂直面之一且由第一深度延伸至第二深 度），則這樣是有利的。第一低摻雜區具有一種水平部 份，其在側面鄰接於第一低摻雜區之垂直部份且由第三 深度（其介於第一深度和第二深度之間）延伸至第二深 度。第二低摻雜區具有一種垂直部份，其鄰接於基板之 -7- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再本頁) 訂- -1線· 483169 A7 - B7 五、發明說明（6 ) 另一垂直面且由第一深度延伸至第二深度。第二低摻雜 區具有一種水平部份，其在側面上鄰接於第二低摻雜區 之垂直部份且由第三深度延伸至第二深度。爲了產生第 一低摻雜區之垂直部份及第二低摻雜區之垂直部份，貝[J 在閘極電極產生之後（但在該隔離結構及接觸區產生之 則）須進行一種傾斜式植入，使基板之各垂直面之未被 閘極電極所覆蓋之這些部份受到此種植入作用。 以上述方式產生源極/汲極區，使源極/汲極區和閘 極電極在同一深度（即，第一深度）相遇。源極/汲極 區藉由傾斜式植入以自我對準之方式依據閘極電極之深 度來調整。低摻雜區之水平部份產生於較第一深度還小 之深度處，其位置因此不會較閘極電極還深且源極/汲 極區藉由傾斜式植入而可依據閘極電極之深度來調整。 爲了提高導電性，則該接觸區含有金屬時是有利的。 此接觸區例如由一種金屬（例如，鋁）所構成或由金屬 矽化物（WSi )所構成。此接觸區亦可由摻雜之多晶矽所 構成。 閘極電極最好由摻雜之多晶矽所構成。 此接觸區例如以下述方式產生： 在產生閘極電極之後產生一種隔離層（其塡入凹口 中）。藉由遮罩式蝕刻而在此隔離層中開啓一個接觸孔 (其到達閘極電極）。在接觸孔中產生該接觸區。 此凹口中之隔離層之其餘部份可形成該隔離結構。在 此種情況下此遮罩（其用在接觸孔之遮罩式飩刻中）中 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再本頁) 訂： .線- 經濟部智慧財產局員工消費合作社印製 483169 A7 B7 五、發明說明（7 ) 之開口小於該凹口。 爲了在接觸區和源極/汲極區之間不會由於遮罩相對 於凹口所進行之對準而發生短路現象，則以下述方式產 生該隔離結構是有利的：在產生閘極電極之後沈積一種 絕緣材料且進行回蝕刻，以便產生一種間隔層（spacer)形 式之隔離結構。隔離結構產生之後產生該接觸區。隔離 結構產生之後但在該接觸區產生之前可沈積該隔離層。 選擇性地對該隔離結構進行遮罩式蝕刻，則可開啓此種 至閘極電極之接觸孔。由於選擇性地對該隔離結構而進 行蝕刻，則所使用之遮罩之開口可相對於該凹口而偏移 (dejiistiert)且重疊於該隔離結構上而不會在該接觸區和 源極/汲極區之間發生短路現象。另一方式是此接觸區 可在該隔離結構產生之後同樣產生於凹口中。 間隔層形成之隔離結構在第一源極/汲極區中之厚度 是與其在第二源極/汲極區中之厚度相同的。此接觸區 至第一源極/汲極區之距離因此等於此接觸區至第二源 極/汲極區之距離。 由於此MOS電晶體具有較高之電壓強度，其適合用 作高電壓電晶體。 此MOS電晶體例如適合以埋入式電晶體構成，其配 置在一種記憶胞配置（例如，EEPROMs )之週邊中。 該隔離層例如可以是一種中間氧化物，其沈積在 EEPROM 上。 閘極介電質可覆蓋在整個凹口，使閘極電極和該隔離 -9- ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 背 面 之 注 意 事 項 再 經濟部智慧財產局員工消費合作社印製483169 A7 B7 V. Description of the invention (1) The present invention relates to a MOS transistor and a manufacturing method thereof. Such a MOS transistor is described, for example, in German patent document 19807213.9. A trench is arranged in the substrate, and the trench has an enlarged area in a region on the substrate surface. An isolation structure is provided in the enlarged area. The highly doped regions of the two source / drain regions of the M 0 S transistor are adjacent to the enlarged region. A low-doped region of the two source / drain regions is disposed below the highly-doped region, and reaches a depth between the bottom of the notch and the enlarged region of the notch. An alarm dielectric is provided in the notch. A cylindrical gate electrode is arranged in the recess. The channel area of the MOS transistor is therefore U-shaped. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. To generate MOS transistors, first an isolation trench was created in the substrate with the aid of a first mask, and was inserted with an insulating material. Then another trench is created by means of a second mask, which is arranged inside the isolation trench and is deeper than the isolation trench. The remainder of the insulating material in the isolation trench forms each isolation structure. The isolation trench forms the notch with another trench, the notch having the enlarged area in the region of the isolation trench. This MOS transistor is suitable to be composed of a so-called buried MOS transistor, which is integrated in a circuit configuration formed by a transistor composed of other technologies. This M0S transistor has a high voltage strength and is suitable for use as a high voltage transistor. When the second mask is aligned relative to the first mask, the structure of the isolation structure in one source / drain region is different from that in the other source / drain region, so that the charge carrier is in one source. The average distance from the electrode / drain region to the channel region is greater than that from the other source / drain region to the channel region. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 483169 A7 B7 V. Description of the invention (2) This MOS transistor is based on the position of the source / drain region relative to the gate electrode Is asymmetric. The purpose of the present invention is to provide a MOS transistor which can be made with higher voltage strength and less space requirements. The asymmetry of the position of the source / drain region of the MQS transistor with respect to the gate electrode Sex can be ruled out. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. This purpose is achieved by a MOS transistor with a first source / drain region and a second source / drain region. Level surface and reach a first depth. A notch is disposed in the substrate between the first source / drain region and the second source / drain region, and the notch is adjacent to the first and second source / drain regions and is deeper than the first depth. deep. This notch is bounded on the side by the vertical planes of the substrate, which extend perpendicular to the horizontal plane of the substrate and extend from the horizontal plane of the substrate to the bottom of the notch. The gate electrode of the transistor is disposed in the recess and extends from the bottom of the recess to a first depth. The notch shall be provided with a gate dielectric to separate the gate electrode from the substrate. A contact area is arranged on the gate electrode. At least one isolation structure is disposed between the contact region and the first source / drain region and between the contact region and the second source / drain region. The isolation structure is disposed in the recess and extends from the gate electrode to at least this. The horizontal surface of the substrate is thicker than the gate dielectric. Since this isolation structure is thicker than the gate dielectric, it can increase the voltage intensity of the MOS transistor. The source / drain region is separated from the contact region by the isolation structure. This isolation structure reduces the capacitance formed by the contact area and the source / drain area. -4- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 483169 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The bottom surface of the mouth reaches the horizontal surface of the substrate) surrounds the notch on the side, so the notch does not have the above-mentioned enlarged area, so that the MOS transistor can have a particularly small space requirement. This notch does not particularly have the enlarged area, The structure of this enlarged region in the first source / drain region is different from that in the second source / drain region. This transistor is therefore symmetrical with respect to the position of the source / drain region relative to the gate electrode The structure of each source / drain region is preferably the same. The channel region of this MOS transistor is arranged between the two source / drain regions, which is adjacent to the notch. The channel region is U-shaped, which is Because the first depth reached by the source / drain region is above the bottom of the notch. Since the channel region is U-shaped, the channel length of the MOS transistor is compared with that of a planar MOS transistor. It is particularly large when the space requirements are the same. The larger the channel length, the M 0 S transistor can have a particularly large voltage intensity. The method of generating such a MOS transistor will be described below, which is also the object of the present invention. A notch must be created in the substrate. Make the side of the notch extend from the substrate to the horizontal surface of the substrate and extend to the bottom of the notch. A first source / drain region and a second source / drain region must be created in the substrate so that they are adjacent to the vertical. The surface is the boundary. These vertical planes extend from the horizontal surface of the substrate to the horizontal surface of the substrate and are adjacent to the notch to reach a first depth. The first depth is higher than the bottom of the notch and is provided with a gate dielectric. The gate electrode is generated in the bottom of the recess and the vertical plane of the substrate, which extends from the bottom of the recess to Di Yi's Zhu Zhu. A contact is made on the electrode of the paper. This paper applies the Chinese national standard ( CNS) A4 specification (210 X 297 mm) Please read the precautions of © before reprinting the page i Luding Line Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative 483169 A7 B7___ V. Description of Invention (4) At least one isolation structure is created between the contact region and the first source / drain region and between the contact region and the second source / drain region, which is arranged in a recess and extends from the gate electrode to at least this substrate It has a horizontal surface and is thicker than the gate dielectric. This contact area is created before or after the isolation structure is created. The notch is created, for example, by anisotropic etching of the substrate. Because this notch does not have the enlargement Area, the notch can be produced by the only etching step, so that the MOS transistor can be made with a small process cost. The isolation structure is generated inside the notch, and the notch is bordered by the vertical plane to make the isolation structure The form does not affect the form of the source / drain regions. The configuration of this notch in each source / drain region is the same because each vertical plane extends from the upper end to the bottom of the notch. Each source / drain region is self-aligningly adjacent to this notch and is generated. A doped layer is created by implantation or by epitaxy doped in suit. This doped layer is structured by creating at least one notch so that the doped layer forms a source / drain region. Another way is to first create the notch, and then implant it so that the source / drain region abuts the notch in a self-aligning manner. The gate electrode is generated in the notch in a self-aligned manner. Therefore, a conductive material must be deposited and etched back to the first depth. In order to simplify the process, it is advantageous to first generate the isolation structure, and then generate the contact region ^ In order to make the first source / drain region and the second source / drain region and each source / drain region The voltage strength between the gate electrode and electrode is increased, with -6- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before this page) Order: Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative 483169 Α7 Β7 V. Description of the invention (5) An advantageous method is that the first source / drain region is composed of the first highly doped region and the first low doped region, and The second source / drain region is composed of a second high-doped region and a second low-doped region. The first highly doped region and the second highly doped region extend from the second depth (which is above the first depth) to the horizontal surface of the substrate, respectively. The first lowly doped region and the second lowly doped region extend from the first depth to the second depth, respectively. The first highly doped region and the first low doped region are adjacent to each other. The second high-doped region is adjacent to the second low-doped region. The highly doped regions can be generated, for example, using such an implantation method having a first implantation energy. Each low-doped region can be generated by using such an implantation method having a second implantation energy (which is larger than the first implantation energy). Each of the highly doped regions and the lowly doped regions can also be generated by the same doping epitaxy in another way. In order to increase the voltage strength between the source / drain region and the substrate, the method of Yuli is: the first highly doped region is separated from the rest of the substrate by the first low doped region, and the second highly doped region The impurity region is separated from the rest of the substrate by a second low-doped region. In the interior of the substrate, the first low-doped region surrounds the first inferior region and the lower-lower region surrounds the second inferior region. The gate electrode and the source / drain regions are self-aligned with respect to the first depth to produce a 'right-low-robber' region with one of the vertical sections (which is adjacent to one of the vertical planes of the substrate and It extends from the first depth to the second depth). The first lowly doped region has a horizontal portion that is laterally adjacent to the vertical portion of the first lowly doped region and extends from a third depth (which is between the first depth and the second depth) to the second depth. The second low-doped region has a vertical part, which is adjacent to the substrate. -7- This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) (Please read the precautions on the back before this page) ) Order--1 line · 483169 A7-B7 V. Description of the invention (6) The other vertical plane extends from the first depth to the second depth. The second lowly doped region has a horizontal portion that is laterally adjacent to the vertical portion of the second lowly doped region and extends from a third depth to a second depth. In order to generate the vertical portion of the first low-doped region and the vertical portion of the second low-doped region, a tilt is required after the gate electrode is generated (but generated in the isolation structure and the contact region). Implantation, so that those parts of the vertical surfaces of the substrate that are not covered by the gate electrode are affected by this implantation. The source / drain region is generated in the manner described above so that the source / drain region and the gate electrode meet at the same depth (ie, the first depth). The source / drain region is self-aligned based on the depth of the gate electrode by tilted implantation. The horizontal part of the low-doped region is generated at a depth smaller than the first depth, so its position will not be deeper than the gate electrode and the source / drain region can be dependent on the gate electrode by tilted implantation To adjust the depth. In order to improve the conductivity, it is advantageous when the contact region contains a metal. This contact area is made of, for example, a metal (for example, aluminum) or a metal silicide (WSi). This contact region may also be made of doped polycrystalline silicon. The gate electrode is preferably composed of doped polycrystalline silicon. This contact area is produced, for example, in the following manner: After the gate electrode is produced, an isolation layer is created (which is sunk into the recess). A contact hole (which reaches the gate electrode) is opened in this isolation layer by mask etching. This contact area is created in the contact hole. The remainder of the isolation layer in the recess may form the isolation structure. In this case, the paper size of this mask (which is used in the mask engraving of the contact hole) applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back first) (On the next page) Order: .line-printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 483169 A7 B7 5. The opening of invention description (7) is smaller than the notch. In order not to cause a short circuit between the contact region and the source / drain region due to the alignment of the mask relative to the notch, it is advantageous to produce the isolation structure in the following manner: After the gate electrode is generated An insulating material is deposited and etched back to produce an isolation structure in the form of a spacer. The contact area is created after the isolation structure is created. The isolation layer may be deposited after the isolation structure is created but before the contact area is created. Selectively masking the isolation structure can open such a contact hole to the gate electrode. Since the isolation structure is selectively etched, the opening of the mask used can be dejiistiert relative to the notch and overlap the isolation structure without being in the contact area and the source / A short circuit occurs between the drain regions. Alternatively, the contact area may be created in the recess after the isolation structure is created. The thickness of the isolation structure formed by the spacer layer in the first source / drain region is the same as its thickness in the second source / drain region. The distance from this contact region to the first source / drain region is therefore equal to the distance from this contact region to the second source / drain region. Since this MOS transistor has a high voltage strength, it is suitable for use as a high voltage transistor. The MOS transistor is suitable, for example, as a buried transistor, which is arranged in the periphery of a memory cell configuration (e.g., EEPROMs). The isolation layer may be, for example, an intermediate oxide, which is deposited on the EEPROM. The gate dielectric can cover the entire notch to isolate the gate electrode from the -9- ^ paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) Please read the precautions on the back first to be economical Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperative

483169 A7 一 B7 五、發明說明（8 ) 結構都鄰接於閘極介電質。另一方式是只有閘極電極鄰 接於閘極介電質。在此種情況下此閘極介電質只配置在 此凹口之底部及配置在此基板之各垂直面之介於此凹口 之底部和第一深度之間之這些部份上。 本發明之實施例以下將依據圖式來詳述。圖式簡單說 明： 第1圖在第一摻雜層和第二摻雜層產生之後此基板之 橫切面。 第2圖在遮罩、凹口、第一源極/汲極區之第一高摻 雜區、第一源極/汲極區之第一低摻雜區之水平部份， 第二源極/汲極區之第二高摻雜區以及第二源極/汲極 區之第二低摻雜區之水平部份產生之後第1圖之橫切 面。 第3圖在閘極介電質、閘極電極、第一低摻雜區之垂 直部份以及第二低摻雜區之垂直部份產生之後第2圖之 橫切面。 第4圖在隔離結構、隔離層和接觸區產生之後第3圖 之橫切面。 經濟部智慧財產局員工消費合作社印製 這些圖式未依比例繪出。 在本實施例中設置一種由矽構成之基板1作爲原始材 料，此基板在水平表面Η之區域中以l〇15cm·3之摻雜物 質濃度來進行P -摻雜。 以η-摻雜用之離子在植入能量50KeV時所進行之植 入而產生一種200nm深之第一摻雜層S1，其鄰接於基板 -10- ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 483169 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（9 ) 1之水平表面Η (第1圖）。以η-摻雜用之離子在植入 能量200KeV時所進行之另一植入而在基板1中產生 3 00nm厚之第二摻雜層S2，其鄰接於第一摻雜層S1 (第 1圖）。 爲了產生一種遮罩M，須沈積400nm厚之Si〇2且藉 由微影術使SiCh被結構化。藉助於遮罩Μ而對基板1 作非等向性蝕刻800nm深而產生凹口 V (第2圖）。凹 口 V之水平橫切面是矩形的，其第一邊長是l//m，第 二邊長是500nm° 藉由凹口 V使第一摻雜層S 1和第二摻雜層S2被結構 化。於是由第一摻雜層S 1形成此MOS電晶體之第一源 極/汲極區S/D1之第一高摻雜區H1以及第二源極/汲 極區S/D 2之第二高摻雜區H2，凹口 V配置在此二個高 摻雜區之間且此二個高摻雜區鄰接於此凹口 V (第2 圖）。由第二摻雜層S2而產生第一源極/汲極區S/D1 之第一低摻雜區N 1之水平部份及第二源極/汲極區 S/D2之第二低摻雜區N2之水平部份，這些低摻雜區配 置在高摻雜區HI、H2下方。此外，由第二摻雜層S2而 產生第一低摻雜區N 1之垂直部份之一部份及第二低摻 雜區N2之垂直部份之一部份，這些部份在側面處鄰接 於低摻雜區N 1、N2之水平部份且鄰接於凹口 V。 藉由熱氧化作用而產生20nm厚之由SiCh構成之閘極 介電質GD，其覆蓋此凹口 V之底部及基板1之各垂直 面（其在側面鄰接於凹口 V)(第3圖）。 -11- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）483169 A7 B7 V. Description of the Invention (8) The structures are adjacent to the gate dielectric. Alternatively, only the gate electrode is adjacent to the gate dielectric. In this case, the gate dielectric is disposed only on the bottom of the notch and on the portions of the vertical planes of the substrate between the bottom of the notch and the first depth. Embodiments of the present invention will be described in detail below with reference to the drawings. The diagram simply illustrates: Figure 1 shows a cross-section of the substrate after the first doped layer and the second doped layer are produced. FIG. 2 is a horizontal portion of a mask, a notch, a first highly doped region of a first source / drain region, a first lowly doped region of a first source / drain region, and a second source The cross section of FIG. 1 after the horizontal portions of the second highly doped region of the / drain region and the second lowly doped region of the second source / drain region are generated. FIG. 3 is a cross-section of FIG. 2 after the gate dielectric, the gate electrode, the vertical portion of the first low-doped region, and the vertical portion of the second low-doped region are generated. FIG. 4 is a cross-section of FIG. 3 after the isolation structure, the isolation layer and the contact area are generated. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs These drawings are not drawn to scale. In this embodiment, a substrate 1 made of silicon is provided as a raw material, and the substrate is P-doped at a dopant substance concentration of 1015 cm · 3 in a region of the horizontal surface Η. Implantation with η-doping ions at an implantation energy of 50 KeV yields a first doped layer S1 at a depth of 200 nm, which is adjacent to the substrate -10- ^ Paper size applies Chinese National Standard (CNS) A4 Specification (210 X 297 mm) 483169 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The horizontal surface of invention description (9) 1 (Figure 1). Another implantation with η-doping ions at an implantation energy of 200 KeV results in a second doped layer S2 of 300 nm thickness in the substrate 1, which is adjacent to the first doped layer S1 (the first Figure). In order to produce a mask M, 400 nm thick Si02 must be deposited and SiCh structured by lithography. The substrate 1 is anisotropically etched to a depth of 800 nm by the mask M to generate a notch V (FIG. 2). The horizontal cross section of the notch V is rectangular. The first side length is 1 // m and the second side length is 500 nm. The first doped layer S 1 and the second doped layer S 2 are formed by the notch V. Structured. Therefore, the first doped layer S 1 forms the first highly doped region H1 of the first source / drain region S / D1 of the MOS transistor and the second of the second source / drain region S / D 2. The highly doped region H2 and the notch V are disposed between the two highly doped regions and the two highly doped regions are adjacent to the notch V (FIG. 2). A horizontal portion of the first low-doped region N 1 of the first source / drain region S / D1 and a second low-doped region of the second source / drain region S / D2 are generated by the second doped layer S2. In the horizontal portion of the impurity region N2, these lowly doped regions are arranged under the highly doped regions HI and H2. In addition, a portion of the vertical portion of the first low-doped region N1 and a portion of the vertical portion of the second low-doped region N2 are generated by the second doped layer S2, and these portions are at the sides Adjacent to the horizontal portions of the low-doped regions N1, N2 and adjacent to the notch V. A gate dielectric GD made of SiCh with a thickness of 20 nm is generated by thermal oxidation, which covers the bottom of this notch V and each vertical surface of the substrate 1 (which is adjacent to the notch V on the side) (Figure 3) ). -11- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

483169 A7 B7 五、發明說明（） 沈積同次（in situ)摻雜之200nm厚之多晶矽且進行回 蝕刻而產生此MOS電晶體之閘極電極GA。此閘極電極 GA由凹口 V之底部延伸至第一深度T1，其位於基板1 之水平表面Η下方600nm處（第3圖）。 以η-摻雜用之離子在相對於基板1之水平表面Η是 75 °之情況下進行一種傾斜式植入而對基板1之各垂直 面之未被閘極電極GA所覆蓋之這些部份進行植入。於 是在基板1中產生此低摻雜區Nl、Ν2之垂直部份之其 它部份（其鄰接於此基板1之各垂直面）。低摻雜區 Nl、Ν2分別由第一深度Τ1到達第二深度Τ2 (其在基板 1之水平表面Η下方200nm處）。低摻雜區Nl、N2之 水平部份分別由第三深度（其在基板1之水平表面Η下 方5 00nm處）到達第二深度Τ2。低摻雜區Nl、Ν2之垂 直部份分別由第一深度T 1到達第二深度T2。低摻雜區 N 1、N2之垂直部份分別具有一種與基板1之垂直面 (其與該垂直部份相鄰接）相垂直之尺寸（其大約是 1OOnm ) 〇 爲了產生各隔離結構I，須沈積500nm厚之氮化矽且 進行回（back)飩刻直至該遮罩Μ裸露爲止（第4圖）。 各隔離結構I由第二深度Τ1到達基板1之水平表面Η 上方3 50nm處。此隔離結構I配置在閘極電極GA上且 鄰接於閘極介電質GD。 藉由遮罩式蝕刻而產生800nm深之隔離溝渠（未顯 示），其圍繞此MOS電晶體。 -12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------% (請先閱讀背面之注意事項再填寫本頁) 訂---------線| « 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 483169 A7 _______JB7___ 五、發明說明（11 ) 沈積lOOnm厚之Si〇2以產生一種隔離層IS。此隔離 溝渠中以Si〇2植入。 藉由遮罩式蝕刻而在隔離層IS中開啓一個接觸孔， 其到達閘極電極GA。於是選擇性地對氮化矽來對SiCh 進行蝕刻，使隔離結構I不會受到侵飩。 沈積400nm厚之鋁（A1)且進行剝蝕直至該隔離層IS裸 露爲止以便產生一種接觸區K。此接觸區K與源極/汲 極區 S/D1、S/D2之距離由於該隔離結構I而成爲 7Onm 〇 基板1之此部份（其配置在第一源極/汲極區S/D 1 和第二源極/汲極區S/D2之間且鄰接於凹口 V )適合用 作通道區。 藉由本方法而產生MOS電晶體，其由於此凹口 V而 在較小之空間需求中具有較長之通道長度。由於源極/ 汲極區S/D 1、S/D2劃分成高摻雜區Η 1、N2及低摻雜區 Nl、Ν2，則此MOS電晶體之電壓強度特別高。由於該 隔離結構I，則接觸區κ和源極/汲極區s/D 1、S/D2之 間的電壓強度是很高的。此MOS電晶體就源極/汲極 區S/D 1、S/D2相對於閘極電極GA之位置而言是對稱 的。 本實施例可有許多變型，其同樣在本發明之範圍中。 因此，上述之各層、區域、凹口、結構和遮罩可依據各 別需求而調整。同樣情況亦適用於摻雜物質濃度以及材 料之選取。源極/汲極區S/D1、S/D2亦可以是ρ-摻雜 -13 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）483169 A7 B7 V. Description of the invention () Deposit 200nm thick polycrystalline silicon doped in situ and etch back to produce the gate electrode GA of this MOS transistor. The gate electrode GA extends from the bottom of the notch V to a first depth T1, which is located 600 nm below the horizontal surface Η of the substrate 1 (FIG. 3). The η-doping ions are implanted at an angle of 75 ° with respect to the horizontal surface of the substrate 1 to the portions of the vertical surfaces of the substrate 1 that are not covered by the gate electrode GA. Perform the implant. As a result, other parts of the vertical portions of the low-doped regions N1, N2 (which are adjacent to the vertical planes of the substrate 1) are generated in the substrate 1. The low-doped regions N1 and N2 respectively reach the second depth T2 from the first depth T1 (which is 200 nm below the horizontal surface 基板 of the substrate 1). The horizontal portions of the low-doped regions N1 and N2 respectively reach the second depth T2 from the third depth (which is 500 nm below the horizontal surface of the substrate 1). The vertical portions of the low-doped regions N1 and N2 respectively reach the second depth T2 from the first depth T1. The vertical portions of the low-doped regions N 1 and N 2 each have a dimension (which is about 100 nm) perpendicular to the vertical plane of the substrate 1 (which is adjacent to the vertical portion). In order to generate each of the isolation structures I, 500 nm thick silicon nitride must be deposited and etched back until the mask M is exposed (Figure 4). Each isolation structure I reaches the horizontal surface 基板 above the substrate 1 from the second depth T1 to a distance of 3 to 50 nm. This isolation structure I is disposed on the gate electrode GA and is adjacent to the gate dielectric GD. An isolation trench (not shown) having a depth of 800 nm is generated by mask etching, which surrounds the MOS transistor. -12- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) --------------% (Please read the precautions on the back before filling this page) Order --------- Line | «Printed by the Employees 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 483169 A7 _______JB7___ V. Description of the Invention (11) Deposit SiOO2 with a thickness of 100 nm To produce an isolation layer IS. This isolation trench is implanted with SiO2. A mask hole is used to open a contact hole in the isolation layer IS, which reaches the gate electrode GA. Therefore, silicon nitride is selectively etched to SiCh so that the isolation structure I is not attacked. A 400 nm-thick aluminum (A1) is deposited and etched until the isolation layer IS is exposed to create a contact area K. The distance between this contact region K and the source / drain regions S / D1, S / D2 becomes 7 nm due to the isolation structure I. This part of the substrate 1 (which is arranged in the first source / drain region S / D) 1 and the second source / drain region S / D2 and adjacent to the notch V) are suitable for use as a channel region. By this method, a MOS transistor is generated, which has a longer channel length in a smaller space requirement due to the notch V. Since the source / drain regions S / D 1, S / D2 are divided into high-doped regions Η1, N2, and low-doped regions N1, N2, the voltage intensity of this MOS transistor is particularly high. Due to the isolation structure I, the voltage intensity between the contact region? And the source / drain regions s / D1, S / D2 is very high. This MOS transistor is symmetrical with respect to the position of the source / drain regions S / D 1, S / D2 with respect to the gate electrode GA. There are many variations to this embodiment, which are also within the scope of the invention. Therefore, the above-mentioned layers, regions, notches, structures, and masks can be adjusted according to individual needs. The same applies to the dopant concentration and the selection of materials. The source / drain regions S / D1, S / D2 can also be ρ-doped -13-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

請 先 閱 讀 背 之 注 意 事 項 再 填赢1 寫彆 本 頁I I I 訂Please read the notes of the memorandum before you fill in the win.

線 I 483169 A7 B7 五、發明說明（12 ) 以取代η-摻雜。在此種情況下此基板1是η-摻雜的。亦 可產生各隔離結構I，使立刻沈積該隔離層IS而不是沈 積氮化矽且該隔離層IS中產生該接觸區K。此凹口 V 內部中之該隔離層IS之其餘部份在此情況下形成該隔 離結構I。 符號說明 1…基板 Μ…遮罩 SI、S2···摻雜層 Η…水平表面 V…凹口 HI、Η2…高摻雜區Line I 483169 A7 B7 V. Description of the invention (12) To replace η-doping. In this case, the substrate 1 is n-doped. It is also possible to generate each isolation structure I, so that the isolation layer IS is deposited immediately instead of depositing silicon nitride and the contact region K is generated in the isolation layer IS. The rest of the isolation layer IS in the interior of the notch V forms the isolation structure I in this case. DESCRIPTION OF SYMBOLS 1 ... substrate M ... mask SI, S2 ... doped layer Η ... horizontal surface V ... recess HI, Η2 ... highly doped region

Nl、Ν2…低摻雜區 S/D1、S/D2···源極/汲極區 GD···閘極介電質 GA···閘極電極 Τ1…第一深度 Τ2···第二深度 Τ3…第三深度 I、II…隔離結構 Κ…接觸區 IS···隔離層 -14- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 背 面 之 注 意 事 項 再 經濟部智慧財產局員工消費合作社印製Nl, N2 ... low doped regions S / D1, S / D2 ... source / drain regions GD ... gate dielectric GA ... gate electrode T1 ... first depth T2 ... Two depths T3 ... Third depth I, II ... Isolation structure K ... Contact area IS ... Isolation layer-14- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Please read the back Note Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Reeconomics

Claims (1)

483169 ‘.巧 ’::>厂 --------.....'」六、申請專利範圍 第89124919號「MOS電晶體及其製造方法」專利案 (90年12月修正） Λ申請專利範圍 1. 一種MOS電晶體，其特徵爲： —具有第一源極/汲極區（S/D1)和第二源極/汲極區 (S/D2)，它們配置在基板（1)中，鄰接於基板（1)之水平 表面（Η)且到達第一深度（Τ1)， —在第一源極/汲極區（S/D1)和第二源極/汲極區（S/D2) 之間於基板（1)中配置一個凹口（V)，此凹口（V)鄰接於 第一源極/汲極區（S/D1)及第二源極/汲極區（S/D2)且 較第一深度（Τ1)還深， —此凹口（V)在側面是以基板（1)之各垂直面爲界，各垂直 面垂直於基板（1)之水平表面（Η)而延伸且由基板（1)之 水平表面（Η)延伸至凹口（V)之底部， 一具有閘極電極（GA)，其配置在凹口（V)中且由凹口（V)之 底部延伸至第一深度（Τ1)， 一此凹口（V)須設有閘極介電質（GD)，使閘極電極（GA)與 基板（1)相隔開， —在閘極電極（GA)上配置一個接觸區（Κ)， —在接觸區（Κ)和第一源極/汲極區（S/D1)之間以及在接 觸區（Κ)和第二源極/汲極區（S/D2)之間配置至少一個 隔離結構（I)，此隔離結構⑴配置在凹口（V)中，由閘極 電極（GA)延伸到至少基板（1)之水平表面（Η)且較閘極介 電質（GD)還厚。 、申請專利範圍 2·如申請專利範圍第丨項之MOS電晶體，其中 —第一源極/汲極區（S/D1)由第一高摻雜區（H1)和第一低 摻雜區（N1)所構成， —第二源極/汲極區（S/D2)由第二高摻雜區（H2)和第二低 摻雜區（N2)所構成， 一第一高摻雜區（H1)和第二高摻雜區（H2)分別由第二深度 (T2)(其在第一深度（T1)上方）延伸至基板（1)之水平 表面（Η)， —第一低摻雜區（Ν1)和第二低摻雜區（Ν2)分別由第一深度 (Τ1)延伸至第二深度（Τ)。 3. 如申請專利範圍第2項之MOS電晶體，其中 一第一高摻雜區（Η1)藉由第一低摻雜區（Ν1)而與其餘之基 板（1)相隔開， 一第二高摻雜區（Η2)藉由第二低摻雜區（Ν2)而與其餘之基 板（1)相隔開。 4. 如申請專利範圍第2或第3項之MOS電晶體，其中 一第一低摻雜區（Ν1)具有一個垂直部份，其鄰接於基板（1) 之各垂直面之一且由第一深度（Τ1)延伸至第二深度 (Τ2)， 一第一低摻雜區（Ν1)具有一個水平部份，其在側面處鄰接 於第一低摻雜區（Ν1)之垂直部份且由第三深度（Τ3)(其 介於第一深度（Τ1)和第二深度（Τ2)之間）延伸至第二深 度（Τ2)， —第二低摻雜區（Ν2)具有一個垂直部份，其鄰接於基板（1) -2- 483169 六、申請專利範圍 之各垂直面之其它面且由第一深度（τι)延伸至第二深度 (T2)， 一第二低摻雜區（N2)具有一個水平部份，其在側面處鄰接 於第二低摻雜區（N2)之垂直部份且由第三深度（T3)延伸 至第二深度（T2)。 5.如申請專利範圍第1項之MOS電晶體，其中 一此接觸區（K)含有金屬， 一閘極電極（GA)由多晶矽構成。 6·如申請專利範圍第1，2,3或5項之MOS電晶體，其中 —該隔離結構（I)是間隔層（spacer)形式的， 一此接觸區（K)至第一源極/汲極區（S/D1)之距離等於此 接觸區（K)至第二源極/汲極區（S/D2)之距離。 7. —種MOS電晶體之製造方法，其特徵爲： —在基板（1)中產生一個凹口（V)，此凹口（V)之側面以基 板（1)之各垂直面爲界，各垂直面垂直於基板（1)之水平 表面（H)而延伸且由基板（1)之水平表面（H)延伸至凹口 (V)之底部， 一在基板（1)中產生第一源極/汲極區（S/D1)及第二源極 /汲極區（S/D2)，使它們鄰接於基板（1)之水平表面（H) 及凹口（V)且到達第一深度（T1)，第一深度（T1)較凹口（V) 之底部還高， 一凹口（V)之底部和基板（1)之各垂直面設有閘極介電質 (GD)， 一閘極電極（GA)產生於凹口（V)中且由凹口（V)之底部延伸 483169 六、申請專利範圍 至第一深度（τι)， 一在閘極電極（GA)上產生一個接觸區（K)， —在接觸區（K)和第一源極/汲極區（S/D1)之間以及在接 觸區（K)和第二源極/汲極區（S/D2)之間產生至少一個 隔離結構（I)，其配置在凹口（V)中，由閘極電極（GA)延 伸到至少基板（1)之水平表面（H)且較閘極介電質（GD)還 厚。 8. 如申請專利範圍第7項之方法，其中 一產生第一源極/汲極區（S/D1)之第一高摻雜區（H1)及第 二源極/汲極區（S/D2)之第二高摻雜區（H2)，這些高摻 雜區由第二深度（T2)(其在第一深度（T1)上方）延伸至 基板（1)之水平表面（H)， —產生第一源極/汲極區（S/D1)之第一低摻雜區（N1)及第 二源極/汲極區（S/D2)之第二低摻雜區（N2)，它們由第 一深度（T1)延伸至第二深度（T2)。 9. 如申請專利範圍第8項之方法，其中 一須產生第一高摻雜區（H1)，使其藉由第一低摻雜區（N1) 而與其餘基板（1)相隔開， 一須產生第二高摻雜區（H2)，使其藉由第二低摻雜區（N2) 而與其餘基板（1)相隔開。 10. 如申請專利範圍第8或第9項之方法，其中 一爲了產生第一低摻雜區（N1)之垂直部份及第二低摻雜區 (N2)之垂直部份，則須在閘極電極（GA)產生之後但在 該隔離結構⑴及接觸區（K)產生之前進行一種傾斜式植 -4- 483169 六、申請專利範圍 入，使基板（1)之各垂直面之未由閘極電極（GA)所覆蓋 之這些部份受到此種植入作用， 一須產生第一低摻雜區（N1)，使其水平部份在側面處鄰接 於第一低摻雜區（N1)之垂直部份且由第三深度（T3)(其 介於第一深度（T1)和第二深度（T2)之間）延伸至第二深 度（T2)， 一須產生第二低摻雜區（N2)，使其水平部份在側面處鄰接 於第二低摻雜區（N2)之垂直部份且由第三深度（T3)延伸 至第二深度（T2)。 11·如申請專利範圍第7項之方法，其中 一該接觸區K至少一部份是由金屬產生， 一閘極電極GA由多晶矽產生。 如申請專利範圍第7或11項之方法，其中 一在產生閘極電極（GA)之後產生一種隔離層（is)，其塡入 該凹口（V)中， 一藉由遮罩式蝕刻而在該隔離層（IS)中開啓一個接觸孔， 此接觸孔到達閘極電極（GA)， 一在接觸孔中產生該接觸區（K)。 如申請專利範圍第12項之方法，其中該隔離層之其餘部 份在凹口中形成該隔離結構。 如申請專利範圍第7或1 1項之方法，其中 一在閘極電極（GA)產生之後沈積一種絕緣材料且進行回 鈾刻，以便產生一種閘隔層（spacer)形式之隔離結構 ⑴， 483169 六、申請專利範圍 一接觸區（κ)在該隔離結構⑴產生之後才產生。 15.如申請專利範圍第1 2項之方法，其中 一在閘極電極（GA)產生之後沈積一種絕緣材料且進行回 蝕刻，以便產生一種閘隔層（spacer)形式之隔離結構 ⑴， 一接觸區（K)在該隔離結構⑴產生之後才產生。 -6-483169 '. 巧' :: > factory --------..... '' 'Patent Application No. 89124919 "MOS Transistor and Manufacturing Method" Patent Case (Amended in December 1990 ) Λ scope of patent application 1. A MOS transistor, characterized by:-having a first source / drain region (S / D1) and a second source / drain region (S / D2), which are arranged on a substrate In (1), the horizontal surface (Η) adjacent to the substrate (1) reaches the first depth (T1),-in the first source / drain region (S / D1) and the second source / drain region (S / D2) A notch (V) is disposed in the substrate (1), and the notch (V) is adjacent to the first source / drain region (S / D1) and the second source / drain region Area (S / D2) and deeper than the first depth (T1), the notch (V) is bounded by the vertical planes of the substrate (1) on the side, and each vertical plane is perpendicular to the level of the substrate (1) The surface (Η) extends from the horizontal surface (Η) of the substrate (1) to the bottom of the notch (V). A gate electrode (GA) is arranged in the notch (V) and is formed by the notch. The bottom of (V) extends to the first depth (T1), and the notch (V) must be provided with gate dielectric (GD) The gate electrode (GA) is separated from the substrate (1),-a contact region (K) is arranged on the gate electrode (GA),-the contact region (K) and the first source / drain region (S / D1) and at least one isolation structure (I) is disposed between the contact region (K) and the second source / drain region (S / D2), and the isolation structure ⑴ is disposed in the notch (V), The gate electrode (GA) extends to at least the horizontal surface (Η) of the substrate (1) and is thicker than the gate dielectric (GD). 2. Patent application scope 2 · For example, the MOS transistor in the first item of the patent application scope, wherein the first source / drain region (S / D1) is composed of the first high-doped region (H1) and the first low-doped region (N1), the second source / drain region (S / D2) is composed of the second highly doped region (H2) and the second low doped region (N2), a first highly doped region (H1) and the second highly doped region (H2) respectively extend from the second depth (T2) (above the first depth (T1)) to the horizontal surface (Η) of the substrate (1), the first low doped The impurity region (N1) and the second lowly doped region (N2) extend from the first depth (T1) to the second depth (T), respectively. 3. For the MOS transistor in the second item of the patent application, a first highly doped region (Η1) is separated from the rest of the substrate (1) by a first lowly doped region (N1), and a second The highly doped region (Η2) is separated from the rest of the substrate (1) by a second lowly doped region (N2). 4. For the MOS transistor in the second or third item of the patent application, one of the first low-doped regions (N1) has a vertical portion, which is adjacent to one of the vertical planes of the substrate (1) and is formed by the first A depth (T1) extends to a second depth (T2), a first lowly doped region (N1) has a horizontal portion, which is adjacent to a vertical portion of the first lowly doped region (N1) at a side and Extending from the third depth (T3) (between the first depth (T1) and the second depth (T2)) to the second depth (T2), the second lowly doped region (N2) has a vertical portion It is adjacent to the substrate (1) -2- 483169 6. Other surfaces of the vertical planes of the patent application range and extends from the first depth (τι) to the second depth (T2), a second low-doped region ( N2) has a horizontal portion which is adjacent to the vertical portion of the second lowly doped region (N2) at the side and extends from the third depth (T3) to the second depth (T2). 5. According to the MOS transistor of the first patent application, one of the contact areas (K) contains metal, and one of the gate electrodes (GA) is made of polycrystalline silicon. 6. If the MOS transistor of the scope of the application for the patent No. 1, 2, 3 or 5, in which-the isolation structure (I) is in the form of a spacer, the contact area (K) to the first source / The distance of the drain region (S / D1) is equal to the distance of this contact region (K) to the second source / drain region (S / D2). 7. A method for manufacturing a MOS transistor, characterized in that:-a notch (V) is generated in the substrate (1), and the sides of the notch (V) are bounded by the vertical planes of the substrate (1), Each vertical plane extends perpendicular to the horizontal surface (H) of the substrate (1) and extends from the horizontal surface (H) of the substrate (1) to the bottom of the notch (V). A first source is generated in the substrate (1) Electrode / drain region (S / D1) and second source / drain region (S / D2) so that they are adjacent to the horizontal surface (H) and the notch (V) of the substrate (1) and reach a first depth (T1), the first depth (T1) is higher than the bottom of the notch (V), a bottom of the notch (V) and a vertical surface of the substrate (1) are provided with a gate dielectric (GD), a The gate electrode (GA) is generated in the notch (V) and extends from the bottom of the notch (V) 483169 6. The scope of the patent application to the first depth (τι), a contact is made on the gate electrode (GA) Region (K), between the contact region (K) and the first source / drain region (S / D1) and between the contact region (K) and the second source / drain region (S / D2) At least one isolation structure (I) is generated, which is arranged in the recess (V), The gate electrode (GA) extends to at least the horizontal surface (H) of the substrate (1) and is thicker than the gate dielectric (GD). 8. If the method of claim 7 is applied, one of the first highly doped regions (H1) and the second source / drain regions (S / D1) generates a first source / drain region (S / D1). D2) second highly doped regions (H2), these highly doped regions extend from the second depth (T2) (above the first depth (T1)) to the horizontal surface (H) of the substrate (1),- A first low-doped region (N1) of the first source / drain region (S / D1) and a second low-doped region (N2) of the second source / drain region (S / D2) are generated. Extending from a first depth (T1) to a second depth (T2). 9. If the method of claim 8 is applied, one of them must generate a first highly doped region (H1), which is separated from the rest of the substrate (1) by the first lowly doped region (N1), one A second highly doped region (H2) must be generated so that it is separated from the rest of the substrate (1) by the second lowly doped region (N2). 10. If the method of claim 8 or 9 is applied for, one of the methods is to generate the vertical part of the first low-doped region (N1) and the vertical part of the second low-doped region (N2). After the gate electrode (GA) is generated, but before the isolation structure ⑴ and the contact area (K) is generated, an inclined planting is performed. 483 169 The parts covered by the gate electrode (GA) are subjected to this implantation. One must generate a first lowly doped region (N1) so that its horizontal portion is adjacent to the first lowly doped region (N1) at the side. ) And extends from the third depth (T3) (between the first depth (T1) and the second depth (T2)) to the second depth (T2), one must produce a second low doping Region (N2) such that its horizontal portion is adjacent to the vertical portion of the second lowly doped region (N2) at the side and extends from the third depth (T3) to the second depth (T2). 11. The method according to item 7 of the patent application, wherein at least a part of the contact area K is made of metal, and a gate electrode GA is made of polycrystalline silicon. For example, the method of claim 7 or 11 of the scope of patent application, one of which is to produce an isolation layer (is) after the gate electrode (GA) is generated, which is inserted into the recess (V), and A contact hole is opened in the isolation layer (IS), the contact hole reaches the gate electrode (GA), and the contact area (K) is generated in the contact hole. For example, the method of claim 12 in which the remaining part of the isolation layer forms the isolation structure in the recess. For example, the method of applying for item 7 or 11 of the scope of patent application, one of which is to deposit an insulating material after the gate electrode (GA) is generated and perform uranium engraving to produce an isolation structure in the form of a gate spacer, 483169 6. Scope of Patent Application-The contact area (κ) is generated after the isolation structure ⑴ is generated. 15. The method according to item 12 of the scope of patent application, wherein an insulating material is deposited and etched back after the gate electrode (GA) is produced, so as to produce an isolation structure in the form of a gate spacer, a contact The region (K) is generated after the isolation structure ⑴ is generated. -6-
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CN102064194A (en) * 2009-11-12 2011-05-18 三星电子株式会社 Recessed channel transistor devices, display apparatuses including recessed channel transistor devices, and methods of fabricating recessed channel transistor devices
WO2021017003A1 (en) * 2019-08-01 2021-02-04 深圳市汇顶科技股份有限公司 Capacitance measurement circuit, touch detection apparatus, and electronic device

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GB2103013B (en) * 1981-07-31 1984-11-07 Secr Defence A method for producing a misfet and a misfet produces thereby
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KR0173111B1 (en) * 1988-06-02 1999-02-01 야마무라 가쯔미 Trench gate metal oxide semiconductor field effect transistor
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102064194A (en) * 2009-11-12 2011-05-18 三星电子株式会社 Recessed channel transistor devices, display apparatuses including recessed channel transistor devices, and methods of fabricating recessed channel transistor devices
WO2021017003A1 (en) * 2019-08-01 2021-02-04 深圳市汇顶科技股份有限公司 Capacitance measurement circuit, touch detection apparatus, and electronic device
US11481072B2 (en) 2019-08-01 2022-10-25 Shenzhen GOODIX Technology Co., Ltd. Capacitance detection circuit, touch detection apparatus and electronic device

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