EP1175701A1 - Dispositif memoire et procede de fabrication associe - Google Patents

Dispositif memoire et procede de fabrication associe

Info

Publication number
EP1175701A1
EP1175701A1 EP00929252A EP00929252A EP1175701A1 EP 1175701 A1 EP1175701 A1 EP 1175701A1 EP 00929252 A EP00929252 A EP 00929252A EP 00929252 A EP00929252 A EP 00929252A EP 1175701 A1 EP1175701 A1 EP 1175701A1
Authority
EP
European Patent Office
Prior art keywords
trenches
produced
substrate
memory cell
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00929252A
Other languages
German (de)
English (en)
Inventor
Bernhard Sell
Josef Willer
Dirk Schumann
Hans Reisinger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1175701A1 publication Critical patent/EP1175701A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Definitions

  • the invention relates to a memory cell arrangement and a method for its production.
  • a so-called single-transistor memory cell is currently used almost exclusively, which comprises a transistor and a capacitor.
  • the information of the memory cell is stored in the form of a charge on the capacitor.
  • the capacitor is connected to the transistor in such a way that when the transistor is activated via a word line, the charge on the capacitor can be read out via a bit line.
  • the general aim is to produce a DRAM cell arrangement that has a high packing density.
  • EP 0852396 A2 describes a DRAM cell arrangement which comprises one-transistor memory cells.
  • the transistor of a memory cell is designed as a vertical transistor and is arranged on a flank of a depression in a substrate.
  • the depression is arranged in a rectangular region, which is surrounded by an insulating structure, and adjoins the insulating structure with a first flank.
  • a storage node of a capacitor of the storage cell, which adjoins the lower source / drain region, is arranged in a lower part of the depression.
  • a bit line is arranged on the upper source / drain region.
  • An insulated word line is arranged above the bit line, which has downward protrusions that travel into the recesses of the memory cells. Chen and act as gate electrodes of the transistors of the memory cells.
  • the memory cell is designed as a vertical transistor.
  • An upper and a lower source / drain region are parts of a cuboid projection of a substrate and are surrounded in a ring shape by a gate electrode.
  • the upper source / drain region also serves as a capacitor electrode of a capacitor of the memory cell.
  • a bit line is arranged above the capacitor electrode and at the same time serves as a further capacitor electrode of the storage capacitor.
  • the invention is based on the problem of specifying a further memory cell arrangement in which a memory cell comprises a transistor and a capacitor.
  • a production method for such a memory cell arrangement is also to be specified.
  • a memory cell arrangement in which a memory cell comprises a transistor and a capacitor and has the following features:
  • First trenches parallel to one another and second trenches running transversely to the first trenches are provided in a substrate.
  • An upper source / drain region of the transistor is arranged in the substrate and adjoins two of the first and two of the second trenches.
  • a lower source / drain region of the transistor is arranged in the substrate under the upper source / drain region.
  • the transistor is thus designed as a vertical transistor.
  • Conductive structures are arranged in the first trenches between the second trenches, each adjoining one of the upper source / drain regions on a first flank of the associated first trench and by an insulating structure arranged in the first trench from a second flank and from the bottom of the first trench iso- are.
  • a word line runs parallel to the first trenches and has protuberances that extend into the second trenches. Parts of the word line, which are arranged between the second trenches, are arranged over an insulating layer. The insulating layer is arranged over the upper source / drain region. A further insulating layer is arranged on the word line. Insulating spacers are laterally adjacent to the word line. The capacitor is connected to the upper source / drain region via a contact which is arranged on the conductive structure and between word lines.
  • first trenches which run essentially parallel to one another are produced in a substrate.
  • the first trenches are filled with insulating material.
  • the insulating material is partially replaced by conductive material in such a way that the conductive material adjoins the first flanks of the first trenches and the insulating material adjoins the second flanks and the bottoms of the first trenches.
  • An insulating layer is created that covers the conductive material.
  • Second trenches, which run essentially parallel to one another and transversely to the first trenches are produced in the substrate in such a way that conductive structures which are separate from one another are produced from the conductive material and insulating structures which are separate from one another from the insulating material.
  • Upper source / drain regions of vertical transistors and lower source / drain regions of the transistors arranged below are produced in the substrate such that the upper source / drain regions are in each case on a surface of the substrate, on two of the first trenches and on two of the border the second trenches.
  • word lines are produced in such a way that they have protuberances that extend into the second trenches and partially overlap two of the first trenches.
  • the word lines are isolated by a further insulating layer produced above and by spacers. The insulating layer becomes selective etched to the further insulating layer and to the spacers so that the conductive structures are exposed. Capacitors are created that are connected to the conductive structures via contacts.
  • the conductive structure is laterally adjacent to the upper source / drain region and is separated from the rest of the substrate by the insulating structure.
  • the conductive structure enables the upper source / drain region to be contacted from above, even though the word line is arranged above the upper source / drain region. Since the conductive structure and the upper source / drain region overlap on a large area, a contact resistance between the capacitor and the transistor is particularly small.
  • the memory cell arrangement can be produced with a high packing density, since the production method has many self-aligned process steps, ie process steps without masks to be adjusted, or process steps with large adjustment tolerances.
  • the upper source / drain region can be contacted by the capacitor without precise adjustment. Since the word line does not cover the conductive structure, etching can be carried out selectively to the further insulating layer and to the insulating spacers, so that the contacts are generated between adjacent word lines even if the alignment of the contacts with respect to the upper source / drain Areas is inaccurate.
  • the upper source / drain region can be produced in a self-aligned manner with respect to the first trenches and to the second trenches.
  • the substrate can be implanted, for example, after the first trenches and the second trenches have been produced.
  • a doped layer is produced in the substrate by implantation, which is structured by the first trenches and the second trenches, so that the upper source / drain regions are produced from the doped region.
  • the lower source / drain areas can also be self-aligned under the upper sources. ce / drain areas are generated.
  • the lower source / drain region is part of a buried doped layer of the substrate.
  • the adjustment tolerance of the word line is large, since only the condition that the protuberances extend into the second trenches, where they can act as gate electrodes of the transistors, and that, during selective etching to produce the contact of a memory cell, the upper source / drain Area of the adjacent memory cell is not exposed.
  • a width of the word line is preferably larger than a width of the upper source / drain region. This increases the adjustment tolerance for generating the word line and consequently increases process reliability. In this case, the word line partially overlaps the first two trenches.
  • the space requirement per memory cell of the memory cell arrangement can be 4F-2, where F is the minimum structure size that can be produced in the technology used.
  • F is the minimum structure size that can be produced in the technology used.
  • the first trenches and the second trenches have a width of F. Distances between adjacent first trenches or adjacent second trenches are then also F.
  • conductive material can first be deposited over the entire surface.
  • a strip-shaped word line mask is then generated, the strips of which have a width of F and a distance of F from one another.
  • the strips of the word line mask are then widened by depositing and etching back material, so that spacers are formed on the lateral surfaces of the word line mask.
  • the conductive material for the word lines can then be structured.
  • the memory cell arrangement can be produced in such a way that the word line has a high electrical conductivity, since parts le of the word line are not buried in the substrate and can consequently be produced from metal.
  • doped polysilicon is first deposited and then a metal or a metal silicide. Both materials are then structured using the word line mask.
  • the lower source / drain region can be connected to a bit line which runs transversely to the word line.
  • the bit line is arranged in a lower part of the second trench and adjoins the lower source / drain region on a first edge of the second trench.
  • the lower source / drain region preferably adjoins only the one of the two second trenches and is spaced apart from the other of the two second trenches.
  • the lower source / drain region can be produced, for example, by diffusing out dopant from the bit line.
  • the lower source / drain region can alternatively be produced from the buried doped layer of the substrate, which is structured by the second trenches.
  • lower source / drain regions of transistors which are adjacent to one another along the second trench are preferably separated from one another by the first trenches.
  • the first trenches are only deep enough to separate the upper source / drain regions of these transistors from one another, but not the lower source / drain regions of these transistors.
  • the bit line can contain metal to increase the electrical conductivity of the bit line.
  • a lower part of the bit line consists of metal and an upper part of the bit line that connects to the lower source / drain region adjacent, made of polysilicon.
  • a diffusion barrier separates the two parts.
  • the bit line can be designed as part of a capacitor electrode. In this case it runs above the substrate. In this case, lower source / drain regions of transistors which are adjacent to one another along one of the first trenches can be connected to one another.
  • the buried doped layer is preferably provided, which is not separated by the first trenches and the second trenches.
  • the conductive structures can be produced, for example, by first creating a protective layer on the substrate before producing the first trenches.
  • the protective layer consists, for example, of silicon nitride or of another material, which is preferably insulating.
  • the replacement of the insulating material with the conductive material is carried out in such a way that the insulating material is selectively etched to a depth with the aid of a strip-shaped mask, the strips of which run parallel to the first trenches and in each case partially overlap one of the first trenches that lies above the bottoms of the first trenches and then the conductive material is deposited and etched back until the protective layer is exposed.
  • the memory cell arrangement can be a DRAM cell arrangement.
  • the capacitors have a capacitor dielectric which preferably has a dielectric constant that is more than 20.
  • the capacitor dielectric consists of a ferroelectric with a Curie temperature below -50 ° C, e.g. Barium strontium titanate, or from Ta2Ü5.
  • the memory cell arrangement can be a FRAM memory cell arrangement.
  • the accounts capacitors a capacitor dielectric, which is a ferroelectric with a Curie temperature, preferably above 200 ° C.
  • FIG. 1 a shows a cross section through a substrate after a protective layer, first trenches, second trenches (shown in FIG. 1 b), upper source / drain regions, insulating structures and conductive structures have been produced. The position of a photoresist mask is also shown schematically.
  • FIG. 1b shows a cross section perpendicular to the cross section from FIG. 1 a through the substrate after the process steps from FIG.
  • FIG. 2 shows the cross section from FIG. 1b after a first part of an insulating layer and bit lines have been produced.
  • FIG. 3a shows the cross section from FIG. 1a after a second part of the insulating layer, lower source / drain regions, a word line mask, word lines, a second insulating layer and spacers have been produced.
  • FIG. 3b shows the cross section from FIG. 1b after the process steps from FIG. 3a.
  • FIG. 4 shows the cross section from FIG. 3a after insulation, contacts and storage nodes of capacitors have been produced.
  • FIG. 5 shows the cross section from FIG. 4 after a capacitor dielectric and a capacitor electrode of the capacitors have been produced.
  • the figures are not to scale.
  • a substrate 1 made of monocrystalline silicon is provided.
  • Thermal oxidation is carried out in order to generate an approximately 10 nm thick scatter oxide (not shown).
  • n-doping ions With the aid of n-doping ions, an implantation with an energy of approx. 10keV and a dose of approx. 5 * 10 1 4 C m ⁇ 2 is carried out over the entire area, so that a doped layer is produced which is attached to a surface of the substrate 1 adjacent.
  • a protective layer II is then produced by depositing silicon nitride to a thickness of approximately 30 nm (see FIGS. 1a and 1b).
  • first trenches G1 are produced in the substrate 1.
  • the first trenches G1 are approximately 100 nm wide and are at a distance of approximately 100 nm from one another (see FIG. 1 a).
  • SiO 2 is then deposited to a thickness of approx. 100 nm and planarized by chemical-mechanical polishing until the protective layer II is exposed.
  • SiO2 is etched approximately 50 nm deep.
  • the second photoresist mask F2 is removed.
  • the removed SiO 2 is replaced by conductive material in that in situ doped polysilicon is deposited to a thickness of approximately 50 nm and is planarized by chemical mechanical polishing until the protective layer II is exposed.
  • the strips of which run transversely to the first trenches Gl are approximately 100 nm wide and are spaced approximately 100 nm apart
  • the protective layer II is cut through and the substrate 1 approximately 500 nm etched. This creates second trenches G2 which are deeper than the first trenches G1 (see FIG. 1b).
  • the doped layer is structured by the first trenches G1 and the second trenches G2. Remaining parts of the doped layer are suitable as upper source / drain regions S / Do of transistors.
  • SiO 2 and the polysilicon are structured in the first trenches G 1 by the second trenches G 2, so that insulating structures I and conductive structures L are produced (see FIG. 1 a).
  • polysilicon and SiO2 are etched at approximately the same etching rate.
  • the third photoresist mask is removed.
  • SiO 2 is deposited in a thickness of approximately 15 nm.
  • SiO 2 covers the conductive structures L and flanks and bottoms of the second trenches G2.
  • in situ doped polysilicon is deposited to a thickness of approx. 50 nm and planarized by chemical mechanical polishing until the protective layer II is exposed. Then polysilicon is etched back to a depth of approx. 400 nm.
  • the fourth photoresist mask will be removed Subsequently, further in situ doped polysilicon is deposited to a thickness of approx. 50 nm and etched back to a depth of approx. 300 nm, so that a bit line B is generated in each of the second trenches G2, which leads to the second trench G2 on a second flank Substrate 1 adjoins (see Figure 2).
  • the protective layer II is removed (see FIG. 2).
  • Thermal oxidation is carried out to produce a second part of the insulating layer 12.
  • the insulating layer 12 also covers the bit lines B (see FIG. 3b).
  • the thermal oxidation acts as a tempering step, through which the dopant diffuses from the bit lines B into the substrate 1 and forms lower source / drain regions S / Du of the transistors there (see FIG. 3b).
  • Each of the lower source / drain regions S / Du adjoins that second trench G2 in which the bit line B is arranged from which the dopant with which the lower source / drain region was produced has diffused.
  • the lower source / drain region S / Du is arranged between this second trench G2 and an adjacent second trench G2 and is spaced apart from the adjacent second trench G2.
  • Polysilicon is then doped in situ in one
  • silicon nitride is deposited in a thickness of approximately 50 nm (see FIGS. 3a and 3b).
  • SiO 2 is applied in a thickness of approx. 50 nm and structured in a strip shape by means of a photolithographic process, so that the strips run parallel to the first trenches Gl and between see the trenches Gl are arranged.
  • the strips have a width of approximately 100 nm and a distance of approximately 100 nm from one another.
  • SiO 2 is deposited and etched back. This creates the word line mask, the stripes of which have a width of approximately 140 nm.
  • the strips of the word line mask WM each overlap two mutually adjacent first trenches G1 (see FIGS. 3a and 3b).
  • the word line mask WM With the help of the word line mask WM, the further insulating layer 13, tungsten silicide and polysilicon are etched until parts of the insulating layer 12, which are arranged on the bit lines B, are exposed.
  • the polysilicon and the tungsten silicide thus result in word lines W which run transversely to the bit lines B and have downward protuberances which extend into the second trenches G2 (see FIGS. 3a and 3b).
  • thermal oxidation is carried out in such a way that the insulating layer 12 is thickened in sections up to below the word lines W.
  • the insulating layer 12 is therefore thickened in the region of edges of the word lines W. This thermal oxidation corresponds to the so-called reoxidation step in planar transistors.
  • silicon nitride is deposited to a thickness of approximately 10 nm and etched back (see FIG. 3a).
  • the spacers Sp cover lateral surfaces of the word lines W.
  • SiO 2 is deposited in a thickness of approximately 100 nm. With the aid of a fifth photoresist mask (not shown), depressions which are separate from one another are produced in such a way that they each expose one of the conductive structures L (see FIG. 4). For this purpose, SiO 2 is selectively etched to silicon nitride. The adjustment tolerance of the recesses is large because the further insulating layer 13 and the spacers Sp protect the word lines W.
  • titanium and TiN are first deposited in a total thickness of approximately 20 nm. Subsequently, tungsten nitride is deposited in a thickness of approximately 50 nm, so that the depressions are filled. Tungsten nitride, titanium and titanium nitride are removed by chemical mechanical polishing until the insulation 14 is exposed. The contacts K are thereby generated between the word lines W in the depressions.
  • the storage nodes P1 are generated from the tungsten nitride via the contacts K (see FIG. 4).
  • SiO 2 is then etched to an etching depth of approximately 100 nm with hydrofluoric acid, so that parts of the insulation 14 which are arranged above the word lines W and the word line mask WM are removed (see FIG. 5). Titanium and titanium nitride at the storage nodes Pl are then e.g. removed with H2O2 / NH4OH.
  • Ta2Ü5 is deposited in a thickness of approximately 10 nm (see FIG. 5).
  • titanium nitride is deposited in a thickness of approximately 50 nm (see FIG. 5).
  • the memory cell arrangement produced is a DRAM cell arrangement, the memory cells of which each comprise a transistor and a capacitor.
  • the protuberances of the word lines W act as gate electrodes of the transistors.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un transistor de cellule mémoire qui comprend une région source/drain supérieure (S/Do) et une région source/drain inférieure, disposées entre deux premiers canaux (G1) et deux seconds canaux perpendiculaires aux premiers. Un canal mot isolé (W), recouvrant la région source/drain supérieure (S/Do), présente des protubérances qui vont jusque dans les seconds canaux (G2). Une structure conductrice (L), disposée dans l'un des premiers canaux (G1) et latéralement adjacente à la région source/drain supérieure (S/Do), est mise en contact à sa partie supérieure avec un élément de contact (K) situé entre les canaux mots (W) adjacents. Le contact (K) est relié à un condensateur (P1, Kd, P2) de la cellule mémoire, ledit condensateur étant placé au-dessus des canaux mots.
EP00929252A 1999-03-30 2000-03-27 Dispositif memoire et procede de fabrication associe Withdrawn EP1175701A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19914490A DE19914490C1 (de) 1999-03-30 1999-03-30 Speicherzellenanordnung und Verfahren zu deren Herstellung
DE19914490 1999-03-30
PCT/DE2000/000932 WO2000060667A1 (fr) 1999-03-30 2000-03-27 Dispositif memoire et procede de fabrication associe

Publications (1)

Publication Number Publication Date
EP1175701A1 true EP1175701A1 (fr) 2002-01-30

Family

ID=7902997

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00929252A Withdrawn EP1175701A1 (fr) 1999-03-30 2000-03-27 Dispositif memoire et procede de fabrication associe

Country Status (7)

Country Link
US (1) US6627940B1 (fr)
EP (1) EP1175701A1 (fr)
JP (1) JP3875493B2 (fr)
KR (1) KR100465040B1 (fr)
DE (1) DE19914490C1 (fr)
TW (1) TW465088B (fr)
WO (1) WO2000060667A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10318625B4 (de) * 2003-04-24 2006-08-03 Infineon Technologies Ag Vertikale Speicherzelle und Verfahren zu deren Herstellung
JP2009182105A (ja) 2008-01-30 2009-08-13 Elpida Memory Inc 半導体装置及びその製造方法
JP2010141259A (ja) 2008-12-15 2010-06-24 Elpida Memory Inc 半導体装置及びその製造方法
US11404091B2 (en) 2020-06-19 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array word line routing
US11423966B2 (en) 2020-07-30 2022-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array staircase structure

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793365B2 (ja) * 1984-09-11 1995-10-09 株式会社東芝 半導体記憶装置およびその製造方法
JP2932635B2 (ja) 1990-08-11 1999-08-09 日本電気株式会社 半導体記憶装置
JP2518147B2 (ja) 1993-04-02 1996-07-24 日本電気株式会社 半導体メモリ装置とその製造方法
US5497017A (en) 1995-01-26 1996-03-05 Micron Technology, Inc. Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors
DE19519159C2 (de) 1995-05-24 1998-07-09 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
US5937296A (en) * 1996-12-20 1999-08-10 Siemens Aktiengesellschaft Memory cell that includes a vertical transistor and a trench capacitor
TW428313B (en) 1998-05-19 2001-04-01 Siemens Ag Integrated circuit-arrangement with at least a transistor and a capacitor and method to it production
DE19911148C1 (de) * 1999-03-12 2000-05-18 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
None *
See also references of WO0060667A1 *

Also Published As

Publication number Publication date
KR100465040B1 (ko) 2005-01-13
US6627940B1 (en) 2003-09-30
JP2002541667A (ja) 2002-12-03
WO2000060667A1 (fr) 2000-10-12
KR20010110478A (ko) 2001-12-13
DE19914490C1 (de) 2000-07-06
TW465088B (en) 2001-11-21
JP3875493B2 (ja) 2007-01-31

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