Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
  • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B15/00—Systems controlled by a computer
  • G05B15/02—Systems controlled by a computer electric
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
  • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention pertains to fabrication of integrated circuits and more particularly to systems and methods for improving fabrication yields.
• Silicon based integrated circuit technology which has evolved into sub-micron line widths, is now able to produce chips containing millions of circuit elements.
• the process is extremely complex, requiring a large number of process steps to produce multi-level patterns of semiconductor, metals, and insulator types of materials.
• the circuits are interconnected by metal lines created in multilevel geometries through a large number of very small via holes. Every process step produces three dimensional statistical variations in the geometry and the materials properties of the final configuration. Such statistical variations, which include systematic and/or random defects, can result in both yield and performance degradation of the product. Yield and performance detractors can be found to vary across a chip, across the wafer and from wafer to wafer.
• the initial design simulations for an integrated circuit chip along with expert knowledge of the process capabilities generate a standard cell library that defines the standard device logic, memory and analog unit cells, and the design rules that define the limits and the desired dimensions of the multi-layer film and active device structures.
• This information is used to generate a mask set for the production of an integrated circuit product.
• a set of manufacturing process specifications is also generated which describes in detail the multitude of processes associated with each mask level.
• the mask generated for each process level defines the two dimensions parallel to the Si substrate, i.e. the planar dimensions of each processed layer.
• the manufacturing process specifications then determine the materials and their properties as well as the third dimension normal to the Si substrate, e.g. diffusion depths, metal thickness, and the thickness of thermally grown and deposited oxides.
• the classic s-shaped "learning curve” is a generally accepted concept that models the manufacturing cycle for the release of such high technology type products.
• the initial flat section of the curve represents the initial trials of the design and process, and generally is considered to represent essentially a very low and inconsistent yield output regime. In this initial stage, some changes to the manufacturing process specifications can be made in order to stabilize the process well enough to obtain a finite but consistent yield result.
• the so called “ramp up,” section of the manufacturing cycle is the section where yield of the product is consistent and is increasing rapidly.
• the end of the "learning curve” is relatively flat where the product yield is flat and stable.
• the cost of the product is essentially determined by the yield, because all the manufacturing costs are relatively fixed. It is well known that the manufacturing cost of the first two sections of this learning cycle are extremely high because of the amortized cost of multi-billion dollar manufacturing facilities, as well as the cost of highly skilled personnel. Thus, a profit greater than zero must be realized at some point of the "ramp up" cycle, and the projected business profit generally occurs at the beginning of the fixed yield cycle.
• Integrated circuit chips all undergo an extensive test procedure at the wafer level.
• Such product testers which are extremely expensive, are designed primarily to test for functionality. Only the nominal performance of the chip can be measured using these results since the probe contact configuration, as well as the limiting capability of the measuring circuits, prevent an accurate measurement of nanosecond switching speeds that can occur during the normal operation the chip. Further, product testers are not able to measure a large number of worst case line and via paths, or worst case gate logic fan-in and fan-out situations in order to evaluate the critical factors of the product design. Therefore, product testers cannot determine the cause of large yield variations when they occur, nor can they provide sufficient information that will lead to the improvement of the existing yield or performance of an integrated circuit product.
• SLM Scribe Line Monitor
• a characte ⁇ zation vehicle includes a single die, including a device neighborhood testing module for allowing measurement of va ⁇ ations in elect ⁇ cal performance of an active device due to a first plurality of process va ⁇ ations withm the active device, and a second plurality of process va ⁇ ations affecting an area su ⁇ oundmg the active device
• the device neighborhood testing module includes at least one active test device and an array of dummy devices, within which the active test device is located
• FIGURE 1 is a block diagram depicting the steps performed by a preferred embodiment of the system of the present invention.
• FIGURE 2 is a block diagram depicting additional steps performed by the system of the present invention to effect a feedback loop.
• FIGURE 3 is a plan view of a Device Neighborhood/Process Neighborhood (DN/PN) characte ⁇ zation vehicle (CV) according to the present invention.
• DN/PN Device Neighborhood/Process Neighborhood
• CV characte ⁇ zation vehicle
• FIGURE 4 is a plan view of the DN CV shown in FIG. 3.
• FIGURE 5 is a plan view of the PN CV shown in FIG. 3.
• FIGURE 6A shows a device under test in the DN CV of FIG 4, surrounded by dummy devices.
• FIGURE 6B is an enlarged view of a detail of FIG 6A
• FIGURE 7 is a diagram of typical DOE (design of expe ⁇ ments) va ⁇ ables for gate length and active width in the DN CV of FIG. 4.
• FIGURE 8 is a diagram of a typical DOE va ⁇ ables for the gate length and poly spacing for poly gate devices in the DN CV of FIG 4
• FIGURES 9A and 9B are diagrams showing a typical (DOE) for the active area including the active width and length, and the active area spacing for the DN CV of FIG. 4.
• DOE typical
• FIGURE 9C is a representation of the structural dimensions referred to in 9A and 9B for the DN CV of FIG. 4.
• FIGURES 10A-10C show special structures for the measurements referenced in Table 3 in the DN CV of FIG. 4.
• FIGURE 11 is a plan view of a typical PN module which includes line width structures in PN CV of FIG. 5.
• FIGURES 12A and 12B show representations of bridge and comb structures in the PN
• FIGURES 13 A and 13B show structures for the measurement of critical dimension and sheet resistance in the PN CV of FIG. 5, referenced in Table 5.
• FIGURE 14 is a plan view of a Kelvin structure used to measure critical dimensions in the PN CV of FIG. 5.
• FIGURES 15A-15C show structures used to measure junction leakage in the PN CV of FIG. 5 and referenced in Table 6.
• FIGURE 16 shows structures used to study the alignment of contact and vias in the PN CV of FIG. 5.
• FIGURE 17 shows a structure used to measure the impact of gate to contact spacing in the TESTCHIP module shown in FIG. 5.
• FIGURE 18 is a detailed schematic diagram of a basic device neighborhood cell.
• FIG. 19 is a diagram showing definitions of "shortable area" in a characterization vehicle.
• FIG. 20 is a diagram showing a test pattern for analyzing yield of T-shaped endings.
• FIG. 21 is a diagram of a nest structure for extracting defect size distributions.
• FIG. 22 is a logarithmic diagram of failures plotted against a parameter relating to number of lines shorted, line spacing, and width.
• a key element of the exemplary embodiment of the invention is a separate chip or Device Neighborhood/Process Neighborhood Characterization Vehicle (DN/PN CV) that can comprehensively represent any given manufacturing process for various families of integrated circuits.
• DN/PN CV provides a means to make meaningful measurements of the critical factors in the manufacturing process which determine the yield and performance of the product.
• the DN/PN CV provides a means to significantly shorten the time dependence of the first two sections of the "learning curve" described above.
• the DN/PN CV can be used to increase the yield and performance of an integrated circuit product in the case where it has progressed to the final stage of its product cycle.
• the DN/PN CV is able to be used in the product cycle at any stage of its development in order to provide yield and/or performance enhancements. Therefore, the DN/PN CV provides a new approach with regard to the solution of the most critical problems encountered in the development and the manufacturing of sub- micron integrated circuit technologies.
• the DN module allows testing of the impact on device performance a first plurality of process variations affecting the device and a second plurality of process variations affecting other devices su ⁇ ounding the device to be analyzed.
• the PN module allows testing of the impact on structure electrical characteristics of a first plurality of process variations affecting the structure, and the simultaneous effect of a second plurality of process variations of the other surrounding structures.
• the structures may include, for example, combs, snakes and the like.
• FIG. 1 there is shown a block diagram depicting the steps performed by a system, generally designated 10, for predicting integrated circuit yields in accordance with the present invention.
• the system 10 utilizes at least one type of characterization vehicle 12.
• the characterization vehicle 12 preferably is in the form of software containing information required to build an integrated circuit structure which incorporates at least one specific feature representative of at least one type of feature to be incorporated into the final product.
• the characterization vehicle 12 might define a test vehicle which can characterize selected lithographic layers for probing the health and manufacturability of the metal interconnection module of the process flow under consideration.
• the structures need to be large enough and similar enough to the actual product or type of products running in the fabrication process to enable a reliable capture or fingerprint of the various maladies that are likely to affect the product during the manufacturing process. .
• the characterization vehicle 12 defines features which match one or more attributes of the proposed product layout.
• the characterization vehicle 12 might define a CV module having a layout which includes features which are representative of the proposed product layout (e.g. examples of line size, spacing and periodicity; line bends and runs; etc.) in order to determine the maladies likely afflicting those specific design types and causing yield loss.
• the CV 12 might also define one or more active regions and neighboring features of the proposed design in order to explore impact of layout neighborhood on device performance and process parameters; model device parameters as a function of layout attributes; and determine which device correlate best with product performance.
• the characterization vehicle is designed to produce yield models 16 which can be used for accurate yield prediction. These yield models 16 can be used for purposes including, but not limited to, product planning, prioritizing yield improvement activities across the entire process, and modifying the original design of the product itself to make it more manufacturable.
• the majority of the test structures in the characterization vehicle 12 contemplated in the invention are designed for electrical testing. To this end, the reliability of detecting faults and defects in the modules evaluated by each characterization vehicle is very high. Inspection equipment cannot deliver or promise this high degree of reliability. Furthermore, the speed and volume of data collection is very fast and large respectively since electrical testing is fast and cheap. In this way, statistically valid diagnosis and/or yield models can be realized.
• the characterization vehicle 12 is preferably in the form of a GDS 2 layout on a tape or disc which is then used to produce a reticle set.
• the reticle set is used during the selected portions of the fabrication cycle 14 to produce the yield model 16.
• the yield model 16 is preferably constructed from data measured from at least a portion of a wafer which has undergone the selected fabrication process steps using the reticle set defined by the characterization vehicle 12.
• the yield model 16 not only embodies the layout as defined by the characterization vehicle, it also includes artifacts introduced by the fabrication process operations themselves.
• the yield model 16 may also include prototype architecture and layout patterns as well as features which facilitate the gathering of electrical test data and testing prototype sections at operating speeds which enhances the accuracy and reliability of yield predictions.
• An extraction engine 18 is a tool for extracting layout attributes from a proposed product layout 20 and plugging this information into the yield model 16 to obtain a product yield prediction 22.
• layout attributes might include, for example, via redundancy, critical area, net length distribution, and line width/space distribution. Then, given layout attributes from the proposed product layout 20 and data from yield models 16 which have been fabricated based upon information from the characterization vehicles 12, product yield 22 is predicted. Using the system and method of the present invention, the predictable product yield obtainable can be that .
• FIG. 2 there is shown a block diagram of the system for predicting integrated circuit yields 10 in accordance with the present invention additionally comprising a feedback loop, generally designated 24, for extracting design attributes 26 from product layout
• the characterization vehicle 12 is developed using attributes of the product layout 20.
• attributes of the product layout are extracted, making sure that the range of attributes are spanned in the characterization vehicle 12.
• the product layout is analyzed to determine line space distribution, width distribution, density distribution, the number of island patterns, in effect developing a subset of the entire set of design rules of the fabrication process, which subset is applicable to the particular product layout under consideration.
• the product layout analysis would determine the most common pattern, the second most common pattern, and so forth. These would be extracted by the extraction engine 28 yielding design attributes 26 encompassing all of these patterns for inclusion into the characterization vehicle 12.
• the characterization vehicle would include the entire range of 10% to 50% for the first metal.
• Figure 3 shows a layout of the DN/PN CV test vehicle that includes the device neighborhood and process neighborhood test engineering groups (DN and PN CVs), and other special structure modules.
• the device neighborhood (DN) subsection incorporates 200 or more discreet NMOS and PMOS transistor structures.
• the purpose of the DN CV is to quantify the impact of within die pattern variations on the performance of the transistor. Placing the test devices within an a ⁇ ay of dummy transistors derives the local pattern dependencies.
• the principal variants in the DN CV are polysilicon and active area density.
• special structures are included to investigate the impact of contact and gate spacing.
• the PN CV portion of the design is typically comprised of 17 or more sub-modules.
• the area containing these modules represents a size comparable to a large portion of a product chip..
• the purpose of these modules is to measure the impact of within die pattern variations on systematic yield loss associated with bridging, junction leakage, CD line width variation and contact and via formation.
• the PN CV accomplishes pattern-dependent characterization by varying the local process environment around the test structures. In this manner, the PN CV can effectively simulate the within-die pattern dependent process variations expected during normal manufactu ⁇ ng.
• both the DN and PN CVs offer a much more comprehensive vehicle for debugging and ramping processes into production.
• a special structure module provides a vehicle to characterize well and channel profiles as well as N+ and P+ sheet resistances, while other structures focuss on the effects of contact to gate spacing.
• the DN/PN CV test chip is composed of four major modules, the DN, PN, CVs MOSCAP and TESTCHIP...
• the DN module measures the variation in electrical device performance as a function of local process environment.
• the DN module is split into two types sub-modules: NMOS and PMOS and three process effects sub-modules: poly variant, active_variant, and special_structure.
• Figure 4 is a plan view of the DN CV.
• the poly variant submodule quantifies the relationship between polysilicon density and electrical device performance. Both macro_ and micro_effects are studied. Similar to the poly variant module, the active_variant structures study the influence of active_area density on the electrical performance of the transistor. Finally, in the special_structures module, the effects of contact_to_poly, contact_to_contact and poly_to_poly spacing are studied along with the influence of contact size.
• the PN test vehicle shown in Figure 5, is split into four types of effects modules: bridging_structures, CD (critical d ⁇ mension),_and_sheet_res ⁇ stance, junction_leakage, and contact_and_via.
• the bridging_structures devices consist of five modules which investigate poly_to_poly bridging on field oxide, poly_to_active bridging (N and P) and poly_to_poly bridging due to stringers at the field oxide edge (N and P).
• the CD_and_sheet_resistance structures measure CD control (e.g. line width), and sheet resistance of active (N+ and P+), gate (N+ and P+), and metal 1, metal 2. metal 3 and metal 4 interconnection layers.
• this part of the chip encompasses 4 sub-modules and 62 individual test structures.
• the junction_leakage section is composed of 2 modules with a total of 24 devices, which quantify the area leakage of N+ and P+ active as well as the perimeter leakage for active area bounded by gate and field.
• the contact_and_via submodule is directed at establishing guidelines for all contact and via formation for the four_layer metal process. This section consists of six sub-modules containing a total of 90 test structures.
• MOSCAP and TESTCHTP modules also shown in Figure 5, contain specialty devices that measure the active sheet resistance and well_ and channel_profiles as well as structures to determine the yield impact of contact to poly gate spacing.
• the purpose of the DN CV is to measure the effects of the local process environment on the final electrical performance of an MOS transistor. This is accomplished by placing the device under test in a "sea" of dummy devices which can be tailored to provide specific values for parameters such as poly and active area density.
• An example of such a layout is provided in Figure 6. In this figure, a large area of filled with dummy structures. The device under test is located at the center of the array of dummy devices. In this manner, the local process environment is effectively controlled.
• the DN module is composed of two type modules, NMOS and PMOS, which are identical in composition and consist of three effects sub-modules, poly variant, active_variant, and special_structure. Each sub-module is described in detail in Sections 3.1.1 through 3.1.3 below.
• Polysilicon etch loading can potentially impact final circuit performance by creating unanticipated and un-testable variation in the gate length within the die due to both macro and micro-density effects.
• the poly variant module incorporates 54 transistor structures in a design of experiments (DOE) that investigates the impact of micro_and macro-polysilicon density on gate length as a function of gate length and width.
• DOE design of experiments
• the DOE for gate length and active width is summarized in Figure 7.
• Six sets of transistors incorporate these gate/active_width variations and form another designed experiment in which the macroscopic polysilicon density is varied. Macroscopic variations are produced by tailoring the length and width of the gate on the dummy transistors within each test structure, while the micro-density effects are controlled by varying the number of gate fingers which are in close proximity.
• Table 1 The list of approximate polysilicon densities and multi-gate variations is provided in Table 1.
• micro-loading during the gate etch is investigated by the use of multi-gate structures.
• the active width is kept constant at 2 ⁇ m while the gate length, gate spacing and number of gates is varied according to Figure 8.
• the effects of macro-loading are also investigated by again varying the local polysilicon density.
• the polysilicon density variations for the multi-finger structures is shown in Table 2.Table 2 lists Target polysilicon densities for polysilicon multi-gateDOE in the PN-CV module.
• the active va ⁇ ant module incorporates 45 transistor structures in a design of expe ⁇ ments (DOE) that investigates the impact of active density on device performance as a function of gate length and width.
• DOE expe ⁇ ments
• the active density is controlled by tailo ⁇ ng the X and Y spacing on the dummy transistors within each test structure.
• the DOE of active spacmgs. Sx and Sy, is given in Figure 9C. For this set of test structures the gate length of the dummy transistors is fixed.
• the DN CV investigates the effects of contact- to-poly, contact-to-contact and poly-to-poly spacmgs, as well as the impact of contact size.
• DOE is contained with the spec ⁇ al_structures module
• the specifics of the va ⁇ ations are listed m Table 3 and Figures lOA-lOC.
• Table 3 provides a Summary of a DOE for c ⁇ tical dimensions of the special structure and devices m the PN-CV module
• FIG. 18 is a plan view showing a basic DN cell 1800 DN cell 1800 has a structure 1802 at its center that can be used in a device and Kelvin sheet resistance measurement, to measure a sheet resistance of the gate of the device 1804.
• Structure 1802 includes a st ⁇ pe 1806 which is an extension of the gate 1805 St ⁇ pe 1806 has four contacts 1808 at its ends Cu ⁇ ent is injected into two of the contacts 1808, and the voltage drop is measured across the other two contacts
• the device 1804 can be tested for functionality and cu ⁇ ent can also be injected through the gate line 1805, to measure voltage drop at the ends of the gate line. This will give a measure proportional to w, which in combination with a Van der Pauw measurement, can give sheet resistance.
• the purpose of the PN CV is to vary the environment around a given test structure to stimulate within_die pattern dependent variation.
• the local environment is controlled over a large area, comparable to a large area on a product chip.
• An example of such a layout is provided in Figure 11.
• a structure to measure line- width is surrounded by a comb-in-comb which dictates the local etch environment.
• CD can be co ⁇ elated with process layer density. In this manner, the test structure is a more accurate predictor for results on actual product.
• the PN CV module is composed of four major sub-modules: bridging_structures, CD_and_sheet_resistance, junction_leakage, and contact_and_via. Each sub-module is described in detail in Sections 3.2.1 through 3.2.4 below.
• the bridging _structures module composed entirely of snakes and combs, is incorporated to measure the effects of polysilicon and active area pitch on systematic yield loss due to polysilicon bridging.
• the module is divided into five sub-modules: SNK_CMB_FLD, SNK_CMB_PAA, SNK_CMB_NAA, SNK_CMB_PAA_FLD, and SNK_CMB_NAA_FLD.
• the SNK_CMB_FLD module looks at poly-to-poly bridging on field oxide.
• SNK_CMB_PAA and SNK_CMB_NAA investigate yield loss mechanisms due to polysilicon_to_active bridging across the sidewall spacer during the silicidation process.
• SNK_CMB_PAA_FLD and SNK_CMB_NAA_FLD focus on potential problems due to polysilicon-to-polysilicon bridging along a field edge caused by shallow trench isolation issues.
• Each of these sub-modules represents a DOE in which the dominant line width and space is varied.
• Table 4 Visual references for the parameter definitions are provided in Figures 12A and 12B Table 4
• the CD_and_sheet_resistance module is incorporated to measure the effects of etch loading on the CD of a given layer. Sheet resistance is included to provide necessary input for the line- width measurement structure.
• the CD_and_sheet _resistance is composed of four sub-modules:
• Line-width structures are included for each of the interconnect layers. These include N+ poly (NGC), P+ poly (PGC), Ml, M2, M3 and M4. Van der Pauw structures are included for each of the above layers as well as for N+ active (NAA) and P+ active (PAA).
• NNC N+ poly
• PPC P+ poly
• Ml M2, M3 and M4.
• Van der Pauw structures are included for each of the above layers as well as for N+ active (NAA) and P+ active (PAA).
• NAA N+ active
• Figures 13 A and 13B provide a visual definition of the parameters investigated.
• the structure used to measure CD is shown in Figure 14.
• a known current is forced from contact II to 12 and the co ⁇ esponding voltage drop is measured at contacts VI and V2.
• the equation which governs the voltage drop is
• the junction_leakage module is implemented within the PN CV to resolve the measured reverse_bias leakage cu ⁇ ent into its primary components of area, perimeter and corner for both field_ and gate_bcmnded diodes.
• the module also provides data on the influence of line width and pitch on the leakage current.
• the module consists of two identical sub-modules, NAA_JCT_LKG and PAA_JCT_LKG that incorporate N+/P and P+/N diodes, respectively.
• Table 6 lists the design attributes of the diodes contained within the junction eakage module. The parameters are defined schematically in Figures 15A-15C. Table 6 includes a summary of junction leakage DOE in the PN-CV module.
• the contact_and_via module is included in the PN CV to study systematic yield issues related to each of the contact_and _via etch steps included in the CMOSIS full_flow process.
• the module consists of six sub-modules: CONT_NAA, CONT_PAA, CONT_NGC, VIAl, VIA2 and VIA3.
• Each sub-module includes 15 contact or via structures for a total of 90.
• the test structures are split between two designed experiments. The first measures the effects of line_width, redundancy and spacing on via yield.
• This DOE is given in Table 7, including DOE for contact and via module in the PN-CV. In this Table DR is the minimum design rule and WIDE denotes some value significantly larger that the minimum dimension.
• MOSCAP The purpose of the MOSCAP module is to provide sheet resistance and capacitance measurements of individual implants not addressed in the PN CV.
• MOSCAP is composed of a single module containing five sheet resistance and 12 capacitor structures. The characteristics of the test structures are summarized in Table 9, including DOE for sheet resistance of source drain and capacity over implants in the DN-CV module. Table 9
• Sheet resistance is measured using the van der Pauw technique described in Section 3.2.2.
• the van der Pauw structures in the MOSCAP measure the resistance values for the deep source/drain and shallow extension implants.
• the capacitors are incorporated to measure the capacitance from gate_to_well and gate_to_well+channel in a standard_oxide_thickness_device as well as the capacitance from gate to well+channel for the thicker_oxide, high_voltage transistors.
• the purpose of the TESTCHIP module is to measure the impact of gate_to_contact spacing.
• the module incorporates 16 devices (8 NMOS/8 PMOS) in a single column of the CV.
• the structure used for this characterization incorporates asymetric contact spacing as is illustrated in Figure
• Table 10 gives the specific range of values for gate-to-contact spacing investigated in the experimental design.
• the structure utilizes a modified comb_in_comb arrangement.
• Each comb structure incorporates 80 gate fingers of 57.6 ⁇ m length providing a total critical perimeter of 4608 ⁇ m.
• Device test is performed by placing a voltage across the gate and active contacts and measuring the current between the contacts.
• Column 8 contains both NMOS and PMOS transistors.
• pads ⁇ 1> and ⁇ 17> provide connections to the PMOS WELL and SOURCE, respectively, while pads ⁇ 10> and ⁇ 26> provide contact to the NMOS WELL and SOURCE.
• Column 15 is unfilled, the WELL and SOURCE contacts are located at pads ⁇ 3> and ⁇ 19>, respectively.
• Pads ⁇ 1>, ⁇ 2>, ⁇ 17> and ⁇ 18> are not used.
• test configurations for each of the 17 PN CV modules is in Sections 4.2.1 through 4.2.4.
• pads involved as well as the measurement conditions on each pad are listed.
• device measurements can be correlated with the process neighborhood measurements, so that simulation models used to infer device performance can be verified.
• characterization vehicles for via, device, suicides, poly, el al are often designed and utilized. However, the procedure and techniques for designing them are the same. For purposes of illustration, the example metal characterization vehicle will be carried through on extraction engines and yield models.
• the extraction engine 18 has two main purposes: (1) it is used in determining the range of levels (e.g. linewidth, linespace, density) to use when designing a characterization vehicle. (2) It is used to extract the attributes of a product layout which are then subsequently used in the yield models to predict yield. (1) has already been described above with reference to how the line width, space and density of the snake, comb and Kelvin structures were chosen in the example characterization vehicle. Thus, most of the following discussion focuses on (2).
• levels e.g. linewidth, linespace, density
• the characterization vehicle drives which attributes to extract.
• the process consists of: 1. List all structures in the characterization vehicle
• C Kelvin_CD and CD variation across density, Histograms of pattern density, van der Pauws linewidth, and space linewidth, and linespace
• D Border structures Effect of different OPC For each OPC scheme selected to schemes on yield use on product layout, the shortable area or instance count.
• the yield model 16 is preferably constructed from data measured from at least a portion of a wafer which has undergone the selected fabrication process steps using the reticle set defined by the characterization vehicle 12.
• the yield is modeled as a product of random and systematic components:
• AREA BASED MODELS The area based model can be written as:
• Y 0 (q) is the yield of a structure with design factor q from the characterization vehicle.
• a 0 (q) is the shortable area of this structure and A(q) is the shortable area of all instances of type q on the product layout.
• Y r (q) is the predicted yield of this structure assuming random defects were the only yield loss mechanism. The procedure for calculating this quantity is described below in connection with random yield modeling.
• shortable area is best illustrated with the example shown in Figure 19.
• This type of test structure can be used to determine if the fab is capable of yielding wide lines that have a bend .with a spacing of s.
• a short is measured by applying a voltage between terminal (1) and (2) and measuring the current flowing from terminal (1) to (2). If this current is larger than a specified threshold (usually 1-lOOnA), a short is detected.
• the shortable area is defined to be the area where if a bridging occurs, a short will be measured. In the example of Figure 19, the shortable area is approximately x*s).
• the A(q) term is the shortable area of all occurrences of the exact or nearly exact patten (i.e. a large line with a spacing of s and a bend of 45 degrees) shown in Figure 19 in a product layout.
• the Yr(q) term is extracted by predicting the random yield limit of this particular structure using the critical area method described below.
• Ni(q) is the number of times the unit cell pattern or very similar unit cell pattern to the test pattern on the characterization vehicle appears on the product layout.
• No(q) is the number of times the unit cell pattern appears on the characterization vehicle.
• the random component can be written as:
• CA(x) is the critical area of defect size
• DSD(x) is the defective size distribution, as also described in"Modeling of Lithography Related Yield Losses for CAD of NSLI Circuits", W. Maly, IEEE Trans, on CAD, July 1985, ppl61-177, which is incorporated by reference as if fully set forth herein.
• Xo is the smallest defect size which can be confidently observed or measured.
• the critical area is the area where if a defect of size x landed, a short would occur. For very small x, the critical area is near 0 while very large defect sizes have a critical area approaching the entire area of the chip. Additional description of critical area and extraction techniques can be found in P. K. Nag and W. Maly, "Yield Estimation of VLSI Circuits," Techcon90, Oct. 16-18, 1990. San Jose; P. K. Nag and W.
• the defect size distribution represents the defect density of defects of size x.
• Do represents the total number of defects/cm 2 greater than x 0 observed.
• P is a unitless value which represents the rate at which defects decay over size.
• p is between 2 and 4.
• K is a normalization factor such that
• the nest structure is designed for extracting defect size distributions. It is composed of N lines of width w and space s as shown in Figure 21. This structure is tested by measuring the shorting current between lines 1 and 2, 2 and 3, 3 and 4, ..., and N-l and N. Any current above a given spec limit is deemed a short. In addition, opens can be testing by measuring the resistance of lines 1, 2, 3, ...., N-l, and N. Any resistance above a certain spec limit is deemed to be an open line. By examining how many lines are shorted together the defect size distribution can be determined.
• the defect size must be greater than s and no larger than 3w + 2s. Any defects smaller than s will not cause a short at all while defects larger than 3w+2s are guaranteed to cause a short of at least 3 lines. For each number of lines shorted, an interval of sizes can be created:
• Tables XIV through XVI are examples of information contained in such a spread sheet. It has been divided into sections of metal yield, poly and active area (AA) yield (Table XIV), contact and via yield (Table XV), and device yield (Table XVI). The columns on the left indicate systematic yield loss mechanisms while the columns on the right indicate random yield loss mechanisms. Although the exact type of systematic failure mechanisms vary from product to product, and technology by technology, examples are shown in Tables XIV through XVI. Usually, targets are ascribed to each module listed in the spread sheet.
• Mi yield loss is also dominated by a random defectivity issue (85.23%) in addition to a systematic problem affecting wide lines near small spaces (96.66%).

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