WO2001033834A1 - Procede et circuit de mise en evidence de contours - Google Patents
Procede et circuit de mise en evidence de contours Download PDFInfo
- Publication number
- WO2001033834A1 WO2001033834A1 PCT/JP2000/007485 JP0007485W WO0133834A1 WO 2001033834 A1 WO2001033834 A1 WO 2001033834A1 JP 0007485 W JP0007485 W JP 0007485W WO 0133834 A1 WO0133834 A1 WO 0133834A1
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- WO
- WIPO (PCT)
- Prior art keywords
- contour
- diagonal
- pixel
- circuit
- pixels
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/20—Circuitry for controlling amplitude response
- H04N5/205—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic
- H04N5/208—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic for compensating for attenuation of high frequency components, e.g. crispening, aperture distortion correction
Definitions
- the present invention relates to a contour emphasizing method and circuit for emphasizing a contour in consideration of the directionality of the contour when emphasizing the contour in processing a digital video signal.
- this type of conventional contour emphasizing circuit outputs a horizontal contour detecting unit 29, a vertical contour detecting unit 30 and outputs of the horizontal contour detecting unit 29 and the vertical contour detecting unit 30.
- An addition circuit 31 for addition is provided, and an addition circuit 32 for adding the contour component signal output from the addition circuit 31 to the video signal.
- the horizontal contour detection section 29 includes a contour detection filter 19 a directly connected to the video signal input terminal 10, and a contour detection filter connected via one 1-dot delay circuit 11. 19b, the output of the contour detection filter 19c connected via the two 1-dot delay circuits 11 and the outputs of the contour detection filters 19a, 19b, and 19c are added.
- the multiplication circuit 21 includes an addition circuit 20, a coefficient multiplication circuit 21 for multiplying a predetermined coefficient K 1, and a one-line delay circuit 34 connected to the coefficient multiplication circuit 21. That is, a horizontal contour component is detected from the target pixel and pixels one dot before and after the target pixel.
- the delay circuit 34 is for matching the output of the vertical contour detection unit 30 with the timing.
- the vertical contour detection section 30 includes a contour detection filter 19 a connected to the video signal input terminal 10 via one 1-dot delay circuit 11, and one 1-dot delay circuit 1.
- Contour detection filter connected via 1 and one 1-line delay circuit 1 2 1 b, connected via 1 1-dot delay circuit 1 1 and 2 1-line delay circuits 1 2
- Addition circuit 20 that adds the output of the detected contour detection filter 19 c and the outputs of the contour detection filters 19 a, 19 b, and 19 c, and a coefficient multiplication that multiplies a preset coefficient K 2.
- the circuit 21 is comprised. That is, a contour component in the vertical direction is detected from the target pixel and pixels before and after one line of the target pixel.
- the contour is a case where the luminance difference appears continuously, and if the luminance difference is not continuous, it cannot be said to be a contour.
- the points where the luminance "8" and the luminance "4" appear continuously in the horizontal and vertical directions are recognized as contours.
- the video signal input terminal 10 is connected to a digital video image with a contour of luminance “8” and luminance “4” in the diagonally right-up direction as shown in Fig. 3 (a). It is assumed that a signal has been input.
- the outputs of the contour detection files 19a, 19b, and 19c are as follows.
- the present invention provides a contour emphasizing method and circuit capable of detecting a directionality of a contour to process a contour emphasis at a point where a horizontal contour and a vertical contour intersect and an oblique contour point as a more natural contour. The purpose is to do so. Disclosure of the invention
- the present invention solves the problem of the point at which the horizontal contour and the vertical contour intersect with each other.
- the luminance of the pixel in the direction having the largest difference in luminance between the pixels in each direction and the luminance of the target pixel are weighted to obtain a contour emphasis value, and the contour emphasis value is added to the target pixel.
- This is a contour emphasizing method characterized by the following.
- the present invention solves not only a point at which a horizontal contour and a vertical contour intersect, but also a problem at an oblique contour point.
- Weighting is applied to the luminance of the pixel having the largest difference in luminance between the pixels in the vertical, right-up diagonal, and left-up diagonal directions, and the luminance of the target pixel to obtain an outline emphasis value.
- a pixel successive to the target pixel is sequentially repeated as a new target pixel, and when two consecutive contour enhancement values have the same sign, the contours before and after the two consecutive contour enhancement values are the same.
- the diagonal optimization processing that sets the contour emphasis values before and after the two consecutive contour emphasis values to 0 is performed.
- the corresponding contour emphasizing values of the diagonal optimization process respectively the This is a contour emphasizing method characterized by adding to a target pixel.
- FIG. 1 is a block diagram of a conventional edge enhancement circuit.
- FIG. 2 is a diagram showing signals of respective parts when a signal having a contour extending in the horizontal direction and the vertical direction is inputted to the contour emphasizing circuit in FIG. 1, and (a) shows a signal inputted from the video signal input terminal 10; (B) shows the output signal of the horizontal contour detector 29, (c) shows the output signal of the vertical contour detector 30, and (d) shows the video output terminal.
- FIG. 23 is a diagram illustrating output signals of 23.
- FIG. 3 is a diagram showing signals of respective parts when a signal having a contour extending in an oblique direction is input to the contour emphasizing circuit in FIG. 1, and (a) shows a digital signal input from a video signal input terminal 10; 5B is a diagram showing an output signal of the video output terminal 23.
- FIG. 3 is a diagram showing signals of respective parts when a signal having a contour extending in an oblique direction is input to the contour emphasizing circuit in FIG. 1, and (a) shows a digital signal input from a video signal input terminal 10; 5B is a diagram showing an output signal of the video output terminal 23.
- FIG. 4 is a block diagram showing a first embodiment of the contour emphasizing circuit according to the present invention.
- FIG. 5 is an explanatory diagram for explaining the operation of FIG.
- FIG. 6 is a diagram showing signals of respective parts of the contour emphasizing circuit in FIG. 4, (a) is a diagram showing an original image of a digital signal input from the video signal input terminal 10, and (b) is a diagram showing a contour detecting unit. 18 is a diagram illustrating an output signal of FIG. 18, and (c) is a diagram illustrating an output signal of the video output terminal 23.
- FIG. 7 is a block diagram showing a second embodiment of the contour emphasizing circuit according to the present invention.
- FIG. 8 is an explanatory diagram for explaining the operation of the oblique optimization circuit 25 in FIG.
- FIG. 9 is a diagram showing signals at various parts of the contour emphasizing circuit in FIG. 7, (a) is a diagram showing an original image of a digital signal input from the video signal input terminal 10, and (b) is a diagram showing an addition circuit 2.
- FIG. 3C is a diagram illustrating an output signal of 0
- FIG. 3C is a diagram illustrating an output signal after the diagonal optimization processing is performed by the diagonal optimization circuit 25
- FIG. 3D is a diagram illustrating an output signal of the video output terminal 23. .
- the present invention employs only a pixel as a center, and adopts only the edge enhancement value in the direction having the largest absolute value between horizontal, vertical, right-upward diagonal, and left-upward diagonal pixels adjacent to this pixel, and Ensure that contour enhancement is not performed more than necessary at intersections of contours and vertical contours and at oblique contour points. It was made. In this way, contour enhancement at points where horizontal and vertical contours intersect and at diagonal contour points is processed twice and processed as a more natural contour without inconvenience due to the lack of necessary contour enhancement. It is made possible.
- the present invention further solves the problem not only at the intersection of the horizontal contour and the vertical contour, but also at the oblique contour point, when two consecutive weighted contour enhancement values have the same sign. If the two consecutive edge enhancement values before and after the two consecutive edge enhancement values are adopted as they are, and if the two consecutive weighted edge enhancement values have different signs, the two consecutive edge enhancement values will be used. A diagonal optimization process of 0 is performed, and the contour emphasis value subjected to the diagonal optimization process is added to the target pixel.
- the horizontal pixel B1, B3, the vertical pixel A2, C2, the right-up diagonal pixel C1, A which are adjacent to the B2 pixel shown in FIG. 3.
- Al and C3, 6 1-dot delay circuits 11 and 2 1-line delay circuits 12 are connected to the video signal input terminal 10. Combined.
- C2 is one pixel delay by one 1-dot delay circuit 11 and C1 is B 2 is a one-line delay due to two one-dot delay circuits 1 1, B 3 is a one-line delay due to one one-line delay circuit 12, and so on, B 2 is a one-line delay and a one-pixel delay.
- 1 is one line and two pixels behind
- A3 is two lines behind
- A2 is two lines and one pixel behind
- A1 is two lines and two pixels behind.
- the contour direction detecting section 24 will be described in detail.
- the horizontal direction 8 1 and 8 3 are sequentially turned to a subtraction circuit 13 a for detecting the difference and an absolute value calculation circuit 14 a.
- C1 and A3 in the diagonally right-up direction are sequentially connected to a subtraction circuit 13b that detects the difference and an absolute value calculation circuit 14b, and A2 and C2 in the vertical direction are
- the subtraction circuit 13 for detecting the difference and the absolute value calculation circuit 14 c are sequentially connected to each other. It is sequentially connected to the value calculation circuit 14d.
- These absolute value calculation circuits 14 a to 14 d are connected to a maximum value detection circuit 15, and this maximum value detection circuit 15 is connected between the first selection circuit 16 and the ⁇ 2 selection circuit 17. Output a signal to select one of the horizontal pixels Bl, B3, vertical pixels A2, C2, right-up diagonal pixels Cl, A3, and upper-left diagonal pixels A1, C3 .
- the output of the first selection circuit 16 is applied to an outline detection filter 19a of an outline detection unit 18; the output of the second selection circuit 17 is applied to an outline detection filter 19c; Each of the contour detection filters 19a, 19b, and 19c is connected to a contour detection filter 19b.
- the contour detection filters 19a, 19b, and 19c are connected to an addition circuit 20. Both are connected to the addition circuit 22.
- A1, A2, A3, B1, B2, B3, C1, C2, and C3 are set to have the same time by the one-dot delay circuit 11 and the one-line delay circuit 12.
- the absolute value of the horizontal pixel IB1—B3I is the maximum value.
- the contour detector 18 calculates ( ⁇ B 1 + 2 B 2-B 3) Z4 and calculates the absolute value of the vertical pixel.
- the contour enhancement effect can be performed without any problem on the contours in the horizontal direction and the 33 ⁇ 41 ⁇ direction, but there is a slight problem that the contours on the oblique contours are overemphasized. Have a point.
- the oblique optimizing circuit 25 is interposed between the adding circuit 20 and the coefficient multiplying circuit 21 to eliminate the above-mentioned inconvenience.
- the diagonal optimization circuit 25 has three 1-dot delay circuits 11 connected in series, and a switching section 27 interposed between the first 1-dot delay circuit 11 and the adder circuit 20. Then, a switching section 28 is interposed between the third one-dot delay circuit 11 1 and the coefficient multiplier 3 ⁇ 4?: Circuit 21, and the output side of the first one-dot delay circuit 11 1?
- a sign comparison unit 26 for comparing these codes is connected to the output side of the 1-dot delay circuit 11 of the second fi, and the switching unit 27 and the switching unit 2 are connected by the output of the sign comparison unit 26. 8 is switched and controlled. Note that a three-dot delay circuit 33 is inserted before the adder circuit 22 in order to time the signal B2 due to the interposition of the oblique optimization circuit 25.
- the output of the adder 20 in the contour detector 18 is the same as in the first embodiment, and corresponds to XI, X2, X3, and X4 in FIG.
- ⁇ second one-dot delay circuit 11 1 are compared by the sign comparison unit 26.
- contour detection filters 19 a and 19 of the contour detection unit 18 are shown.
- the coefficients of b and 19 c are respectively set to — 1 Z 4, 1/2 and 1 1 4, but are not limited to these, and adding 3 coefficients becomes 0, for example, 1 1 Z5, 2Z5, 1-15, etc.
- A1 to A5, B1 to B5, C1 to C5, D1 to D5, and E1 to E5, C3 is the center pixel, and the luminance difference In the horizontal direction, the difference between 1 and 5 and the difference between C 2 and C 4 are detected.
- each coefficient can be set to, for example, 1/16, -2/16, 6/16, -2 / 16.1-1Z16.
- not all 25 pixels are subject to the calculation, but the 8 pixels A2, A4, B1, B5, D1, D5, E2, and E4 are excluded from the detection.
- the horizontal, vertical, upper right diagonal, and upper left diagonal 17 pixels are the targets of the performance.
- the contour emphasizing method and circuit according to the present invention enhances the contour in a natural state even at the point where the horizontal contour crosses the vertical contour or when a digital video signal having a diagonal contour is input. It can be used for natural contour enhancement of PDP and LCD driven by digital video signal.
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Picture Signal Circuits (AREA)
- Image Analysis (AREA)
- Image Processing (AREA)
- Studio Circuits (AREA)
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002389599A CA2389599C (en) | 1999-10-30 | 2000-10-25 | Method and circuit for emphasizing contour |
US10/089,799 US6980258B1 (en) | 1999-10-30 | 2000-10-25 | Method and circuit for emphasizing contour |
EP00970084A EP1227668A4 (en) | 1999-10-30 | 2000-10-25 | METHOD AND CIRCUIT FOR HIGHLIGHTING CONTOURS |
AU79582/00A AU772526B2 (en) | 1999-10-30 | 2000-10-25 | Method and circuit for emphasizing contour |
HK03102421A HK1053562A1 (en) | 1999-10-30 | 2003-04-04 | Method and circuit for emphasizing contour. |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11/346641 | 1999-10-30 | ||
JP34664199A JP3743235B2 (ja) | 1999-10-30 | 1999-10-30 | 輪郭強調方法及び回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001033834A1 true WO2001033834A1 (fr) | 2001-05-10 |
Family
ID=18384829
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2000/007485 WO2001033834A1 (fr) | 1999-10-30 | 2000-10-25 | Procede et circuit de mise en evidence de contours |
Country Status (11)
Country | Link |
---|---|
US (1) | US6980258B1 (ja) |
EP (1) | EP1227668A4 (ja) |
JP (1) | JP3743235B2 (ja) |
KR (1) | KR100473191B1 (ja) |
CN (1) | CN1175658C (ja) |
AU (1) | AU772526B2 (ja) |
CA (1) | CA2389599C (ja) |
HK (1) | HK1053562A1 (ja) |
RU (1) | RU2256297C2 (ja) |
TW (1) | TW516315B (ja) |
WO (1) | WO2001033834A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8310566B2 (en) | 2005-12-28 | 2012-11-13 | Olympus Corporation | Image pickup system and image processing method with an edge extraction section |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100433875B1 (ko) * | 2002-01-31 | 2004-06-04 | 엘지전자 주식회사 | 디스플레이 장치의 샤프니스 보정장치 |
JP4044826B2 (ja) * | 2002-07-25 | 2008-02-06 | 富士通株式会社 | 半導体集積回路 |
KR100870015B1 (ko) * | 2002-08-13 | 2008-11-21 | 삼성전자주식회사 | 디지털 화상 데이터의 윤곽 강조 장치 및 그 방법, 이를이용한 디지털 표시 장치 |
JP4390506B2 (ja) * | 2003-09-02 | 2009-12-24 | 三洋電機株式会社 | 水平輪郭補正回路 |
FR2867935A1 (fr) * | 2004-03-17 | 2005-09-23 | Thomson Licensing Sa | Procede de rehaussement des contours dans une image |
JP4031462B2 (ja) * | 2004-04-23 | 2008-01-09 | 松下電器産業株式会社 | 輝度信号処理装置、信号処理装置および輝度信号処理方法 |
JP2005341021A (ja) * | 2004-05-25 | 2005-12-08 | Matsushita Electric Ind Co Ltd | 輪郭強調処理装置 |
TWI272853B (en) | 2005-09-21 | 2007-02-01 | Quanta Comp Inc | Image edge enhancement apparatus and method thereof |
JP4552881B2 (ja) * | 2006-04-03 | 2010-09-29 | 日本ビクター株式会社 | 映像信号処理装置 |
KR20070099170A (ko) * | 2006-04-03 | 2007-10-09 | 엘지.필립스 엘시디 주식회사 | 데이터 변환장치 및 변환방법과 이를 이용한 영상표시장치의 구동장치 및 구동방법 |
JP4701144B2 (ja) * | 2006-09-26 | 2011-06-15 | 富士通株式会社 | 画像処理装置、画像処理方法および画像処理プログラム |
KR101086424B1 (ko) * | 2007-01-12 | 2011-11-23 | 삼성전자주식회사 | 디지털 영상 처리 장치 및 방법 |
KR101346084B1 (ko) * | 2007-11-23 | 2013-12-31 | 엘지디스플레이 주식회사 | 영상의 선명도 개선회로 및 개선방법 |
WO2014091720A1 (ja) * | 2012-12-10 | 2014-06-19 | パナソニック株式会社 | 輪郭補正装置および画像処理装置 |
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JPH10257352A (ja) * | 1997-03-15 | 1998-09-25 | Sunao Shibata | 半導体演算回路 |
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1999
- 1999-10-30 JP JP34664199A patent/JP3743235B2/ja not_active Expired - Fee Related
-
2000
- 2000-10-24 TW TW089122335A patent/TW516315B/zh not_active IP Right Cessation
- 2000-10-25 AU AU79582/00A patent/AU772526B2/en not_active Ceased
- 2000-10-25 WO PCT/JP2000/007485 patent/WO2001033834A1/ja active IP Right Grant
- 2000-10-25 KR KR10-2002-7005411A patent/KR100473191B1/ko not_active IP Right Cessation
- 2000-10-25 CN CNB008148325A patent/CN1175658C/zh not_active Expired - Fee Related
- 2000-10-25 US US10/089,799 patent/US6980258B1/en not_active Expired - Fee Related
- 2000-10-25 CA CA002389599A patent/CA2389599C/en not_active Expired - Fee Related
- 2000-10-25 RU RU2002114042/09A patent/RU2256297C2/ru not_active IP Right Cessation
- 2000-10-25 EP EP00970084A patent/EP1227668A4/en not_active Withdrawn
-
2003
- 2003-04-04 HK HK03102421A patent/HK1053562A1/xx not_active IP Right Cessation
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JPH0279566A (ja) * | 1988-09-14 | 1990-03-20 | Dainippon Screen Mfg Co Ltd | 画像の輪郭強調方法 |
JPH08289173A (ja) * | 1995-04-14 | 1996-11-01 | Matsushita Electric Ind Co Ltd | 輪郭補正回路 |
JPH10257352A (ja) * | 1997-03-15 | 1998-09-25 | Sunao Shibata | 半導体演算回路 |
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US8310566B2 (en) | 2005-12-28 | 2012-11-13 | Olympus Corporation | Image pickup system and image processing method with an edge extraction section |
Also Published As
Publication number | Publication date |
---|---|
US6980258B1 (en) | 2005-12-27 |
RU2256297C2 (ru) | 2005-07-10 |
CN1382342A (zh) | 2002-11-27 |
KR20020047295A (ko) | 2002-06-21 |
CA2389599A1 (en) | 2001-05-10 |
EP1227668A4 (en) | 2005-11-30 |
KR100473191B1 (ko) | 2005-03-10 |
EP1227668A1 (en) | 2002-07-31 |
AU772526B2 (en) | 2004-04-29 |
JP3743235B2 (ja) | 2006-02-08 |
CN1175658C (zh) | 2004-11-10 |
CA2389599C (en) | 2008-04-22 |
AU7958200A (en) | 2001-05-14 |
TW516315B (en) | 2003-01-01 |
HK1053562A1 (en) | 2003-10-24 |
JP2001128031A (ja) | 2001-05-11 |
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