WO2001015219A3 - Verfahren zur herstellung einer integrierten schaltung mit mindestens einer metallisierungsebene - Google Patents

Verfahren zur herstellung einer integrierten schaltung mit mindestens einer metallisierungsebene Download PDF

Info

Publication number
WO2001015219A3
WO2001015219A3 PCT/DE2000/002811 DE0002811W WO0115219A3 WO 2001015219 A3 WO2001015219 A3 WO 2001015219A3 DE 0002811 W DE0002811 W DE 0002811W WO 0115219 A3 WO0115219 A3 WO 0115219A3
Authority
WO
WIPO (PCT)
Prior art keywords
metalicized
conductors
dielectric layer
layer
dielectric
Prior art date
Application number
PCT/DE2000/002811
Other languages
English (en)
French (fr)
Other versions
WO2001015219A2 (de
Inventor
Siegfried Schwarzl
Manfred Engelhardt
Franz Kreupl
Original Assignee
Infineon Technologies Ag
Siegfried Schwarzl
Manfred Engelhardt
Franz Kreupl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Siegfried Schwarzl, Manfred Engelhardt, Franz Kreupl filed Critical Infineon Technologies Ag
Priority to JP2001519483A priority Critical patent/JP2003508896A/ja
Priority to KR1020027002328A priority patent/KR20020025237A/ko
Priority to EP00965776A priority patent/EP1212794A2/de
Publication of WO2001015219A2 publication Critical patent/WO2001015219A2/de
Publication of WO2001015219A3 publication Critical patent/WO2001015219A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Zur Herstellung einer Metallisierungsebene mit Leitungen und Kontakten werden auf ein Substrat (4) dielektrische Schichten aufgebracht. Es erfolgt zunächst eine Kontaktlochätzung durch die obersten beiden dielektrischen Schichten in die darunterliegende dielektrische Schicht, wobei die verbleibende Dicke dieser Schicht im wesentlichen gleich der Dicke der obersten Schicknt ist. Anschließend erfolgt eine Leitungsgrabenätzung selektiv zu der ersten dielektrischen Schicht und der dritten dielektrischen Schicht, deren Oberfläche im wesentlichen gleichzeitig freigelegt werden. Nach Strukturierung der ersten dielektrischen Schicht und der dritten dielektrischen Schicht werden Kontakte und Leitungen in den Kontaktlöchern und Leitungsgräben erzeugt.
PCT/DE2000/002811 1999-08-25 2000-08-18 Verfahren zur herstellung einer integrierten schaltung mit mindestens einer metallisierungsebene WO2001015219A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001519483A JP2003508896A (ja) 1999-08-25 2000-08-18 少なくとも１つのメタライゼーション面を有する集積回路の製造方法
KR1020027002328A KR20020025237A (ko) 1999-08-25 2000-08-18 적어도 하나의 금속화 평면을 구비한 집적회로의 생산 방법
EP00965776A EP1212794A2 (de) 1999-08-25 2000-08-18 Verfahren zur herstellung einer integrierten schaltung mit mindestens einer metallisierungsebene

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19940358 1999-08-25
DE19940358.9 1999-08-25

Publications (2)

Publication Number Publication Date
WO2001015219A2 WO2001015219A2 (de) 2001-03-01
WO2001015219A3 true WO2001015219A3 (de) 2001-07-19

Family

ID=7919589

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/002811 WO2001015219A2 (de) 1999-08-25 2000-08-18 Verfahren zur herstellung einer integrierten schaltung mit mindestens einer metallisierungsebene

Country Status (7)

Country Link
US (2) US20020098679A1 (de)
EP (1) EP1212794A2 (de)
JP (1) JP2003508896A (de)
KR (1) KR20020025237A (de)
CN (1) CN1192427C (de)
TW (1) TW461037B (de)
WO (1) WO2001015219A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605540B2 (en) 2001-07-09 2003-08-12 Texas Instruments Incorporated Process for forming a dual damascene structure
KR100506943B1 (ko) * 2003-09-09 2005-08-05 삼성전자주식회사 식각정지막으로 연결홀의 저측면에 경사를 갖는 반도체소자의 제조 방법들
US20060261036A1 (en) * 2005-04-11 2006-11-23 Stmicroelectronics S.R.L. Method for patterning on a wafer having at least one substrate for the realization of an integrated circuit
US7358182B2 (en) * 2005-12-22 2008-04-15 International Business Machines Corporation Method of forming an interconnect structure
US7592253B2 (en) * 2005-12-29 2009-09-22 Dongbu Electronics Co., Ltd. Method for forming a damascene pattern of a copper metallization layer
EP1990432B1 (de) * 2006-02-28 2012-04-11 Advanced Interconnect Materials, LLC Halbleitervorrichtung, herstellungsverfahren dafür und sputtern von zielmaterial zur verwendung für das verfahren
US20080303154A1 (en) * 2007-06-11 2008-12-11 Hon-Lin Huang Through-silicon via interconnection formed with a cap layer
DE102007054384A1 (de) 2007-11-14 2009-05-20 Institut Für Solarenergieforschung Gmbh Verfahren zum Herstellen einer Solarzelle mit einer oberflächenpassivierenden Dielektrikumdoppelschicht und entsprechende Solarzelle
TWI490939B (zh) * 2008-10-01 2015-07-01 Vanguard Int Semiconduct Corp 孔洞的形成方法
CN102543837A (zh) * 2010-12-22 2012-07-04 中芯国际集成电路制造(上海)有限公司 顶层金属互连层结构和制作方法
EP2820672A2 (de) * 2012-03-01 2015-01-07 Koninklijke Philips N.V. Drahtanordnung für eine elektronische schaltung und verfahren zur herstellung davon
KR102477608B1 (ko) * 2017-12-12 2022-12-14 삼성디스플레이 주식회사 표시 기판, 표시 기판의 제조 방법 및 표시 기판을 포함하는 표시 장치
CN112018077A (zh) * 2020-07-29 2020-12-01 复旦大学 一种铜互连结构及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19723062A1 (de) * 1996-07-13 1998-01-22 Lg Semicon Co Ltd Verfahren zum Bilden einer selbst ausgerichteten Metallverdrahtung für ein Halbleiterbauelement
US5821169A (en) * 1996-08-05 1998-10-13 Sharp Microelectronics Technology,Inc. Hard mask method for transferring a multi-level photoresist pattern
WO1999033102A1 (en) * 1997-12-19 1999-07-01 Applied Materials, Inc. An etch stop layer for dual damascene process
WO2000003432A1 (en) * 1998-07-09 2000-01-20 Applied Materials, Inc. Plasma etch process of a dielectric multilayer structure particularly useful for dual damascene
WO2000059030A1 (fr) * 1999-03-26 2000-10-05 Commissariat A L'energie Atomique Procede de creation de lignes de connexion et de points de contact sous-jacents dans un substrat dielectrique

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5143820A (en) * 1989-10-31 1992-09-01 International Business Machines Corporation Method for fabricating high circuit density, self-aligned metal linens to contact windows
US6197696B1 (en) 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
JP3657788B2 (ja) * 1998-10-14 2005-06-08 富士通株式会社 半導体装置及びその製造方法
US6326301B1 (en) * 1999-07-13 2001-12-04 Motorola, Inc. Method for forming a dual inlaid copper interconnect structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19723062A1 (de) * 1996-07-13 1998-01-22 Lg Semicon Co Ltd Verfahren zum Bilden einer selbst ausgerichteten Metallverdrahtung für ein Halbleiterbauelement
US5821169A (en) * 1996-08-05 1998-10-13 Sharp Microelectronics Technology,Inc. Hard mask method for transferring a multi-level photoresist pattern
WO1999033102A1 (en) * 1997-12-19 1999-07-01 Applied Materials, Inc. An etch stop layer for dual damascene process
WO2000003432A1 (en) * 1998-07-09 2000-01-20 Applied Materials, Inc. Plasma etch process of a dielectric multilayer structure particularly useful for dual damascene
WO2000059030A1 (fr) * 1999-03-26 2000-10-05 Commissariat A L'energie Atomique Procede de creation de lignes de connexion et de points de contact sous-jacents dans un substrat dielectrique

Also Published As

Publication number Publication date
KR20020025237A (ko) 2002-04-03
US6930052B2 (en) 2005-08-16
CN1377511A (zh) 2002-10-30
WO2001015219A2 (de) 2001-03-01
US20040092093A1 (en) 2004-05-13
CN1192427C (zh) 2005-03-09
EP1212794A2 (de) 2002-06-12
US20020098679A1 (en) 2002-07-25
TW461037B (en) 2001-10-21
JP2003508896A (ja) 2003-03-04

Similar Documents

Publication Publication Date Title
EP0887849A3 (de) Herstellungsverfahren von einem Kondensator für eine Halbleitervorrichtung
WO2002054446A3 (en) Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices
SG125881A1 (en) Define via in dual damascene process
WO2002017387A3 (en) Conductive material patterning methods
TW377502B (en) Method of dual damascene
WO2005013363A3 (de) Schaltungsanordnung auf einem substrat und verfahren zum herstellen der schaltungsanordnung auf dem substrat
WO2001015219A3 (de) Verfahren zur herstellung einer integrierten schaltung mit mindestens einer metallisierungsebene
WO2006013230A3 (en) Manufacture of a layer including a component
WO2006056643A3 (en) Method for manufacturing an electronics module
WO2006037933A3 (fr) Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees
TW200725864A (en) Semiconductor structure, electrical fuse and method of making same
KR890015376A (ko) 전자소자에 대한 전기적 접속방법
WO2006104817A3 (en) Method for reducing dielectric overetch when making contact to conductive features
WO2004095515A3 (en) Methods for contracting conducting layers overlying magnetoelectronic elements of mram devices
EP1050905A3 (de) Halbleitervorrichtung mit isolierender Schicht
WO2004077548A3 (de) Verbindungstechnik für leistungshalbleiter
WO2002023625A3 (en) Semiconductor device and fabrication method therefor
WO2003019649A3 (de) Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnung
EP0769813A3 (de) Integrierte Schaltung mit planarisierter dielektrischer Schicht zwischen aufeinanderfolgenden Polysilizium-Schichten
EP1408724A4 (de) Schaltungsausgebildetes substrat und verfahren zur herstellung des schaltungsausgebildeten substrats
KR100299379B1 (ko) 반도체소자의금속배선형성방법
KR100299521B1 (ko) 반도체 소자의 배선 형성방법
JP2000003961A5 (de)
WO1995028000A3 (en) Method of manufacturing a semiconductor device with a multilayer wiring structure containing narrow vias
WO1998054755A3 (en) A method of manufacturing an electronic device whereby a conductive layer is provided on an electrically insulating substrate, from which layer a conductor pattern is formed

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
ENP Entry into the national phase

Ref country code: JP

Ref document number: 2001 519483

Kind code of ref document: A

Format of ref document f/p: F

WWE Wipo information: entry into national phase

Ref document number: 2000965776

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1020027002328

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 008120277

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 1020027002328

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2000965776

Country of ref document: EP

WWR Wipo information: refused in national office

Ref document number: 1020027002328

Country of ref document: KR

WWW Wipo information: withdrawn in national office

Ref document number: 2000965776

Country of ref document: EP