WO2000059030A1 - Procede de creation de lignes de connexion et de points de contact sous-jacents dans un substrat dielectrique - Google Patents
Procede de creation de lignes de connexion et de points de contact sous-jacents dans un substrat dielectrique Download PDFInfo
- Publication number
- WO2000059030A1 WO2000059030A1 PCT/FR2000/000717 FR0000717W WO0059030A1 WO 2000059030 A1 WO2000059030 A1 WO 2000059030A1 FR 0000717 W FR0000717 W FR 0000717W WO 0059030 A1 WO0059030 A1 WO 0059030A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- locations
- mask
- etched
- lines
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 239000000203 mixture Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 239000011347 resin Substances 0.000 abstract description 16
- 229920005989 resin Polymers 0.000 abstract description 16
- 239000000463 material Substances 0.000 abstract description 9
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
Definitions
- connection lines and contact or crossing points ("contact noies” or “via holes” in English) extending under these lines in an insulating substrate to a lower stage of the circuit.
- This technique of creating connection lines and contact points by depositing a conductive material there after having hollowed out the circuit substrate at the corresponding locations is often called double damascene, alluding both to the old process of creating a pattern. by embedding a metal in imprints of another material, and carrying out the process at two depths of the substrate.
- the advantage of this process in the semiconductor industries is that it does not require etching of the conductive material, which would be a delicate operation like copper which we would like to use more often in place of aluminum. more widespread today.
- the invention originates from the desire to use substrates made of material with low peritivity, and the observation that these materials were easily degraded by the solvents and the oxygen plasma used to remove the resin layers after the attack of the hard masks.
- resin is poured into the etched parts in order to etch the second mask and must then be removed, which inevitably exposes the substrate material to degradation.
- US Patent 5,821,169 describes a process where a single mask is engraved several times at different depths; a layer of resin which covers it is removed at the locations of the points, and the mask is engraved over part of its depth; then the layer of resin is removed at the locations of the lines, and the mask is etched again until a
- the second step of etching the mask, necessary to expose the substrate at the locations of the lines is an anisotropic etching, over the entire surface of the mask, from which the resin which covered it has been removed before etching the points in the substrate: such an engraving is also exerted laterally and widens the locations of the lines, the exact width of which becomes impossible to know; the risks of short circuit in the integrated circuit will be increased when it is completed.
- the inventors therefore concluded that the resin had to be kept separate from the material of the substrate, and found a particular order of the steps necessary to achieve the structure of the integrated circuit which satisfied this requirement; this process is the subject of the invention. It is characterized in that, successively: a lower mask is deposited on the substrate; an upper mask is deposited on the lower mask; the upper mask is attacked at the locations of the lines; the lower mask is attacked at the point locations; holes are etched in the substrate at the locations of the points; the lower mask is attacked at the locations of lines; trenches are etched in the substrate at the locations of the lines; and conductive material is deposited in the holes and the trenches to respectively give the contact points and the connection lines.
- Figure 1 represents a portion of the circuit obtained by the invention, where the conductive material
- Figures 2, 3, 4, 5A, 6, 7A, 8, 9A and 10 illustrate the stages of creation of the circuit according to an embodiment of the invention
- FIG. 1 • and Figures 2A, 6A, 8A and 10A illustrate a more complex embodiment.
- An integrated circuit shown in FIG. 1 comprises a dielectric or semiconductor substrate 1 in a stage 2 from which connection lines 3 have been made parallel to one another and, under them, contact points 4 which connect them to regions 5 point or linear, sources, drains, memory points or others, established in a lower stage 6 of the substrate 1.
- the levels of lines 3 and points 4 in stage 2 are separated by an intermediate layer 7 dielectric in silicon oxide ; the lower sub-layer of stage 2, under the intermediate layer 7, may be 0.9 ⁇ m thick, and the upper sub-layer 0.5 ⁇ m. Other values are obviously possible, and the total thickness of stage 2 can be between 0.5 ⁇ m and approximately 2 ⁇ m.
- the object of the method proposed here is to produce the stage 2 of the substrate 1 from a smooth layer, in accordance with the following figures.
- FIG. 2 shows that the first steps consist in depositing successively on stage 2 of substrate, by chemical deposits, for example in vapor phase (CVD), by sputtering, a mask lower 8 which may be made of silicon oxide, and an upper mask 9 which will serve as a mask for etching the interconnection lines and which may be made of nitride, carbide or silicon oxide on the lower mask 8; then a first layer of resin 10 is deposited on the upper mask 9, except at the locations 11 located at the locations of the connection lines 3 (FIG. 3). A subsequent chemical attack removes the upper mask 9 at these locations 11 while sparing the lower mask 8, then the first layer of resin 10 is removed, and we arrive at the state of FIG. 4.
- CVD vapor phase
- a second layer of resin 12 is deposited on the upper mask 9 and the part of the lower mask 8 which has been exposed, except at the locations 13 of the contact points 4.
- the resulting state is illustrated in FIG. 5A for perfect alignment or centering of the locations 11 and 13 ; one cannot however exclude misalignments which will have the effect, if they are large enough, of deporting the free locations of resin astride the masks 8 and 9: this situation is represented in FIG. 5B where the locations bear the reference 13 '; we will come back to the consequences of such a situation.
- the next step of the process consists in attacking the lower mask 8 at the free locations
- the last steps of the method consist in selectively attacking the lower mask 8 but not the upper mask 9, in order to expose the substrate 1 over the entire surface of the connection lines 3 (FIG. 8), then to resume etching of the substrate 1 of so as to create trenches 15 at the locations of the connection lines 3 while completing the etching of the holes 14; this etching is continued until the desired digging depth is reached, and in particular until the trenches 15 reach the intermediate layer 7, which however resists etching (FIG. 9A); finally, a conductive material is deposited in the holes 14 and the trenches 15 to produce the connection lines 3 and the contact points 4, and the upper mask 9 is entirely removed at the end of a usual chemical-mechanical polishing in this technical and which flattens the upper surface of the integrated circuit.
- the final state is illustrated in FIG. 10, and another stage of the integrated circuit can be deposited on the lower mask 8 and the connection lines 3.
- FIG. 5B the same operations will have the effect of attacking the lower mask 8 only over part of the surface of the locations 13 ', the upper mask 9 remaining intact, and the holes 14' dug will also be of smaller cross section, as illustrated in FIGS. 7B and 9B which correspond to the preceding FIGS. 7A and 9A.
- the holes 14 ′ will have a smaller area than those 14 encountered previously, but will not extend laterally from the trenches 15 and will not widen them, which protects from short-circuits with the neighboring lines.
- the line 17 of FIG. 9B would then be the lateral limit of the etching of the masks 8 and 9 and of the substrate 1.
- the overflow of the holes which one would then undergo could be accepted if the connection lines 3 were sufficiently distant to reduce the risk of short-circuit.
- the invention makes it possible to choose between the risks of short circuit and those of circuit breaker coming from holes that the misalignment would make too fine, according to the concrete topography.
- the method can be implemented in other ways.
- the intermediate layer 7 intended to stop the digging of the trenches 15 is only optional.
- the substrate 1 can be of any suitable material, but the invention is appreciable especially for materials with low permittivity such as those which are known under the trade names of Silk and Fox.
- the upper mask 9 must be thick enough to withstand the step of etching the trenches. A thickness of around 200 nm can be proposed. As for the lower mask 8, which generally remains in the final structure of the integrated circuit, it is desirable that it has a smaller thickness, such as 40 nm.
- a more complex embodiment can be envisaged if an insulating layer 17 is deposited on the substrate 1 before the lower mask 8, which therefore covers it, as illustrated in FIG. 2A.
- the insulating layer 17 has no utility for etching the holes and the lines and serves to isolate the upper face of the stage 2 better than the lower mask 8 would do; it can be of the same composition as the upper mask 9 and fairly fine, around 50 nm.
- the lower layer 17 is etched like the lower mask 8, successively at the locations of the holes and the lines and immediately after it, as shown in FIGS. 6A and 8A. At the end of the process, the lower mask 8 is completely removed, and only one remains the lower layer 17 on the substrate 1, as illustrated in FIG. 10A.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00912726A EP1177577A1 (fr) | 1999-03-26 | 2000-03-22 | Procede de creation de lignes de connexion et de points de contact sous-jacents dans un substrat dielectrique |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR99/03819 | 1999-03-26 | ||
FR9903819A FR2791472B1 (fr) | 1999-03-26 | 1999-03-26 | Procede de creation de lignes de connexion et de points de contact sous-jacents dans un substrat dielectrique |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000059030A1 true WO2000059030A1 (fr) | 2000-10-05 |
Family
ID=9543692
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2000/000717 WO2000059030A1 (fr) | 1999-03-26 | 2000-03-22 | Procede de creation de lignes de connexion et de points de contact sous-jacents dans un substrat dielectrique |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1177577A1 (fr) |
FR (1) | FR2791472B1 (fr) |
WO (1) | WO2000059030A1 (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001015219A2 (fr) * | 1999-08-25 | 2001-03-01 | Infineon Technologies Ag | Procede de production d'un circuit integre comportant au moins un plan de metallisation |
EP1744211A1 (fr) * | 2005-07-14 | 2007-01-17 | ASML Netherlands BV | Fonds, procédé d'exposition multiple lithographique, support de machine lisible |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19723062A1 (de) * | 1996-07-13 | 1998-01-22 | Lg Semicon Co Ltd | Verfahren zum Bilden einer selbst ausgerichteten Metallverdrahtung für ein Halbleiterbauelement |
US5821169A (en) * | 1996-08-05 | 1998-10-13 | Sharp Microelectronics Technology,Inc. | Hard mask method for transferring a multi-level photoresist pattern |
US5877076A (en) * | 1997-10-14 | 1999-03-02 | Industrial Technology Research Institute | Opposed two-layered photoresist process for dual damascene patterning |
US5935762A (en) * | 1997-10-14 | 1999-08-10 | Industrial Technology Research Institute | Two-layered TSI process for dual damascene patterning |
-
1999
- 1999-03-26 FR FR9903819A patent/FR2791472B1/fr not_active Expired - Fee Related
-
2000
- 2000-03-22 EP EP00912726A patent/EP1177577A1/fr not_active Withdrawn
- 2000-03-22 WO PCT/FR2000/000717 patent/WO2000059030A1/fr not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19723062A1 (de) * | 1996-07-13 | 1998-01-22 | Lg Semicon Co Ltd | Verfahren zum Bilden einer selbst ausgerichteten Metallverdrahtung für ein Halbleiterbauelement |
US5821169A (en) * | 1996-08-05 | 1998-10-13 | Sharp Microelectronics Technology,Inc. | Hard mask method for transferring a multi-level photoresist pattern |
US5877076A (en) * | 1997-10-14 | 1999-03-02 | Industrial Technology Research Institute | Opposed two-layered photoresist process for dual damascene patterning |
US5935762A (en) * | 1997-10-14 | 1999-08-10 | Industrial Technology Research Institute | Two-layered TSI process for dual damascene patterning |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001015219A2 (fr) * | 1999-08-25 | 2001-03-01 | Infineon Technologies Ag | Procede de production d'un circuit integre comportant au moins un plan de metallisation |
WO2001015219A3 (fr) * | 1999-08-25 | 2001-07-19 | Infineon Technologies Ag | Procede de production d'un circuit integre comportant au moins un plan de metallisation |
US6930052B2 (en) | 1999-08-25 | 2005-08-16 | Infineon Technologies Ag | Method for producing an integrated circuit having at least one metalicized surface |
EP1744211A1 (fr) * | 2005-07-14 | 2007-01-17 | ASML Netherlands BV | Fonds, procédé d'exposition multiple lithographique, support de machine lisible |
Also Published As
Publication number | Publication date |
---|---|
FR2791472A1 (fr) | 2000-09-29 |
EP1177577A1 (fr) | 2002-02-06 |
FR2791472B1 (fr) | 2002-07-05 |
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