Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/764—Air gaps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
  • H01L23/64—Impedance arrangements
  • H01L23/645—Inductive arrangements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers

Definitions

• TECHNICAL FIELD This invention relates to a method of forming high quality factor passive components on silicon substrates. More specifically, the present invention relates to formation of an etch mask on a silicon substrate and use of the etch mask to provide a low dielectric constant platform in the silicon substrate.
• the present invention relates to formation of a robust, high quality dielectric layer in a silicon substrate that is compatible with formation of active components to provide RF circuitry on the silicon substrate.
• the present invention relates to formation of platforms suitable for carrying high speed digital busses.
• GaAs substrates may be made to be semi-insulating, thereby reducing or substantially eliminating parasitic substrate currents, GaAs substrates are expensive. Additionally, many GaAs devices have higher standby power requirements than do silicon devices.
• Silicon substrates are typically provided with a lightly doped epitaxial layer for formation of active components (e.g., transistors and the like).
• active components e.g., transistors and the like.
• a more heavily doped substrate is usually employed to support the epitaxial layer and to provide a low resistance ground return path for components formed in the epitaxial layer.
• a highly doped substrate aids in prevention of latch-up phenomena. While the heavily doped substrate provides a ground return path for the active circuits, it also results in reduced coil Q and losses when coils are formed on insulating layers above the substrate. As a result, silicon substrates that have been prepared for formation of active components are poorly suited to formation of high Q inductors.
• One approach to providing monolithic inductors having increased Qs is to form a thick dielectric layer on the substrate.
• the inductors require a relatively thick dielectric layer in order to be adequately isolated from the conductive substrate.
• this results in a nonplanar surface, which interferes with photolithographic processes employed for definition of other circuit elements.
• these dielectric layers tend to result in substantial stresses in the substrate, which can lead to bowing of the substrate and other problems.
• an object of the present invention to provide improvements in masking for formation of high quality, thick dielectric layers in silicon substrates.
• Another object of the present invention is the provision of an improved platform for formation of high speed digital busses on silicon substrates.
• An additional object of the instant invention is the provision of an improved method and apparatus for providing thick dielectric layers on silicon substrates while preserving planarity of the substrate surface.
• an object of the instant invention is the provision of an improved method and apparatus for providing reduction in coil losses while preserving capability for formation of active components on a silicon substrate.
• Yet still another object of the instant invention is the provision of a method for forming thick, planar, low dielectric constant, low loss dielectric layers in silicon substrates.
• a further object of the invention is to provide a method, system and apparatus for suppressing losses in monolithic inductors. And still a further object of the invention is the provision of method and apparatus, according to the foregoing, which is intended to improve operation of inductors in monolithic silicon circuits.
• a dielectric platform having a dielectric constant that is reduced below that of silicon dioxide and that is formed in a silicon substrate.
• the dielectric platform may be formed to have a depth of up to tens of microns.
• the dielectric platform may be coplanar or nearly coplanar with a surface of a silicon wafer, promoting subsequent formation of active circuitry using conventional techniques.
• high Q inductors may be realized together with conventional CMOS, bipolar or
• BiCMOS structures to form monolithic RF circuits.
• FIG. 1 is a simplified plan view of a portion of an integrated circuit including an etch mask formed on a silicon substrate, in accordance with an embodiment of the instant invention
• FIG. 2 is a simplified and enlarged plan view of a portion of the dielectric platform shown in FIG. 1, in accordance with an embodiment of the instant invention
• FIG. 3 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate at another step in processing, in accordance with an embodiment of the present invention
• FIG. 4 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate at another step in processing, in accordance with an embodiment of the present invention
• FIG. 5 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate at another step in processing, in accordance with an embodiment of the present invention
• FIG. 6 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate at another step in processing, in accordance with an embodiment of the present invention
• FIG. 7 is a simplified and enlarged side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate at another step in processing, in accordance with an embodiment of the instant invention
• FIG. 8 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate at another step in processing, in accordance with an embodiment of the instant invention
• FIG. 9 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate at another step in processing, in accordance with an embodiment of the instant invention.
• FIG. 1 illustrates a simplified plan view of an embodiment of a dielectric platform, generally designated by the reference character 12, in accordance with an embodiment of the instant invention.
• FIG. 1 is a simplified plan view of a portion of an integrated circuit showing dielectric platform 12 formed in a silicon substrate 10, in accordance with an embodiment of the instant invention.
• the substrate 10 includes one or more areas 11 that may be used to support active electrical components such as MOS and bipolar transistors, diodes, and the like. Active electronic components may be formed in the areas 11 using conventional CMOS, bipolar or BiCMOS processes.
• the dielectric platform 12 is outlined by a boundary 9 and the area 11 is outlined by a boundary 6.
• the dielectric platform 12 may be used to support passive electrical components such as interconnections, which may be formed from metals or doped polycrystalline silicon, for example.
• the dielectric platform 12 may also be used to support inductors, such as spiral inductors, or thin film resistors, such as doped polycrystalline silicon or metal resistors.
• the platform 12 may also be used to support capacitors having two conductive plates separate by an insulating dielectric.
• the conductive plates may each be formed from metal, polycrystalline silicon or metal suicides. Examples include metal-insulator- metal, poly-insulator-metal, metal silicide-insulator- metal, poly-insulator-metal suicide or poly-insulator- poly capacitors.
• dielectric platform 12 An advantage provided by the dielectric platform 12 is that passive components formed on the dielectric platform 12 have greatly reduced capacitance to the conductive silicon substrate 10. As a result, reduced amounts of electrical power are required in order to switch electrical signals in conductors and other components formed on the dielectric platform 12, such as high speed digital busses and interconnects.
• FIG. 2 is a simplified and enlarged plan view of a portion of the dielectric platform 12 shown in FIG. 1, in accordance with an embodiment of the instant invention.
• a mask 13 is formed that includes multiple openings 20.
• the openings 20 may have any shape, however, hexagonal openings 20 are shown in FIG. 2.
• the mask 13 is formed by oxidizing a portion or all of the silicon substrate 10 followed by conventional photolithography and etching.
• One or more regions 7 may also be formed in portions of the mask 13.
• the openings 20 are formed to have a width, measured along section line 8-8, of between 0.5 and 2 microns. In one embodiment, the openings 20 are formed to have a width of about 1.2 microns and are separated by about .4 microns.
• FIG. 3 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate 10 at another step in processing, in accordance with an embodiment of the present invention.
• FIG. 3 illustrates a mask layer 13 having openings 20 and cavities 21 formed by etching the silicon substrate 10 through the mask 13.
• the cavities 21 are formed by conventional anisotropic plasma etching of the silicon substrate 10 to have a depth of between 1 and ten microns. In one embodiment, the cavities are etched to have a depth of about three microns. In one embodiment, the etching is carried out using high speed anisotropic etching in a HBr/NF 3 /He-0 2 plasma.
• the mask 13 is formed by conventional oxidation of portions of the substrate 10, followed by conventional photolithography and etching, such as anisotropic plasma etching. In one embodiment, the mask 13 is formed to have a thickness of between 0.3 and 1.0 microns. In one embodiment, the mask 13 is formed to have a thickness of about 0.6 microns.
• FIG. 4 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate 10 at another step in processing, in accordance with an embodiment of the present invention.
• a conventional isotropic etch of the silicon substrate 10 has been employed to enlarge the cavities 21 and to reduce the thickness of the sidewalls separating the cavities 21.
• the sidewalls are etched to have a thickness of about .2 microns. In one embodiment, the sidewalls are etched to have a thickness of between .1 and .4 microns.
• FIG. 5 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate 10 at another step in processing, in accordance with an embodiment of the present invention.
• a conventional oxidation has been employed to oxidize all exposed silicon surfaces in the cavities 21, and the mask 13 has increased in thickness to form a mask 14.
• the oxidation has been carried out to form an oxide layer 14.
• the sidewalls have been oxidized to provide an oxide 14' having a thickness of between .01 and .2 microns. In one embodiment, the sidewalls have been oxidized to provide an oxide 14' having a thickness of about .1 micron.
• FIG. 6 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate 10 at another step in processing, in accordance with an embodiment of the present invention.
• a conventional anisotropic plasma etch is used to remove the oxide layer 14' from bottoms of the cavities 21 but not from sidewalls of the cavities 21.
• a conventional silicon etch is used to remove silicon from beneath the cavities 21 to provide one or more cavities 200.
• the silicon etch is a high speed plasma etch having predominantly anisotropic characteristics. In one embodiment, alternating between isotropic etching and anisotropic etching completes the cavity 200.
• one or more pillars 17 are formed within the cavity 200 beneath the region 7.
• the cavity 200 is formed to have a depth of between 2 and 15 microns, and the increase in width is between .2 and .7 microns. In one embodiment, the cavity 200 is formed to have a depth of about 5 microns, and the increase in width is about .5 microns. As a result of these etches, a suspended lattice 15 comprised of silicon and a silicon based dielectric is formed above the cavity 200.
• FIG. 7 is a simplified and enlarged side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate 10 at another step in processing, in accordance with an embodiment of the instant invention.
• a conventional thermal oxidation has been used to provide a silicon dioxide layer 15' on all exposed silicon surfaces and to convert the suspended lattice 18 to silicon dioxide 15.
• the openings 20 have a reduced width.
• the openings 20 have a width of about 1.16 microns and the silicon dioxide separating the openings 20 has a width of about .44 microns.
• the oxide 15' has a thickness of about .22 microns.
• the oxides 15 and 15' are conventional silicon oxynitride layers.
• FIG. 8 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate 10 at another step in processing, in accordance with an embodiment of the instant invention.
• a layer 55 has been formed to fill all or most of the openings 20.
• the layer 55 may seal the openings 20 and isolate the cavity 200 from potential contamination.
• the layer 55 may be formed using CVD or gas deposition techniques .
• a conventional TEOS process may be used to deposit an oxide layer 55. It will be appreciated that formation of the layer 55 may result in some deposition of silicon dioxide within the cavity 200, however, significant improvements in relative dielectric constant and in parasitic capacitance to the substrate may still be provided.
• Conventional TEOS processes include heating of the substrate 10 in a partial vacuum, resulting in a partial vacuum or gaseous dielectric in the cavity 200 after the TEOS layer 55 seals the openings 20.
• the oxide layer 55 has been formed to a thickness of about 1.1 microns.
• the TEOS oxide layer 55 is formed and seals the cavity 200, resulting in a continuous oxide layer 55 at and slightly beneath the surface of the silicon substrate 10, filling tops of the cavities 21 and sealing them.
• the cavity 200 includes a gaseous dielectric.
• FIG. 9 is a simplified side view, in section, taken along section lines 8-8 of FIG. 2, of a silicon substrate 10 at another step in processing, in accordance with an embodiment of the instant invention.
• a conventional chemical-mechanical polish has been used to provide planarized regions 56 on the top surface of the silicon substrate 10 and to remove some or most of the TEOS oxide layer 55 from the regions 11 that will be employed in subsequent processing to provide active electronic components, as discussed above.
• the planarized region 56 completes a dielectric platform that includes a cavity 200 in the conductive silicon substrate 10.
• the dielectric constant of the composite structure is greatly reduced compared to, e.g., what would be provided by a thick, predominantly solid dielectric layer. Additionally, reduced stress is induced in the silicon substrate 10 compared to thick dielectric layers or to dielectric layers prepared using etched trenches followed by oxidation, because the dielectric platform does not include long portions formed from oxide and does include substantial volumes that are not occupied by solids having thermal coefficients of expansion differing from that of the silicon substrate 10.
• the dielectric platform includes voids occupying in excess of 40% of the total volume prior to TEOS deposition. This results in an effective dielectric constant reduction of about 30%, from an ⁇ R of about 3.9 to an effective ⁇ R of about 2.74. In one embodiment, the dielectric platform includes voids occupying in excess of 50% of the total volume prior to TEOS deposition. This results in an effective dielectric constant reduction of about 39%, from an ⁇ R of about 3.9 to an effective ⁇ R of about 2.39. Formation of cavity 200 results in further reductions of the effective dielectric constant.
• an effective dielectric constant ⁇ R of about 1.81 is provided over a depth of about 8 microns.
• passive elements formed on top of the layer 56 of the dielectric platform 12 have sharply reduced parasitic capacitances to the substrate 10.
• Traditional integrated circuits employ relative thin (e.g., less than one micron) dielectric layers for isolation of passive components and busses from the substrate.
• the dielectric platform 12 of the present invention is capable of providing a substantially thicker dielectric. Additionally, the dielectric platform 12 may be formed to have a reduced dielectric constant relative to conventional dielectric layers.
• the effective dielectric constant of the dielectric platform 12 is reduced by both the reduced effective dielectric constant and the increased thickness.
• the effective dielectric constant for capacitance between passive components formed on the surface 56 of the dielectric platform 12 and the substrate 10 is reduced by a factor of between one and two orders of magnitude over that of conventional dielectric layers.
• parasitic capacitance to the substrate is greatly reduced and losses due to substrate resistance are also dramatically reduced.
• the amount of current needed to switch the electrical state of conductors formed on the dielectric platform 12 is also dramatically reduced, reducing power requirements for integrated circuits formed using the dielectric platform 12.
• CMOS and bipolar integrated circuits may be formed in areas adjacent to the dielectric platform 12, and these circuits may be coupled to and employ passive components such as spiral inductors, microstrip transmission lines and the like that are formed on the planar surface of the dielectric platform 12. Separating the planar surface from the silicon substrate 10 allows higher Qs to be realized for these passive components.

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• 1999
  • 1999-07-12 US US09/351,714 patent/US6307247B1/en not_active Expired - Lifetime
• 2000
  • 2000-07-11 AU AU60925/00A patent/AU6092500A/en not_active Abandoned
  • 2000-07-11 JP JP2001509086A patent/JP2003504875A/ja active Pending
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• 2001
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