GB2346259A

GB2346259A - Via connections in wafer bonded structures

Info

Publication number: GB2346259A
Application number: GB0001192A
Authority: GB
Inventors: William Graham Easter; Charles Arthur Goodwin; Muhammed Ayman Shibib
Original assignee: Lucent Technologies Inc
Current assignee: Nokia of America Corp
Priority date: 1999-01-22
Filing date: 2000-01-19
Publication date: 2000-08-02
Also published as: JP2000216367A; KR20000053544A; GB0001192D0

Abstract

The invention includes an integrated circuit device comprising a device substrate 1 having a top and bottom surface, wherein the device substrate comprises an electrically conductive via 11, wherein the electrically conductive via extends from the bottom surface to the top surface of the device substrate and wherein the walls of the electrically conductive via are separated from the device substrate by an electrical insulator 9. The integrated circuit device is bonded to a support substrate 13 and the device substrate 1 is etched back I to expose the via conductor structure.

Description

AN INTEGRATED CIRCUIT DEVICE HAVING AN INTERNAL TOP TO BOTTOM CONDUCTIVE PATH FIELD OF THE INVENTION The present invention is directed, in general, to integrated circuit devices and, more specifically, to an integrated circuit device comprising an internal top to bottom electrically conductive via.

BACKGROUND OF THE INVENTION In dielectric isolated (DI) wafer fabrication, a typically silicon handle wafer with an exposed insulating silicon dioxide layer is bonded to a device wafer, the electrically insulating silicon dioxide layer being between them. The presence of the insulating layer has advantages, especially when fabricating high voltage circuits, where it can be made as thick as desired to provide isolation. However, if electrical connection is desired between the top and bottom of a device, for example to form a ground path, fabricated from a DI wafer, it must be done external to the device. Usually, this is done by attaching the device to a case by soldering or with a conductive epoxy and bonding a wire from the case to a contact pad on the top of the device. It would be desirable to provide such an electrical connection internal to the device itself, rather than requiring an extra packaging step.

SUMMARY OF THE INVENTION The invention includes an integrated circuit device comprising a device substrate having a top and bottom surface, wherein the device substrate comprises an electrically conductive via, wherein th electrically conductive via extends from the bottom surface to the top surface of the device substrate and wherein the walls of the electrically conductive via are separated from the device substrate by an electrical insulator.

BRIEF DESCRIPTION OF THE DRAWING The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice in the semiconductor industry, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Figs. 1-6 show a cross-sectional view of an integrated circuit during various steps in accordance with an embodiment of the invention, while Fig. 6 shows a plan view.

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the invention may be understood with reference to Fig. 1, which shows in cross-section, for one embodiment of the invention, a device substrate 1, comprising a trench 3, a surface 5, initially oriented towards the"top" and a surface 7, initially oriented towards the"bottom."Fig. 2 shows that a layer of an insulator 9 is formed over the surface 5 (top) of the device substrate 1 and in the trench 3, thereby isolating a device substrate 1 by an insulator 9. An electrical conductor material 11 is then formed in the trench 3 over the electrical insulator layer 9, as shown in Fig. 3. The electrical conductor layer 11 is planarized to remove excess electrical conductor material 3 until the electrical insulator layer 9 is exposed, as shown in Fig. 4. Turning now to Fig. 5, which shows the device substrate 1 after being inverted and bonded to an electrically conductive handle substrate 13. Surface 7, formerly the"bottom", is now the top of the device wafer, and surface 7 is then planarized to expose the electrical conductor 11, as shown in Fig. 5. Conductive material 11 is now a via and Fig. 6 shows that current 15 can now flow through the resulting structure from the new top surface 7 to the handle substrate 13 of the device one surface to the other, while maintaining electrical isolation 9 between the conductive material 11 and the device wafer 1. Fig. 7 is a plan view showing a device wafer comprising a plurality of devices, each device 2 comprising conductive material 11 surrounded by electrical insulator 9, which isolates the conductive material from the device substrate 1. While Fig. 7 shows one via per device, there may be a plurality of vias in each device.

Note that while the process described above is preferred, the first planarization step is optional and may be substituted by a mask and etch to remove electrical conductor adjacent to the trench. Similarly, the bonding to a handle substrate is optional. The oxide on surface 5 may be etched off and the device substrate metallized or bonded to a case packaging surface as is.

The device substrate 1 of the present invention will generally be a semiconductor such as silicon, germanium, gallium arsenide and the like. Silicon is preferred.

Trench formation may be done by conventional masking and etching. As used herein a"trench"is a feature that does not extend all the way through a substrate, but a"trench"is not necessarily elongated and a trench may be round.

Similarly, a"via", as defined herein, provides electrical communication between two layers, but a via need not be round.

The electrical insulator materials include silicon nitride and diamond, but silicon dioxide is preferred, as silicon dioxide acts as a bonding agent to silicon.

The thickness of the silicon dioxide may range from about 0.1 to about 10 microns for high voltage work, with about 0.5 to about 1 micron being preferred. About 4 microns is preferred for 600 volt devices, For low voltages, such as 1 volt, insulator thicknesses may be as low as 1 nm on the walls of the via for isolation, but planarization limitations may require the formation of additional oxide on the surface 5 of the device wafer to achieve bonding.

Formation of silicon dioxide is conventional and techniques include thermal oxidation and plasma enhanced tetraethylorthosilicate. Bonding is conventional and details may be found in U. S. Pat. Nos. 4,878,957 and 4,883 215, both incorporated herein by reference in their entirety as if set forth in full.

The electrical conductor materials include, tungsten, copper, aluminum, doped polysilicon and the like, doped polysilicon being preferred. Formation of the electrical conductor is by conventional techniques such as chemical vapor deposition and physical vapor deposition.

Planarization may be done by chemical-mechanical polishing. Planarization of DI wafers is conventional and details may be found in U. S. Pat. No. 5,366,924, to W. G. Easter, et aL, incorporated herein by reference in its entirety as if set forth in full. Note that excess electrical conductor material adjacent to the trenches may also be removed by masking and etching.

The preferred handle substrate is silicon doped to impart conductivity.

The present invention provides a way to achieve electrical contact access from the top of a wafer or a device to the bottom of a wafer or device, in order to provide ground, for example. The technique taught is useful in any application where it is desirable to control potential (V) on the back of a device or handle substrate. For example, the present invention enables the use of the lower substrate as a control gate, allowing the creation of a complimentary metal-oxide semiconductor with a bottom gate in addition to the top gate. Additionally, the present invention may be used to simulate an induced buried layer in a bipolar device without the use of a dopant by inducing an accumulation or inversion layer by enhancing the concentration of electrons or holes. This may be done by applying a bias to the back of the substrate in an embodiment where the handle substrate is missing, or where the handle substrate is provided with conductive paths.

Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.

Claims

Claims : 1. An integrated circuit device, comprising : a device substrate having a top and bottom surface, wherein the device substrate comprises an electrically conductive via, wherein the electrically conductive via extends from the bottom surface to the top surface of the device substrate and wherein the walls of the electrically conductive via are separated from the device substrate by an electrical insulator.
2. The device of claim 1, wherein the integrated circuit device further comprises a handle substrate bonded to the device substrate.
3. The device of claim 2, wherein the handle substrate is a doped silicon wafer.
4. The device of claim 1, wherein the device substrate is a silicon wafer.
5. The device of claim 1, wherein the electrically conductive via is comprised of doped polysilicon.
6. The device of claim 1, wherein the thickness of the electrical insulator is about 0.1 to about 10 microns.
7. The device of claim 1, wherein the thickness of the electrical insulator is about 0.5 to about 4 microns.
8. An integrated circuit device, comprising : a device substrate having a top and bottom surface, wherein the device substrate comprises an electrically conductive via, wherein the electrically conductive via extends from the bottom surface to the top surface of the device substrate and wherein the walls of electrically conductive via are separated from the device substrate by an electrical insulator and wherein the device substrate is bonded to a handle substrate.
9. An integrated circuit device, comprising: a device silicon wafer having a top and bottom surface, wherein the device silicon wafer comprises a doped polysilicon via, wherein the via extends from the bottom surface to the top surface of the device silicon wafer and wherein the walls of the via are separated from the device silicon wafer by silicon dioxide and wherein the device silicon wafer is bonded to a doped silicon wafer handle.
10. A process for making an internal conductive path between the top and bottom of an integrated circuit device comprising the steps of : providing a device substrate having a top surface and a bottom surface; forming a trench in the top surface of the device substrate; forming an electrical insulator in the trench; forming an electrical conductor in the trench ; and planarizing the bottom of the device substrate to expose the conductive material.
11. The process of claim 10, further comprising the step of planarizing the top surface of the device substrate subsequent to forming the conductive material.
12. The process of claim 10, further comprising the steps of : providing a handle substrate; and bonding the top surface of the device substrate to the handle substrate prior to planarizing the bottom of the device substrate.
13. The process of claim 10, wherein the device substrate is a silicon wafer.
14. The process of claim 10, wherein the handle substrate is a doped silicon wafer.
15. The process of claim 10, wherein the electrical insulator is silicon dioxide.
16. The process of claim 10, wherein the electrical conductor is doped polysilicon.
17. The process of claim 10, wherein the thickness of the electrical insulator is about 0.1 to about 10 microns.
18. The process of claim 10, wherein the thickness of the electrical insulator is about 0.5 to about 4 microns.
19. A process for making an internal electrically isolated conductive via between the top and bottom of an integrated circuit device comprising the steps of : providing a device substrate having a top surface and a bottom surface; forming a trench in the top surface of the device substrate; forming an electrical insulator in the trench; forming an electrical conductor in the trench; planarizing the top surface of the device substrate; providing a handle substrate; bonding the top surface of the device substrate to the handle substrate; and planarizing the bottom of the device substrate to expose the conductive material.
20. A process for making an internal electrically isolated conductive via between the top and bottom of an integrated circuit device comprising the steps of : providing a device silicon wafer having a top surface and a bottom surface; forming a trench in the top surface of the device silicon wafer; forming silicon dioxide in the trench; forming doped polysilicon in the trench; planarizing the top surface of the device substrate; providing a handle silicon wafer; bonding the top surface of the device silicon wafer to the handle substrate; and planarizing the bottom of the device silicon wafer sufficient to expose the doped polysilicon.