WO2000048245A1 - Dispositifs silicium sur isolant pourvus de motifs - Google Patents

Dispositifs silicium sur isolant pourvus de motifs Download PDF

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Publication number
WO2000048245A1
WO2000048245A1 PCT/US2000/003744 US0003744W WO0048245A1 WO 2000048245 A1 WO2000048245 A1 WO 2000048245A1 US 0003744 W US0003744 W US 0003744W WO 0048245 A1 WO0048245 A1 WO 0048245A1
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WIPO (PCT)
Prior art keywords
wafer
mask
silicon
region
soi
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PCT/US2000/003744
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English (en)
Inventor
Robert P. Dolan
Michael L. Alles
Julian G. Blake
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Ibis Technology Corporation
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Publication date
Application filed by Ibis Technology Corporation filed Critical Ibis Technology Corporation
Priority to AU29936/00A priority Critical patent/AU2993600A/en
Publication of WO2000048245A1 publication Critical patent/WO2000048245A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Definitions

  • the present invention relates generally to silicon wafer processing, and more particularly, to the manufacture of silicon-on-insulator (SOI) devices.
  • SOI silicon-on-insulator
  • SOI devices silicon-on-insulator devices
  • SOI devices a thin silicon film is formed on the surface of a silicon or other semiconductor wafer and isolated from the bulk of the wafer by an insulating layer.
  • SOI devices have a number of potential advantages over conventional silicon devices (e.g., higher speed performance, higher temperature performance and increased radiation hardness).
  • the isolation electrically active semiconductor material in SOI devices tends to reduce parasitic effects such as latch-up, leakage capacitance, resistance, and radiation sensitivity.
  • Ion implantation techniques are particularly useful in forming SOI devices.
  • SIMOX single layer of a monocrystalline silicon substrate is separated from the bulk of the substrate by implanting oxygen ions into the substrate to form a buried dielectric layer.
  • This technique of "separation by implanted oxygen” (SIMOX) provides a heterostructure in which a buried silicon dioxide layer serves as a highly effective insulator for surface layer electronic devices.
  • oxygen ions typically are implanted into silicon until a predetermined dose is achieved. After implantation, the material is annealed to form the buried oxide layer or BOX region.
  • While SIMOX wafers may provide advantages over bulk silicon in many applications, there are some applications for which it would be desirable to form certain circuits with SOI and other circuits from bulk silicon.
  • microprocessors formed from SOI devices can be faster and more efficient than processors formed from bulk silicon devices.
  • other circuits, such as DRAMs may require different processing techniques, for example the formation of capacitive elements, so that bulk silicon is preferred.
  • Previous attempts to form wafers having SOI and bulk regions have achieved limited success due to relatively large defective transition regions between SOI and bulk regions.
  • the formation of SOI regions is typically accompanied by a change in wafer surface topography (i.e. the buried oxide layer causes the SOI regions to be higher than the neighboring bulk regions).
  • the high step heights over the transition regions make subsequent high resolution lithography more difficult.
  • Methods are disclosed for the formation of patterned semiconductor wafers by selective implantation of the wafer to create Silicon-on-insulator (SOI) regions and bulk regions. Device constructions based on such hybrid wafers are also disclosed. Better defined transition regions and/or smaller step heights are achieved by control of the energy and/or dose of the implanted ions.
  • a mask which is largely impervious to oxygen ion implantation at the chosen energy is used selectively shield portions of the wafer. Those regions protected by the mask remain composed of bulk silicon, while buried oxide (BOX) layers are form in the regions that are exposed to the ion beam.
  • advanced ion implantation dosage controls are utilized to allow patterning to be accomplished with thin layer (low profile) masks.
  • thin layer (low profile) masks By masking a wafer prior with a desired pattern and bombarding the wafer with an oxygen ion dose sufficient to form a continuous but relatively thin BOX region, a SOI/bulk wafer is formed having limited transition areas and relatively small step heights.
  • the limited transition areas provide more usable space on the wafer and the small step heights provide a relatively planar processing surface that is desirable for standard microlithography techniques.
  • the resulting wafer can be processed using generally conventional techniques for forming logic circuits in the SOI regions and in the bulk regions.
  • block and opaque when used herein to describe the function of the mask elements in the present invention are intended to encompass compositions that absorb or impeded the passage of oxygen ions to preclude substantial penetration of the ions into an underlying wafer and thereby prevent the formation of a buried oxide layer in the regions that are "masked.”
  • unmasked refers to regions of a wafer that either have no overlying mask or have a mask composition that does not prevent penetration of ions.
  • FIG. 1 is an schematic top view of a silicon wafer having SOI regions and bulk regions in accordance with the present invention
  • FIG. 2 is a schematic cross-sectional representation of the wafer of Figure 1;
  • FIGS. 3A - 3E illustrate a set of processing steps according to the invention.
  • Fig. 3A is a cross-sectional view of a silicon wafer prior to processing according to the invention.
  • FIG 3B shows an initial step of depositing a resist
  • the resist is lithographically patterned
  • FIG. 3D a portion of the resist is removed
  • the wafer is selectively implanted with oxygen ions to form a SOI region
  • FIG. 4 is another cross-sectional view of a hybrid SOI/bulk silicon structure formed by SIMOX processing
  • FIG. 5 is a cross-section view of a hybrid SOI/bulk silicon structure in which the SOI region has be separated from the bulk region by trench etching;
  • FIG. 6 is a cross-sectional view of another hybrid SOI/bulk silicon structure in which the step height over the transition region has been reduced by a modified implantation protocol that provides a thinner BOX region;
  • FIG.7 is a cross-sectional schematic representation of an illustrative electronic device formed in an SOI region
  • FIGS. 8 is a schematic representation of a patterned SOI/bulk wafer having logic circuits disposed thereon in accordance with the present invention.
  • FIGS. 9A - 9C illustrate the effects of implantation of a mask-patterned wafer at an angle;
  • the wafer is selectively implanted with oxygen ions to form a SOI region;
  • FIG.9B is a cross-sectional schematic representation of the resulting BOX region if the wafer is rotated in the course of implantation;
  • FIG.9C is a cross-sectional schematic representation of the resulting BOX region if the wafer is not rotated;
  • FIGS. 10A - 10D illustrate the manufacture of micromachine structures in SOI/bulk silicon wafers by implantation of a mask-patterned wafer at an angle, followed by etching;
  • the wafer is selectively implanted with oxygen ions using a masking having shaped sidewalls;
  • FIG. 10B is a cross-sectional schematic representation of the resulting
  • FIG. 10C illustrated an initial etching step whereby a portion of the BOX region is exposed at the surface; and in FIG. 10D the oxide is removed by further oxide- selective etching to form a lever structure in the silicon surface layer.
  • the thin film layer structure of SIMOX SOI devices can be fabricated by a high current, high energy implantation of oxygen ions for the creation of a buried oxide layer below about 50 nm to about 2100 nm of silicon.
  • the oxygen ion implantation process is followed by high temperature annealing to form well delineated interfaces and very pure crystallinity.
  • the invention is preferable practiced with an ion implantation system, such as the
  • the IBIS 1000 machine comprises an ion source, a mass analyzer, an accelerator column, a scanner magnet, a neutral filter magnet, and a collimator magnet.
  • the system is capable of delivering up to about 70 mA of O + from about 70 keV to about 210 keV while maintaining a parallel beam scan across 200 mm wafers.
  • the system uses a microwave ECR ion source operating at 2.45 Ghz, for example, to produce up to 70 mA of O ⁇ ions through a 40 mm high by 3 mm wide aperture.
  • the microwave generator is a 1000 watt magnetron coupled to the source through rectangular WRJ84 waveguide components and a vacuum isolating dielectric window.
  • the source magnetic field is produced by three independent solenoids mounted coaxially with the plasma chamber.
  • the source extraction electrode is adjustable with three degrees of freedom (gap, sideways, and tilt) through a manipulator mounted external to the vacuum chamber with the motions coupled through welded bellows.
  • Wafers are implanted in batches using a 'spinning disk' end station.
  • the end station can encompass a disk containing 13 product 200mm wafers located in the target chamber as shown in Figure 3.
  • the disk can spin, for example, at about 105 rpm to ensure doping uniformity along the wafer circumference.
  • Uniform doping in the radial direction is achieved by high speed (150 Hz) parallel scanning of the beam.
  • the combination of "mechanical” scan and “beam” scan eliminates the need to mechanically translate the disk as it spins.
  • the use of a fixed rotation axis greatly reduces the mechanical complexity of the target chamber with a corresponding improvement in reliability and serviceability.
  • the wafers can be heated to temperatures in the range of about 20-600 °C by an array of quartz halogen lamps facing the spinning disc.
  • FIGS. 1 and 2 show a silicon wafer 200 having SOI regions 202 A and 202B and bulk regions 204A and 204B in accordance with the present invention.
  • the SOI regions 202 include a silicon layer 16 and a buried silicon dioxide layer or BOX region 14, which is disposed on the single crystal silicon substrate 12.
  • the bulk regions 204 are formed from bulk silicon.
  • a wafer is apportioned between SOI and bulk regions 202, 204, i.e., selectively isolated, by implanting oxygen into selected areas of the wafer using a patterned mask that blocks the ion beam.
  • the wafers can be treated with a reduced ion implantation dose to achieve desirable geometries and to minimize transition areas.
  • full dose SIMOX processing corresponds to a BOX region thickness of about 400 nm.
  • the SOI/bulk wafer 200 has a transition region 212 at each boundary of the SOI and bulk regions 202, 204. In some applications, it can be desirable to form trenches in the transition regions 212 to improve isolation between the SOI regions 202 and bulk regions 204.
  • FIGS 3A -3E A manufacturing process according to the invention is shown in FIGS 3A -3E.
  • a mask is applied to the wafer as shown in FIG. 3B prior to SIMOX processing to provide SOI and bulk regions.
  • the mask should be formed from materials that are opaque to oxygen ion bombardment so as to keep the covered bulk silicon regions pristine.
  • the mask material should not contaminate the silicon layer on the wafer.
  • the mask material is preferably able to withstand the relatively high annealing temperatures and/or the elevated implantation temperatures.
  • Exemplary suitable materials for the mask include oxide materials, such as silicon dioxide and silicon nitride, using deposition and/or thermal growth techniques. Polysilicon mask materials may also be used.
  • vapor deposition techniques can be employed using, for example, tetraethoxysilane (TEOS) as a precursor gas for depositing silicon oxide on the wafer.
  • TEOS tetraethoxysilane
  • thermal growth processes can be used whereby the wafer is heated in the presence of oxygen to form a silicon dioxide on the wafer.
  • the wafers can be heated to temperatures in the range from about 900 degrees Celsius to about 1200 degrees Celsius for a duration of between about 0.5 hour to several hours. It is understood that the temperature influences the oxidation rate, and thus, the time required to form an oxide layer of desired thickness.
  • the thickness of the mask should be minimized in order to block the least amount of ions from reaching the exposed areas of the wafer. That is, with respect to the incoming ion beam, shadows on the targeted wafer regions due to the mask should be minimized.
  • a relatively thin mask thereby helps to minimize the area of the transition regions.
  • One particularly advantageous use of thinner masks is in conjunction with slanted ion implantation.
  • the thickness of the mask is directly related to the degree of "shadowing" that will occur. Shadowing effects acerbate transition region discontinuities.
  • the thickness of the masks useful in the present invention will typically range from about 0.05 micrometers to about 10 micrometers, more preferably, from about 0J micrometers to about 5 micrometers, and most preferably from about 0J micrometers to about 2.0 micrometers. It is understood that the necessary thickness of the mask is determined by the energy level of the oxygen ions. More particularly, higher energy levels for the ions require thicker masks.
  • a thermal oxide mask of at least 0.9 micrometers is required to stop oxygen ions at greater that 200 keV.
  • An oxide mask of about 0.6 micrometers or more is needed to stop ions at 180 keV and lesser mask thicknesses are necessary to stop ions having energies lower that about 150 keV.
  • the oxide mask is patterned and etched.
  • a photosensitive polymer mask is applied over the oxide layer and patterned using lithographic techniques well known to one of ordinary skill in the art as shown schematically in FIG. 3C.
  • the patterned polymer layer can then be plasma etched with a CF 4 type plasma etcher for example, and the remaining polymer can then be removed to provide a wafer having exposed portions and portions covered with the oxide layer as shown in FIG.
  • An implantation system is used to process the wafer, as shown in FIG. 3E, to achieve a desired pattern of SOI and bulk regions on the wafer, which correspond to the exposed and oxide covered portions of the wafer, respectively.
  • the wafer can be bombarded with oxygen ions having a predetermined energy, or range of energies, to achieve a desired dose level for the SIMOX wafer.
  • oxygen ions having a predetermined energy, or range of energies, to achieve a desired dose level for the SIMOX wafer.
  • U.S. Patent Nos. 5,288,650, (Sandow) and 5,196,355 (Wittkower) describe exemplary SIMOX processing techniques.
  • the dose level determines the thickness of the BOX region.
  • the transition region 212 is unusable when forming logic circuits on the top silicon layer 206.
  • a step height h, of the transition region 212 is measured from the surfaces of the SOI regions 202 and the bulk regions 204.
  • the dose applied to the wafer can be less than so-called "full dose” to provide a thinner BOX region and thereby minimize step heights and transition areas.
  • a full oxygen dose corresponds to a BOX region thickness, d, of about 400 nm.lt should be apparent that the step height h, is dependent on the BOX region thickness d,.
  • a wafer 300 having a SOI region 302 and a bulk region 304 is processed to remove the transition region so as to form a step 308.
  • the step 308 has a height H' in the range from about 0J micrometers to about 0.6 micrometers.
  • the present invention can utilize advanced ion implantation dosage controls to allow patterning to be accomplished with thin layer (low profile) masks.
  • thin layer (low profile) masks By masking a wafer prior with a desired pattern and bombarding the wafer with less than a full oxygen ion dose to form a relatively thin BOX region, a SOI/bulk wafer is formed having limited transition areas and relatively small step heights.
  • doses of less than about 1 x 10 18 O7cm 2 are applied to the wafer at energy levels that can range from about 50 keV to about 190 keV.
  • a wafer having a BOX region about 50 nm in thickness corresponds to a dose of about 1-2 x 10 17 O cm 2 .
  • the lower energies levels also permit the use of thinner masks.
  • BOX region thickness d 2 yields a smaller step height, h 2 .
  • the limited transition areas provide more usable space on the wafer and the small step heights provide a relatively planar processing surface that is desirable for standard microlithography techniques.
  • the resulting wafer can be processed using generally conventional techniques for forming logic circuits in the SOI regions and in the bulk regions.
  • the BOX region 208 preferably has a thickness in the range from about 50 nm to about 350 nm. In an exemplary embodiment, the BOX thickness is about 170 nm.
  • the transition region 212 has a width that is less than about two micrometers and the step height h is preferably less than about 0J micrometers. Again in an exemplary embodiment, the step height can be 0.06 micrometers.
  • Exemplary devices include SOI logic and bulk power devices for smart power circuits, patterned buried oxide etch stops for MEMs structures, and
  • Another illustrative device includes a CMOS SOI logic circuit and a bulk silicon CCD camera.
  • FIG. 7 shown an illustrative device 70 formed on a silicon surface layer 16 of a SOI wafer.
  • the buried oxide layer 14 provided electrical isolation of a MOSFET device from the bulk substrate.
  • a junction 73 is formed between a doped source region 72 and a similarly doped drain region 74.
  • a gate oxide 76 separates the gate electrode 78 from the junction 73.
  • the gate electrode is sufficiently proximal to the junction to induce current flow from source to drain when an appropriate voltage is applied to the gate electrode.
  • FIG. 8 is a schematic illustration of an exemplary device 400 utilizing the hybrid constructions of the present invention.
  • Device 400 includes a processor 402 and an SRAM 404 formed in SOI region 406 and DRAM memories 408A and 408B formed in a bulk region
  • FIGS. 9A - 9C illustrate the effects of implantation of a mask-patterned wafer at an angle.
  • a mask 18 is deposited of a wafer 12 and patterned to create openings (or regions of limited resistance to the ion beam 20.
  • wafer 12 is selectively implanted with oxygen ions at a non-perpendicular angle to form a SOI region.
  • One of the effects of the ion beam is the "rounding off of the upper edge 18A and the undercutting of lower edge 18B of the sidewalls of the resist where a pattern has been selectively removed.
  • FIG. 9B is a cross-sectional schematic representation of the resulting BOX region if the wafer is rotated in the course of implantation (e.g. following one half of the implantation dose) while FIG. 9C is a cross-sectional schematic representation of the resulting BOX region if the wafer is not rotated.
  • FIGS. 10A - 10D illustrate how asymmetric BOX formation can be used in the manufacture of micromachine structures in SOI/bulk silicon wafers by implantation of a mask-patterned wafer at an angle, followed by etching.
  • the wafer is selectively implanted with oxygen ions using a mask having shaped sidewalls.
  • FIG. 10B is a cross- sectional schematic representation of the resulting BOX region 14.
  • FIG. 10C illustrates an initial etching step (e.g., plasma etching) whereby a portion of the BOX region 40 is exposed at the surface.
  • the oxide is removed by further oxide-selective etching (e.g., hydrofluoric acid) to create a subsurface cavity 44 and form a lever structure 46 in the silicon surface layer.
  • oxide-selective etching e.g., hydrofluoric acid

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

L'invention concerne des procédés permettant de former des plaquettes de semi-conducteurs pourvues de motifs par implantation sélective des plaquettes afin de créer des zones silicium sur isolant (SOI) et régions non épitaxiées. L'invention concerne des constructions du dispositif fondées sur ce type de plaquettes hybrides. La régulation de l'énergie et/ou des doses d'ions implantés permettent de réaliser des régions de transition mieux définies et/ou des hauteurs de palier réduites. Un masque qui est largement imperméable à l'implantation d'ions d'oxygène au niveau d'énergie choisi permet de protéger de manière sélective des parties de la plaquette. Les régions protégées par le masque restent composées de silicium non épitaxié, tandis que les couches d'oxyde enterrées (BOX) se forment sur les régions exposées au faisceau ionique.
PCT/US2000/003744 1999-02-12 2000-02-14 Dispositifs silicium sur isolant pourvus de motifs WO2000048245A1 (fr)

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AU29936/00A AU2993600A (en) 1999-02-12 2000-02-14 Patterned silicon-on-insulator devices

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US11971699P 1999-02-12 1999-02-12
US60/119,716 1999-02-12

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Cited By (8)

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WO2003083934A1 (fr) * 2002-03-28 2003-10-09 Advanced Micro Devices, Inc. Dispositif a semi-conducteur forme sur une couche d'oxyde enterree a epaisseurs multiples, et procedes de fabrication correspondants
EP1487010A2 (fr) * 2003-06-13 2004-12-15 Siltronic AG Substrat SOI, substrat semi-conducteur et son procédé de fabrication
US6955971B2 (en) 2002-11-12 2005-10-18 S.O.I.Tec Silicon On Insulator Technologies S.A. Semiconductor structure and methods for fabricating same
CN100342539C (zh) * 2001-09-27 2007-10-10 株式会社东芝 半导体装置和半导体装置的制造方法
EP1875516A2 (fr) * 2005-04-15 2008-01-09 International Business Machines Corporation Cellule-soi 6t-sram de substrat hybride pour une stabilite et une performance de cellule amelioree
GB2494231A (en) * 2011-08-31 2013-03-06 Ibm On-chip radiation dosimeter
US8703516B2 (en) 2008-07-15 2014-04-22 Infineon Technologies Ag MEMS substrates, devices, and methods of manufacture thereof
DE102017212437B3 (de) 2017-07-20 2018-12-20 Infineon Technologies Ag Verfahren zum Herstellen einer vergrabenen Hohlraumstruktur

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US6737332B1 (en) 2002-03-28 2004-05-18 Advanced Micro Devices, Inc. Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same
CN1310306C (zh) * 2002-03-28 2007-04-11 先进微装置公司 形成于多厚度埋入氧化层上的半导体装置以及制造此半导体装置的方法
WO2003083934A1 (fr) * 2002-03-28 2003-10-09 Advanced Micro Devices, Inc. Dispositif a semi-conducteur forme sur une couche d'oxyde enterree a epaisseurs multiples, et procedes de fabrication correspondants
US6955971B2 (en) 2002-11-12 2005-10-18 S.O.I.Tec Silicon On Insulator Technologies S.A. Semiconductor structure and methods for fabricating same
US7320925B2 (en) 2003-06-13 2008-01-22 Siltronic Ag SOI substrate, semiconductor substrate, and method for production thereof
EP1487010A2 (fr) * 2003-06-13 2004-12-15 Siltronic AG Substrat SOI, substrat semi-conducteur et son procédé de fabrication
EP1487010A3 (fr) * 2003-06-13 2005-03-16 Siltronic AG Substrat SOI, substrat semi-conducteur et son procédé de fabrication
CN1315175C (zh) * 2003-06-13 2007-05-09 硅电子股份公司 硅绝缘体基片的制造方法
EP1875516A2 (fr) * 2005-04-15 2008-01-09 International Business Machines Corporation Cellule-soi 6t-sram de substrat hybride pour une stabilite et une performance de cellule amelioree
EP1875516A4 (fr) * 2005-04-15 2008-08-13 Ibm Cellule-soi 6t-sram de substrat hybride pour une stabilite et une performance de cellule amelioree
US8703516B2 (en) 2008-07-15 2014-04-22 Infineon Technologies Ag MEMS substrates, devices, and methods of manufacture thereof
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US10784147B2 (en) 2017-07-20 2020-09-22 Infineon Technologies Ag Method for producing a buried cavity structure

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