WO2000019526A1 - Cellule d'accumulation a semi-conducteur et procede d'accumulation de ladite cellule - Google Patents

Cellule d'accumulation a semi-conducteur et procede d'accumulation de ladite cellule Download PDF

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Publication number
WO2000019526A1
WO2000019526A1 PCT/DE1999/002760 DE9902760W WO0019526A1 WO 2000019526 A1 WO2000019526 A1 WO 2000019526A1 DE 9902760 W DE9902760 W DE 9902760W WO 0019526 A1 WO0019526 A1 WO 0019526A1
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WO
WIPO (PCT)
Prior art keywords
layer
wiring
electrode
conductive
semiconductor component
Prior art date
Application number
PCT/DE1999/002760
Other languages
German (de)
English (en)
Inventor
Carlos Mazure-Espejo
Thomas RÖHR
Christine Dehm
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO2000019526A1 publication Critical patent/WO2000019526A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Definitions

  • the invention is in the field of semiconductor technology and relates to a semiconductor component with at least one storage capacitor, which comprises a first electrode, a second electrode and an oxide ceramic "capacitor dielectric arranged between the first electrode and the second electrode, with further components, and with one electrically conductive wiring for connecting the further components, and a method for producing such a semiconductor component, which are separate from the first and second electrodes.
  • the increase in the integration density and the circuit complexity in integrated circuits is associated with complex wiring of the individual components by means of several wiring levels.
  • the individual wiring levels generally consist of metal layers structured in the form of conductor tracks, which are insulated from one another.
  • the individual wiring levels are from below, i.e. starting from the component level, numbered upwards.
  • a semiconductor component mentioned at the outset is disclosed, for example, in the technical article “High-K Dielectric Materials for DRAM Capacitors” in Semiconductor International, 11, 1996, pages 109 to 116.
  • the semiconductor component described therein essentially consists of a large number of
  • Memory cells each individual memory cell being formed by a MOSFET transistor and a storage capacitor in a so-called stack configuration.
  • the storage capacitor is located on an insulation layer above the source region of a MOSFET transistor.
  • an electrode of the storage capacitor is connected to the source region.
  • the gate of the transistor is driven via the so-called word line, the transistor is switched to pass, whereby the charge stored in the storage capacitor can flow through the now open transistor.
  • the wiring of the individual memory cells as well as other components is made over several separate and complex wiring levels.
  • This object is achieved by a semiconductor component of the type mentioned in the introduction in that at least one of the two electrodes and the wiring consist of the same material.
  • the semiconductor component according to the invention can e.g. at least one wiring level in the form of a further metal layer can be saved. This is achieved in that, on the one hand, the entire surface of the deposited layer is used to form the electrode necessary for the construction of a memory cell and, on the other hand, a wiring in the form of an additional conductor track for contacting further components.
  • the layer deposited over the entire surface is suitably structured, an electrode of the storage capacitor and the wiring being formed. Standard lithography processes are preferably used to form the electrode and the wiring.
  • a further, for example a second, wiring can advantageously also be formed from a further layer which is used to produce a second electrode of the memory cell.
  • the wiring created is used, for example, for the electrical connection of individual components arranged on the semiconductor component to one another.
  • the wiring can also produce a conductive connection to a further conductive layer, which in turn can consist of a metal or a metal alloy, but also of a doped semiconductor or silicon.
  • Wiring density can be used as an additional wiring level to the commonly used wiring levels without additional material and without an increase in the number of process steps, as a result of which greater flexibility in the configuration of all contacts on the semiconductor component can be achieved.
  • An advantageous embodiment of the invention is characterized in that at least one of the two electrodes and the wiring have been created by structuring a jointly deposited layer.
  • the common layer After the common layer has been deposited in a process step, it is subsequently structured in an etching process in order to form one of the two electrodes and the wiring.
  • the material expenditure is reduced, since the invention makes it possible to dispense with the application of a further metal layer serving as a wiring level.
  • the uniform process steps also simplify subsequent structuring and the deposition of additional layers.
  • the wiring is already arranged in the immediate vicinity above the components. Associated with this is a reduction in the etching depth necessary to create contact holes for connecting the components to the wiring. Furthermore, the overall height of the semiconductor component is reduced, as a result of which its properties with regard to dissipation of power loss are significantly improved.
  • a further advantageous embodiment of the invention is characterized in that the further components are arranged in a memory cell array of the semiconductor component having a plurality of storage capacitors or on its periphery.
  • At least one contact hole filled with conductive material is provided in the substrate below the wiring, which extends from the wiring to at least one of the further components.
  • Local wiring in particular can advantageously be produced from the jointly deposited layer.
  • the wiring is outstandingly suitable for connecting individual memory cells or their selection transistors to one another.
  • the electrical connection between the wiring, which is arranged, for example, in a first level on the semiconductor component, and others Layers or further components which are arranged in a second level on the semiconductor component are advantageously achieved in that at least one contact hole filled with conductive material is provided in an insulation layer separating the two levels.
  • the electrical contact between the wiring and the further layer or the components can, however, also be produced after the insulation layer has been suitably structured by direct contact of the wiring with the further layer or the components.
  • the wiring can preferably also be used for contacting components which are located on the periphery of the semiconductor component and which control individual memory cells. Control and amplifier components are usually integrated into the semiconductor component at the periphery.
  • the wiring is global, i.e. it serves for the electrical connection of components arranged at a distance from one another.
  • the memory cells can also be arranged peripherally.
  • an insulation layer arranged above the wiring can be provided on the semiconductor component, in which at least one contact hole filled with a conductive material is arranged, which extends to the wiring.
  • a further advantageous embodiment of the invention is characterized in that the capacitor dielectric consists of barium strontium titanate, strontium bismuth tantalate, niobium-doped strontium bismuth tantalate or lead zirconium titanate.
  • the capacitor dielectric consists of barium strontium titanate, strontium bismuth tantalate, niobium-doped strontium bismuth tantalate or lead zirconium titanate.
  • Another advantageous embodiment of the invention is characterized in that at least one of the two electrodes and the wiring consist of platinum, iridium, palladium, ruthenium, a conductive oxide of the aforementioned metals or an alloy of at least one of the aforementioned metals and oxides.
  • Electrode materials are advantageously used in the production of memory cells which, as a capacitor dielectric, have ceramic materials with a high dielectric constant, e.g. B. barium strontium titanate, or ferroelectric ceramic materials, e.g. B. from strontium bismuth tantalate or niobium-doped strontium bismuth tantalate.
  • the electrodes of such memory cells are predominantly made of platinum, iridium or ruthenium. Due to their low electrical resistance, these metals can be used simultaneously for wiring different components.
  • the use of other less reactive metals or oxides, such as. B. palladium, iridium oxide or ruthenium oxide is also possible.
  • At least one of the two electrodes is made up of two conductive layers, one of the two conductive layers being arranged on the side facing the capacitor dielectric and made of platinum, iridium, palladium, ruthenium, a conductive oxide mentioned above Metals or an alloy of at least one of the aforementioned metals and oxides.
  • the first conductive layer facing the capacitor dielectric consists of a less reactive material for protecting the sensitive capacitor dielectric.
  • the material thickness to save material the first conductive layer can be kept relatively thin, ie thinner than the actual thickness of the electrode. At the same time, this leads to a structurally true etching of the first conductive layer and of the capacitor dielectric.
  • the second conductive layer facing away from the capacitor dielectric forms an electrode together with the first conductive layer. It is advantageous that the second conductive layer and the wiring are made from a jointly deposited layer.
  • Preferred materials for the second conductive layer and the wiring are platinum, iridium, palladium, ruthenium, aluminum, copper, tungsten, conductive oxides of the aforementioned metals or an alloy of at least one of the aforementioned metals and oxides.
  • metal silicides of a metal M, conductive metal nitrides of a metal M or conductive ternary compound are also found
  • MBN use, where N for nitrogen, M for a metal from the group titanium, tungsten, cobalt, tantalum, molybdenum, copper, platinum, rhodium and aluminum and B for a metal from the
  • the substrate is provided, in which, for example, individual components or parts thereof are already integrated.
  • the first layer is then deposited and structured to form the first electrode. Suitable deposition processes are, for example, CVD (chemical vapor deposition) or sputtering processes.
  • an oxide ceramic layer and a second layer are applied to the substrate and structured.
  • the oxide ceramic layer and the second layer can be structured in succession or together. If a separate structuring is desired, this is done before the second layer is said goodbye.
  • the result is the capacitor dielectric from the oxide ceramic layer and the second electrode from the second layer.
  • the wiring is formed from the respective layers simultaneously or in a separate step. The wiring has no direct contact with the individual electrodes.
  • the manufacturing method is advantageously characterized in that the wiring and the first and / or second electrode are created in a common etching process.
  • the above-mentioned object is also achieved by a method for producing a semiconductor component with the following steps: Provision of a substrate,
  • Components is formed on the substrate.
  • an electrode is formed by two conductive layers deposited one after the other.
  • the first conductive layer is applied conformally to the oxide ceramic layer and protects it during further structuring.
  • the first conductive layer is then etched together with the oxide ceramic layer.
  • the first conductive layer protects the regions of the oxide ceramic layer remaining on the substrate from attack by the etching.
  • This is followed by the application of the second conductive layer, from which an electrode and also the wiring are formed together with the first conductive layer in the region of the capacitor dielectric.
  • the production processes according to the invention are furthermore advantageously characterized in that the first layer is deposited on the substrate with the interposition of an adhesion-promoting and / or barrier layer.
  • Barrier layers prevent the diffusion of silicon or other materials to the capacitor dielectric and thus ensure constant material properties.
  • the production methods according to the invention are furthermore advantageously characterized in that, in the area of the wiring, at least one contact hole is created in the substrate and filled with a conductive material before the first layer is applied, or that an insulation layer is applied to the wiring and subsequently at least one to one for the wiring reaching and filled with conductive material contact hole is created in the insulation layer.
  • Figure 1 shows a semiconductor device according to the invention with a first variant for contacting the
  • FIG. 2 shows a semiconductor component according to the invention with a further variant for contacting the wiring
  • FIG. 3 shows a semiconductor component according to the invention with a multilayer electrode
  • FIG. 4 shows a plan view of a memory cell array of a semiconductor component according to the invention
  • FIGS. 5a to 5e individual process steps for producing a semiconductor component according to the invention
  • FIGS. 6a to 6e production steps for producing a semiconductor component according to the invention with a multilayer electrode
  • Figures 7 and 8 further variants for contacting the wiring.
  • the semiconductor component 1 shown in FIG. 1 has a silicon base body 2 and an insulation layer 3 arranged above it.
  • the first electrode 10, which is lower in this exemplary embodiment, is cylindrical or guader-shaped and sits on a barrier layer 25 made of titanium nitride and titanium. This barrier layer 25 separates the lower electrode 10 from the insulation layer 3 and a contact hole 30 filled with polysilicon, which leads from the lower electrode 10 through the insulation layer 3 to a source region 40 of a selection transistor 45.
  • the barrier layer 25 on the one hand prevents the diffusion of silicon through the lower electrode 10 to the capacitor dielectric 15 and on the other hand prevents the electrode material of the lower electrode 10 from diffusing through the contact hole 30 to the source region 40 of the selection transistor 45.
  • Palladium, platinum, iridium, ruthenium, iridium oxide or ruthenium oxide are preferably used as the electrode material for the lower electrode.
  • the capacitor dielectric 15 and the second, in this exemplary embodiment upper electrode 20 are arranged both on the lower electrode 10 and on the side walls thereof. This increases the area of the storage capacitor 5 that can be used for storage.
  • the selection transistor 45 Via the selection transistor 45, charges can be brought into the storage capacitor 5 as well as read out from it.
  • the selection transistor 45 also has a so-called drain region 50 objected to by the latter. Both regions 40 and 50 are created in the silicon base body 2 by means of ion implantation.
  • a gate oxide 60 with a seated gate electrode 65 is arranged on the silicon base body 2 between the source region 40 and the drain region 50.
  • the gate electrode 65 is preferably formed by a doped polysilicon layer running perpendicular to the plane of the drawing. The selection transistor 45 is driven via this.
  • the drain region 50 is connected to a wiring 75 via a further contact hole 70 in the insulation layer 3 filled with polysilicon.
  • This wiring 75 consists of the same electrode material as the lower electrode 10. Both the lower electrode 10 and the wiring 75 were produced from one and the same deposited layer in the production of the semiconductor component. Therefore, there is also a barrier layer 80 below the wiring 75, which was formed together with the barrier layer 25 below the first electrode 10.
  • the wiring 75 is both opposite the lower electrode 10 and also insulated from the upper electrode 20. This prevents accidental drainage of the charge stored in the storage capacitor 5.
  • the wiring 75 connects the selection transistor 45 as a further component 45, for example to amplifier devices arranged on the periphery of the semiconductor component.
  • Another wiring 90 is also arranged on the insulation layer 3. This wiring 90 was created together with the upper electrode 20 during the production of the semiconductor component 1. Depending on the process, the oxide ceramic layer 95 from which the capacitor dielectric 15 was formed is arranged below the wiring 90.
  • the storage capacitor 5 and the wirings 75 and 90 are completely covered with a planarizing layer 100, which consists, for example, of thermal silicon dioxide, BPSG (boron-phosphorus-silicate glass) or TEOS (tetra-ethyl-ortho-silicate). Contact holes 105 and 110 are led through the planarizing layer 100 as far as the wiring 90 and up to the upper electrode 20.
  • These contact holes 105 and 110 connect the wiring 90 and the upper electrode 20 to the so-called metal layer 1 (metal 1), which is designed in the form of conductor tracks 115 and 120.
  • the conductor tracks 115 and 120 consist predominantly of aluminum or an aluminum-copper alloy. If the wiring 75 or 90 is already implemented as a metal layer 1, i.e. this already takes over local or global wiring function, so the conductor tracks 115 and 120 already represent the metal layer 2 (metal 2).
  • FIG 2 further contact variants of the wiring 75 and 90 are shown.
  • a variant consists in direct contact between the wiring 75 and 90.
  • the oxide ceramic layer 95 was selectively removed in the desired contact area 125, so that the upper electrode material material is deposited directly onto the already deposited lower electrode material from which the wiring 75 originated. If the oxide ceramic layer 95 is removed from a further contact area 130 beforehand, the subsequently deposited upper electrode material can also be applied directly to a filled contact hole 135. This also makes it possible to contact the wiring 90 downward through the insulation layer 3.
  • the upper electrode 150 of the storage capacitor 5 consists of a first conductive layer 155 and a second conductive layer 160.
  • the first conductive layer 155 preferably consists of the same electrode material that is also used for producing the lower electrode 10, for example platinum, Iridium, palladium, ruthenium or a conductive oxide of the aforementioned metals. It is also possible to use alloys made from one of the aforementioned metals and oxides.
  • the first conductive layer 155 is made relatively thin since it essentially serves to protect the capacitor dielectric 15.
  • the first conductive layer 155 and the capacitor dielectric 15 are etched together, so that both the capacitor dielectric 15 and the first conductive layer are removed from all regions which were not previously masked.
  • the second conductive layer 160 is applied to the first conductive layer 155 and suitably structured.
  • the first and second conductive layers 155 and 160 thereby together form the upper electrode 150.
  • a wiring 165 is produced from the second conductive layer 160.
  • the materials used for the second conductive layer 160 can correspond to those used for the first conductive layer 155. chen. However, it is cheaper to dispense with these relatively expensive materials and to resort to less expensive and easier to handle materials such as polysilicon, metal silicides or conductive metal nitrides or ternary nitride compounds.
  • FIG. 1 a top view of a semiconductor component 1 is shown in FIG.
  • the individual storage capacitors 5 are arranged in a matrix-like manner in a memory cell array 180.
  • a selection transistor 45 is assigned to each storage capacitor 5.
  • the drain regions, not shown here, of each selection transistor 45 are connected to a strip-shaped wiring 190, which leads to an amplifier element 192 on the periphery 195 of the memory cell array 180.
  • This periphery 195 can also be arranged on the edge of the semiconductor component 1. Due to the wiring shown in Figures 1 to 4, both a local connection of the other components, e.g. of selection transistors 45, as well as a global connection of the other components to one another.
  • the further components also include the amplifier elements 192 and further assemblies, not shown, on the semiconductor component 1.
  • a substrate 3 that corresponds to the insulation layer 3 is assumed. Contact holes 30 and 70 have already been made in this substrate 3.
  • a barrier layer 200 is first applied to the substrate 3, followed by a first layer 205 of an electrode material.
  • the barrier layer 200 which is made of titanium nitride / titanium, for example, is preferably produced by a CVD process, the first layer 205 is preferably produced by a sputtering process. applied.
  • the two layers 200 and 205 are structured using a suitable lithography process. On the one hand, this creates the first and lower electrodes 10, which are separated from the substrate 3 by the likewise structured barrier layer 25. Simultaneously with the formation of the lower electrode 10, a wiring 75 with a barrier layer 80 arranged underneath was created.
  • a lacquer layer is first applied to the first layer 205 and then structured using photo technology. Depending on the use of a positive or a negative photoresist, the exposed or unexposed areas are chemically activated and can subsequently be removed in one development step. Finally, the lacquer mask produced in this way is used to structure the barrier layer 200 and the first layer 205 by means of suitable etching processes. After the lithography process, a cleaning step may follow
  • an oxide-ceramic layer is now applied conformally to the substrate 3, to the first electrode 10 and to the wiring 75.
  • the preferred method for this is an MOCVD process in which the individual constituents of the oxide ceramic are applied via an oxidizing precursor gas.
  • a second layer 215 is then applied to the oxide ceramic layer 210.
  • the second electrode 20 and the capacitor dielectric 15 are also formed from this by means of suitable lithography methods. In this method step, the simultaneous formation of a wiring 90 is also possible.
  • the oxide-ceramic layer 210 can be suitably structured before the second layer 215 is deposited, so that only the capacitor dielectric 15 of the oxide-ceramic layer remains in the area of the storage capacitor 5 on the substrate 3 and the first electrode 10, in the remaining areas of the semiconductor device 1, however, is completely removed.
  • the second layer 215 is in direct contact with the substrate 3 or with contact holes arranged therein or with already formed wirings, which are shown for example in FIG. 2.
  • a BPSG layer 220 is deposited on the storage capacitor 5 formed and on the wirings 75 and 90, in which a contact hole 225 is subsequently formed.
  • This contact hole 225 leads, for example, to the wiring 90 and connects it to a metallization layer 230 applied to the BPSG layer 220.
  • FIG. 6a To describe the manufacturing steps of a semiconductor component with a multilayer electrode, a structure according to FIG. 5b is assumed in FIG. 6a.
  • the lower electrode 10 and the wiring 75 have already been formed on the substrate 3.
  • the structure shown in FIG. 6a is formed by depositing the oxide ceramic layer 210 and a first conductive layer 230. Both layers 210 and 230 are predominantly applied conformally to the lower electrode 10 and the wiring 75, the first conductive layer 230 being made relatively thin in contrast to the thickness of the lower electrode 10.
  • the first conductive layer 230 preferably made of platinum, protects the oxide ceramic layer 210 during the subsequent structuring.
  • the structure shown in FIG. 6b is obtained by means of a suitable lithography method with subsequent substrate cleaning.
  • the oxide ceramic layer 210 and the first conductive layer 230 have been completely removed from the wiring 75 and other areas of the substrate 3, so that the layers 210 and 230 only cover the lower electrode 10 in a conforming manner. These now form the capacitor dielectric 15 and the first conductive layer 230 of the upper electrode 20 of the storage capacitor 5.
  • a second conductive layer 235 is formed over the entire surface applied to the substrate 3, the wiring 75 and the first conductive layer 230.
  • This layer 235 is subsequently structured by means of a suitable lithography method, so that, on the one hand, a second conductive layer 235 and a wiring 165 separate therefrom are formed in the region of the storage capacitor 5.
  • the second conductive layer 235 and the first conductive layer 230 together form the upper electrode 20 of the storage capacitor 5.
  • the wiring 165 deposited and structured directly on the substrate 3 is in direct contact with a contact hole 240.
  • a contact hole 250 is etched into the TEOS layer 245 and with a conductive one Material filled.
  • a metallization layer 255 in the form of conductor tracks is formed on the TEOS layer 245, which are connected to the wiring 75 in an electrically conductive manner via the filled contact hole 250.
  • FIGS. 7 and 8 show further variants for contacting the wiring.
  • the wiring 260 can have direct contact with a further conductive layer 265. This is in a contact hole 275 is etched into an insulation layer 270, into which the wiring 260 applied to the insulation layer 270 extends as far as to the further conductive layer 265 arranged under the insulation layer 270.
  • the conductive connection between the wiring 260 and the further conductive layer 265 can of course also be established via a contact hole 275 filled with conductive material. Both polysilicon and other conductive materials can be used for the further conductive layer 265.
  • the wiring 260 also consists of conductive metal silicides or conductive metal nitrides.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Composant à semi-conducteur doté d'au moins une électrode métallique (10) qui fait partie d'une cellule d'accumulation destinée à l'accumulation localement limitée d'une charge électrique, et d'un câblage (75) électriquement conducteur isolé par rapport à l'électrode métallique (10), destiné à la mise en contact électrique de composants (45) individuels du composant à semi-conducteur. Ledit élément à semi-conducteur est caractérisé en ce que l'électrode métallique (10) et le câblage (75) sont constitués de la même matière.
PCT/DE1999/002760 1998-09-30 1999-09-01 Cellule d'accumulation a semi-conducteur et procede d'accumulation de ladite cellule WO2000019526A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19845033.8 1998-09-30
DE19845033A DE19845033A1 (de) 1998-09-30 1998-09-30 Halbleiterbauelement

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WO2000019526A1 true WO2000019526A1 (fr) 2000-04-06

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10008573A1 (de) 2000-02-24 2001-09-13 Infineon Technologies Ag Halbleiterbauelement und Herstellungsverfahren

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Publication number Priority date Publication date Assignee Title
US5399890A (en) * 1991-10-24 1995-03-21 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level
JPH08204012A (ja) * 1994-07-29 1996-08-09 Nec Corp 半導体装置及びその製造方法
JPH0964303A (ja) * 1995-08-25 1997-03-07 Hitachi Ltd 半導体集積回路装置の製造方法
JPH1079479A (ja) * 1996-09-05 1998-03-24 Hitachi Ltd 半導体集積回路装置及びその製造方法
JPH1098166A (ja) * 1996-09-20 1998-04-14 Nippon Steel Corp 半導体記憶装置及びその製造方法

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DE19721232A1 (de) * 1996-05-31 1997-12-04 Electrovac Sauerstoffpartikeldrucksensor mit zwei Meßbereichen
KR100234361B1 (ko) * 1996-06-17 1999-12-15 윤종용 강유전체 캐패시터를 구비하는 반도체 메모리장치 및그제조방법
DE19640240A1 (de) * 1996-09-30 1998-04-02 Siemens Ag Halbleiteranordnung mit einer Schicht aus einem Edelmetall und Verfahren zum Herstellen derselben
DE19640218C2 (de) * 1996-09-30 2000-11-02 Siemens Ag Integrierte Halbleiterspeicheranordnung mit Speicherkondensatoren

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Publication number Priority date Publication date Assignee Title
US5399890A (en) * 1991-10-24 1995-03-21 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level
JPH08204012A (ja) * 1994-07-29 1996-08-09 Nec Corp 半導体装置及びその製造方法
JPH0964303A (ja) * 1995-08-25 1997-03-07 Hitachi Ltd 半導体集積回路装置の製造方法
JPH1079479A (ja) * 1996-09-05 1998-03-24 Hitachi Ltd 半導体集積回路装置及びその製造方法
JPH1098166A (ja) * 1996-09-20 1998-04-14 Nippon Steel Corp 半導体記憶装置及びその製造方法

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PATENT ABSTRACTS OF JAPAN vol. 1997, no. 7 31 July 1997 (1997-07-31) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 8 30 June 1998 (1998-06-30) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 9 31 July 1998 (1998-07-31) *

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