WO1999057811A1 - Circuit de mise en forme d'onde numerique, circuit de multiplication de frequence, circuit de synchronisation exterieure, et procede de synchronisation exterieure - Google Patents

Circuit de mise en forme d'onde numerique, circuit de multiplication de frequence, circuit de synchronisation exterieure, et procede de synchronisation exterieure Download PDF

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Publication number
WO1999057811A1
WO1999057811A1 PCT/JP1999/002321 JP9902321W WO9957811A1 WO 1999057811 A1 WO1999057811 A1 WO 1999057811A1 JP 9902321 W JP9902321 W JP 9902321W WO 9957811 A1 WO9957811 A1 WO 9957811A1
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Prior art keywords
circuit
output
signal
duty
input
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PCT/JP1999/002321
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English (en)
Japanese (ja)
Inventor
Akira Yokomizo
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Akira Yokomizo
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Publication of WO1999057811A1 publication Critical patent/WO1999057811A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle

Definitions

  • the present invention relates to a digital waveform shaping circuit, a frequency doubling circuit, an external synchronizing circuit for generating a digital signal whose frequency is the same as the frequency of a digital input signal and whose phase coincides with the phase position of an external trigger signal, and an external synchronizing method.
  • the cut-off frequency of a semiconductor active device is finite, and the maximum usable frequency is limited.
  • the waveforms of digital signals (1) and (2) have the same repetition frequency f.
  • the waveform of the signal (1) has a ratio of 1: 1 (duty 50%) between the rising H-level section TA and the falling L-level section TB, the ratio of the interval TA and period TB the waveform of the signal (2) is 1: for which ceases to 1, since this c the frequency f of the apparent is increased, IC is duty 50 is semiconductors active element
  • the waveform of% (1) receives the input waveform and operates at the full upper limit of the operable range, the waveform of the input signal changes from the 50% duty state (Signal (1)) to the lower duty cycle. If one waveform (signal (2)) is distorted, a signal having a frequency exceeding the operable range is input to the IC, and the IC can operate in response to the frequency of the input signal. No longer.
  • the digital signal to be handled is preferably a waveform whose ratio between section TA and section TB is 1: 1 (duty 50%).
  • the digital signal to be handled is always shaped into a waveform with a duty ratio of 50 ⁇ 1 ⁇ 2, a signal with a higher frequency can be handled using the same semiconductor active device.
  • the sub-reference signals SA, SB, SC having n different phases from the reference signal S 0 ... is being created.
  • a reference signal having a frequency of m times (m is an integer of 2 or more) the required repetition frequency ⁇ of the synchronization output signal is required.
  • n is an integer of 2 or more sub-reference signals SA, SB, SC with different phases, and triggers
  • these sub-reference signals are divided by the dividers 23, 24, and 25.
  • the divided signals are logically synthesized by the logic circuit 22, and the output is used as a synchronous output signal. It is a circuit to take out.
  • This synchronization signal selection circuit must handle a signal whose frequency is m times the frequency f of the synchronization output signal as the reference signal, but the jitter decreases in accordance with the number of phase divisions, that is, the number n of sub-reference signals. .
  • n sub-reference signals SA, SB, SC having different phases from the reference signal S 0, but conventionally, a large number of delay elements DL 1, DL 1 2 ... were connected in series, and the phase was shifted sequentially through the reference signal.
  • a clock signal generator for writing video signals and a clock signal for reading For example, a clock signal generation circuit requires an external synchronization circuit that generates a clock signal in synchronization with the horizontal synchronization signal.
  • FIG. 14 Japanese Patent Application Laid-Open No. 61-95606
  • a reference signal S 0 having a frequency of m times (m is an integer of 2 or more) the repetition frequency ⁇ of the required synchronization output signal is received, and the phase of the reference signal is sequentially shifted by delay elements DL 1 and DL 2.
  • n (n is an integer of 2 or more) sub-reference signals SA, SB, SC having different phases are generated, and these sub-reference signals are divided into frequency dividers 23, 24,
  • the circuit starts to divide at 25, and the signals after the division are logically synthesized by the logic circuit 22, and the output is taken out as a synchronous output signal.
  • This synchronization signal selection circuit must handle a signal whose frequency is m times the frequency f of the synchronization output signal as the reference signal, but the jitter decreases in accordance with the number of phase divisions, that is, the number n of sub-reference signals. Things.
  • n sub-reference signals SA, SB, SC having different phases from the reference signal S 0, but conventionally, a large number of delay elements DL 1, DL 1 2 ... were connected in series, and the phase was shifted sequentially through the reference signal.
  • the jitter is reduced in accordance with the number of phase divisions, that is, the number n of the sub-reference signals.
  • the number of delay elements to be prepared is as many as 2,000 to 3,000, which is disadvantageous both economically and in terms of element heat generation.
  • the configuration of the frequency multiplication circuit becomes as follows. Further, when the frequency to be handled changes, the design is redone. For this reason, the actual frequency was actually obtained by using an oscillator with a frequency twice as high as the frequency to be obtained and dividing that frequency.
  • the frequency handled will be substantially higher. The problem is that the frequency limit exceeding the operable capacity of the IC may be reached.
  • the jitter is reduced in accordance with the number of phase divisions, that is, the number n of the sub-reference signals.
  • the number of delay elements to be prepared increases to 2,000 to 3,000, which is disadvantageous both economically and in terms of element heat generation. Therefore, it is desired to develop an external synchronous circuit that can extract a quick signal synchronized with a trigger signal without using the technique of sequentially shifting the phase and using as few semiconductor elements as possible. ing. Also, when the conventional external trigger signal fluctuates, it has been difficult to automatically synchronize the output clock following the fluctuation.
  • a practical external synchronization method and external synchronization circuit that can synchronize the input clock signal with the external trigger signal, have a simple configuration, and output the input digital signal after being shaped into a waveform with a duty of 50%. It is hoped that this will be provided.
  • an external synchronization method and an external synchronization circuit that can automatically synchronize the output clock in accordance with the fluctuation are desired.
  • the present invention has been proposed in order to solve the above-described problems of the prior art.
  • the first object of the present invention is to determine whether an input signal has a duty of 50%. Regardless, it is an object of the present invention to provide a waveform shaping circuit which is shaped into a waveform with a duty of 50% and outputted.
  • a second object of the present invention is to improve the efficiency of a practical frequency delay multiplying circuit which has a simple configuration and is output after being shaped into a waveform having a duty of 50%.
  • a third object of the present invention is to provide a practical configuration in which an input clock signal can be synchronized with an external trigger signal, the configuration is simple, and an input digital signal is shaped into a 50% duty waveform and output.
  • An external synchronization method and an external synchronization circuit are used.
  • a fourth object of the present invention is to stt an external synchronization circuit and an external synchronization method capable of automatically synchronizing an output clock following the fluctuation of an external trigger signal. Disclosure of the invention
  • the present invention is configured as follows.
  • a digital waveform shaping circuit generates a required timing signal from an incoming clock signal, and determines a predetermined duty based on the timing signal.
  • a timing signal generating circuit for generating the timing signal; and a N-cycle signal arriving at intervals of an integral multiple of N cycles of the input clock signal.
  • a period measuring circuit for measuring the length an arithmetic circuit for calculating a length of 2N of the total length of the N periods based on a measurement value of the period measuring circuit, and the input clock signal
  • An actual measurement circuit that measures the length in each cycle of the above, and when the measured value of the actual measurement circuit matches the calculated value of the arithmetic circuit, a coincidence signal is output as a timing position with a duty of 50%.
  • a duty determining circuit having a coincidence circuit, a signal synchronized with a leading edge of each pulse of the input clock signal, and a timing position determined and instructed by the duty determining circuit.
  • a width generating circuit that generates and outputs an output clock signal having a pulse width corresponding to a duty of 50%.
  • the measurement circuit and the Z or duty determination circuit may be configured in a plurality of stages. As a result, the measurement accuracy of the cycle of the input clock signal is improved, and the accuracy of waveform shaping of the finally obtained output signal can be improved.
  • the output value of the counter for performing the period measurement operation is periodically all zero.
  • a reset circuit for resetting the state may be provided.
  • the period measurement circuit and the Z or the actual measurement circuit and the Z or the duty determination circuit may output a signal of a plurality of phase stages, and the plurality of phase stages May be provided with a plurality of counters and latches (in the case of an actual measurement circuit, only the counters) corresponding to the signal of (1).
  • period measurement can be performed accurately (period measurement).
  • a signal with a desired duty of 50% can be obtained with certainty.
  • the circuit configuration is simpler and the power consumption is more likely to be greater than when a synchronous counter is used.
  • a frequency doubler circuit includes a digital waveform shaping circuit having the above characteristics.
  • an external synchronization circuit includes a digital waveform shaping circuit having the above characteristics. According to these aspects, the measurement accuracy of the cycle of the input clock signal is improved, so that the accuracy of the finally obtained output signal can be improved.
  • a timing signal is generated by a timing signal generation circuit, and each of the N cycles arriving at intervals of an integral multiple of N cycles of the input clock signal is generated by the cycle measurement circuit.
  • the length of the N period is calculated by the arithmetic circuit based on the measurement value of the period measuring circuit, and the length of the N period is calculated as 1/2 N of the total length.
  • the du one tee one decision circuit determines the indicated timing position Based on the bets, which comprises using the digital waveform shaping method for outputting to create an outgoing Kaku-locking signal having a pulse width corresponding to the duty one 50%.
  • FIG. 1 is a diagram showing a first basic mode of the digital waveform shaping circuit of the present invention.
  • FIG. 2 is a timing chart showing the operation of the main part of the circuit of FIG.
  • FIG. 3 is a diagram showing a second basic mode of the digital waveform shaping circuit of the present invention.
  • FIG. 4 is a timing chart showing the operation of the main part of the circuit of FIG.
  • FIG. 5 is a diagram showing a third basic mode of the digital waveform shaping circuit of the present invention.
  • FIG. 6 is a timing chart showing the operation of the main part of the circuit of FIG.
  • FIG. 7 is a diagram showing a basic form of the frequency doubler of the present invention.
  • FIG. 8 is a timing chart showing the operation of the main part of the circuit of FIG.
  • FIG. 9 is a diagram showing the left half of the circuit showing the first basic mode of the external synchronization circuit of the present invention.
  • FIG. 10 is a diagram showing the right half of the circuit showing the first basic form of the external synchronization circuit of the present invention.
  • FIG. 11 is a timing chart showing the operation of the main parts of the circuits of FIGS. 9 and 10.
  • FIG. 12 is an enlarged view of the upper half of the timing chart of FIG.
  • FIG. 13 is an enlarged view of the lower half of the timing chart of FIG.
  • FIG. 14 is a circuit diagram showing a specific example of the timing generation circuit 302 of FIG.
  • FIG. 15 is a timing chart showing the operation of the timing generation circuit 302 and the mode switching signal generation circuit shown in FIG.
  • FIG. 16 is a timing chart showing the operation of the duty-one determining circuit and the width generating circuit shown in FIG.
  • FIG. 17 is an enlarged view of the upper half of the timing chart of FIG.
  • FIG. 18 is an enlarged view of the lower half of the timing chart of FIG.
  • FIG. 19 is a diagram illustrating the CKFA and CKFB created by the timing generation circuit 301 of FIG. 9, wherein (a) shows a case where one cycle of the input clock is matched, and (b) shows a case where two cycles of the input clock are matched. This shows the case where the period is matched.
  • FIG. 20 is a diagram showing another basic form of the external synchronization circuit of the present invention.
  • FIG. 21 is a diagram for explaining a change in frequency handled by the semiconductor active element.
  • FIG. 22 is a diagram showing a configuration of a phase division unit used in a conventional synchronization signal selection circuit.
  • FIG. 23 is a diagram illustrating one embodiment in which the period measurement time of the digital waveform shaping circuit in FIG. 1 is changed.
  • FIG. 24 is a timing chart showing the operation of the main part of the circuit of FIG.
  • FIG. 25 is a diagram showing an embodiment in which the digital waveform shaping circuit of FIG. 23 is generalized.
  • FIG. 26 is a timing chart showing the operation of the main part when performing 1Z8 frequency division in the circuit of FIG.
  • FIG. 27 is a diagram illustrating an example in which the counter of the timing generation circuit in FIG. 1 is a 1-by-4 counter.
  • FIG. 28 is a diagram illustrating an example in which the counter of the timing generation circuit in FIG. 1 is a 1 ZM counter.
  • FIG. 29 is a diagram illustrating an example in which the counter of the timing generation circuit in FIG. 3 is a ⁇ ⁇ ⁇ ⁇ counter.
  • FIG. 30 is a diagram illustrating an example of a duty determining circuit, a width generating circuit, and the like applied to the case where the timing generating circuit of FIG. 29 or FIG. 32 is used.
  • FIG. 31 is a timing chart showing the operation of the main part of the circuits of FIGS. 29 and 30.
  • FIG. 32 is a diagram showing another example in which the counter of the timing generation circuit in FIG. 3 is a ⁇ ⁇ ⁇ ⁇ counter.
  • FIG. 33 is a timing chart showing the operation of the main part of the circuits of FIGS. 32 and 30.
  • FIG. 34 is a diagram illustrating an example in which the counter of the timing generation circuit in FIG. 3 is a 1 ZM counter.
  • FIG. 35 is a diagram illustrating an example of a duty determination circuit, a width creation circuit, and the like applied to the timing generation circuit of FIG. 34.
  • FIG. 36 is a diagram showing an example in which the counter of the timing generation circuit in FIG. 5 is a ⁇ ⁇ ⁇ ⁇ counter.
  • FIG. 37 is a diagram illustrating an example of a duty decision circuit, an iff creation circuit, and the like applied to the case where the timing generation circuit of FIG. 36 is used.
  • FIG. 38 is a timing chart showing the operation of the main part of the circuits of FIGS. 36 and 37.
  • FIG. 39 is a timing chart showing the operation of the main parts of the circuits of FIGS. 36 and 37.
  • FIG. 40 is a diagram illustrating an example in which the measurement circuit in FIG. 1 is configured in two stages.
  • FIG. 41 is a diagram illustrating an example of a timing generation circuit when the duty determination circuit in FIG. 3 is configured in three stages.
  • FIG. 42 is a diagram illustrating an example in which the duty determination circuit in FIG. 3 is configured in three stages.
  • FIG. 43 is a timing chart showing the operation of the main part of the circuits of FIGS. 41 and 42.
  • FIG. 44 is a timing chart showing the operation of the main part of the circuits of FIGS. 41 and 42.
  • FIG. 45 is a diagram illustrating another example of the timing generation circuit when the duty determination circuit in FIG. 3 is configured in three stages.
  • FIG. 46 is a timing chart showing the operation of the main part of the circuits of FIGS. 45 and 42.
  • FIG. 47 is a diagram illustrating an example in which the duty determination circuit in FIG. 5 is configured in three stages.
  • FIG. 48 is a diagram illustrating an example of a timing generation circuit when the duty-one determining circuit in FIG. 3 is configured in M stages.
  • FIG. 49 is a diagram illustrating an example in which the duty determination circuit in FIG. 3 is configured in M stages.
  • FIG. 50 is a diagram illustrating an example in which the duty determination circuit in FIG. 5 is configured in M stages.
  • FIG. 51 is a diagram illustrating an example of a power reset signal generation circuit.
  • FIG. 52 is a time chart showing an example of the power reset signal of FIG.
  • FIG. 53 is a diagram showing an embodiment in which a power supply reset is added to the timing signal generation circuit in FIG.
  • FIG. 54 shows the duty ratio applied to the timing signal generation circuit in Fig. 53.
  • FIG. 3 is a diagram illustrating an example of a constant circuit, a width creation circuit, and the like.
  • FIG. 55 is a diagram illustrating an example of a duty determination circuit, a width creation circuit, and the like applied when the circuit in FIG. 53 is used as the timing signal generation circuit in FIG.
  • FIG. 56 is a diagram showing an embodiment in which a periodic reset is added to the timing signal generation circuit in FIG.
  • FIG. 57 is a diagram illustrating an example of a duty determination circuit, a width creation circuit, and the like applied to the timing signal generation circuit in FIG. 56.
  • FIG. 58 is a diagram showing an embodiment in which a periodic reset is added to the timing signal generation circuit in FIG.
  • FIG. 59 is a timing chart showing the operation of the main parts of the circuits of FIGS. 56 to 58.
  • FIG. 60 is a diagram showing an embodiment in which the frequency divider of the timing signal generation circuit of FIG. 56 is generalized.
  • FIG. 61 is a timing chart showing part of the operation of the waveform shaping circuit of FIG.
  • FIG. 62 is a diagram showing an embodiment in which positive and negative two-phase latches are added to the waveform shaping circuit of FIG.
  • FIG. 63 is a diagram showing a part of the waveform shaping circuits of FIGS. 3 and 5.
  • FIG. 64 is a timing chart showing the operation of the circuit of FIG.
  • FIG. 65 is a diagram showing an embodiment in which only the state of the counter is latched in the waveform shaping circuits of FIGS. 3 and 5.
  • FIG. 66 is a diagram showing an embodiment in which the state of DL-OSC in FIG. 65 is also latched.
  • FIG. 67 is a diagram showing an embodiment in which the state of DL-OSC is also latched in FIG. 65 and FIG. 66, and two latches are added so that the pulse width of SA is widened.
  • FIG. 68 is a diagram showing the relationship between the frequency of DL-OSC and the frequency of the counter.
  • FIG. 69 is a diagram illustrating a configuration example (a) in which DL-OSC is a two-stage NAND and a configuration example (b) in which a four-stage NAND is used.
  • FIG. 70 is a diagram illustrating an example using a multi-stage DL-OSC.
  • FIG. 71 is a diagram showing an embodiment using two stages of DL-OSC and two-phase clocks.
  • FIG. 72 is a timing chart showing the operation of the circuits of FIG. 71 and FIG.
  • FIG. 73 is a diagram illustrating an embodiment in which the waveform shaping circuits of FIGS. 1 and 3 are set to have a duty other than 50% (create a two-phase clock for CPU).
  • FIG. 74 shows the waveform shaping circuit of FIG. /.
  • FIG. 10 is a diagram showing an embodiment in the case of setting other than (creating a two-phase clock for CPU).
  • FIG. 75 is a diagram showing an embodiment in which the CKW circuit is deleted from the waveform shaping circuit of FIG.
  • FIG. 76 is a diagram illustrating an example of the timing generation circuit applied to FIG.
  • FIG. 77 is a timing chart showing the operation of the circuits of FIGS. 75 and 78.
  • FIG. 78 is a diagram showing an embodiment in which RS ⁇ FF is changed to PD ⁇ FF in the waveform shaping circuit of FIG. 75.
  • FIG. 79 is a diagram showing an embodiment in which the waveform shaping circuit of FIG. 75 is configured with a positive-negative two-phase counter.
  • FIG. 80 is a diagram illustrating an example in which the waveform shaping circuit of FIG. 1 is applied to a delay circuit (phase adjustment circuit).
  • FIG. 81 shows another example in which the waveform shaping circuit of FIG. 1 is applied to a delay circuit (phase adjustment circuit).
  • FIG. 82 is a diagram illustrating an example in which the waveform shaping circuit of FIG. 3 is applied to a delay circuit.
  • FIG. 83 is a timing chart showing the operation of the circuits of FIGS.
  • FIG. 84 is a diagram illustrating one embodiment in which the waveform shaping circuit of FIG. 1 is applied to a frequency doubler.
  • FIG. 85 is a diagram showing another embodiment in which the waveform shaping circuit of FIG. 1 is applied to a frequency doubling circuit.
  • FIG. 86 shows an embodiment in which the frequency shaping circuit of FIG. 1 is applied to a frequency doubling circuit, and the frequency dividing ratio of the frequency divider constituting the timing signal generating circuit is 1 / M.
  • FIG. 86 shows an embodiment in which the frequency shaping circuit of FIG. 1 is applied to a frequency doubling circuit, and the frequency dividing ratio of the frequency divider constituting the timing signal generating circuit is 1 / M.
  • FIG. 87 is a diagram illustrating another embodiment in which the frequency shaping circuit of FIG. 1 is applied to a frequency doubling circuit and the frequency division ratio of a frequency divider that forms a timing signal generation circuit is 1 ZM. It is.
  • FIG. 88 is a diagram illustrating an example in which the duty ratio determining circuit is provided in three stages in the frequency doubling circuit of FIG.
  • FIG. 89 is a diagram illustrating an example of a case where the waveform counter is operated by a positive / negative two-phase clock in an example in which the waveform shaping circuit of FIG. 1 is applied to a frequency multiplying circuit.
  • Figure 90 shows an example in which the waveform shaping circuit in Figure 1 is applied to a frequency multiplication circuit. It is a figure showing an example when operating.
  • FIG. 91 is a timing chart showing an example of the output frequency of the delay line oscillator.
  • FIG. 92 is a diagram illustrating a configuration example (a) in which DL-OSC is a two-stage NAND and a configuration example (b) in which a four-stage NAND is used.
  • FIG. 93 is a diagram showing an example using multiple stages of DL-OSC.
  • Figure 94 shows an example of applying the waveform shaping circuit of Fig. 1 to a frequency doubling circuit, and using only one set of matching circuit and arithmetic circuit, the frequency division ratio of the frequency divider that constitutes the timing signal generation circuit. It is a figure which shows the example which made 1 ZM.
  • Fig. 95 shows an example in which the waveform shaping circuit of Fig. 1 is applied to a frequency multiplying circuit, and an adder is used to add each output edge to change the matching value. is there.
  • FIG. 96 is a diagram illustrating an example in which the magnification ratio is M in the frequency doubling circuit of FIG. -FIG. 97 is a diagram illustrating an example in which the frequency division ratio of the frequency divider of the timing generation circuit is 1 in the frequency doubling circuit of FIG.
  • FIG. 98 is a diagram showing a circuit diagram of the right half of FIG. 97.
  • Figure 99 shows a simplified version of the frequency doubling circuit of It is a figure showing an example.
  • FIG. 100 shows an example in which the delay multiplication ratio is M and the frequency division ratio of the frequency divider of the timing generation circuit is 1 ZM in the frequency doubling circuit of FIG. It is a figure showing the example applied.
  • FIG. 101 is a diagram showing another example of FIG.
  • FIG. 102 is a diagram showing another example of FIG.
  • FIG. 103 is a diagram showing an example in which the waveform shaping circuit of FIG. 77 is applied to a frequency doubling circuit.
  • FIG. 104 is a diagram showing an example in which the frequency division ratio of the frequency divider of the timing generation circuit is 1 in the frequency multiplication circuit of FIG. 103.
  • FIG. 105 is a diagram illustrating an example in which a single arithmetic circuit is used in the frequency delay multiplying circuit of FIG. 103.
  • FIG. 106 is a diagram showing an example in which the frequency division ratio of the frequency divider of the timing generation circuit is 1 / M in the frequency multiplication circuit of FIG.
  • FIG. 107 is a diagram showing an embodiment in which addition is performed for each edge of the output clock in the frequency multiplication circuit of FIG.
  • FIG. 108 is a diagram showing an example in which the frequency division ratio of the frequency divider of the timing generation circuit is 1 ZM in the frequency multiplication circuit of FIG. 107.
  • FIG. 109 is a diagram showing an example of a case where a duty other than 50% is set in the frequency doubler circuit.
  • FIG. 110 is a timing chart showing the operation of the circuit of FIG.
  • FIG. 11 is a diagram illustrating an example of application to a dot clock in a frequency doubling circuit.
  • FIG. 112 is a timing chart showing the operation of the circuit of FIG.
  • FIG. 11 is a diagram showing an example in which a frequency doubling circuit is applied to the inside of a CPU chip to reduce power consumption, noise, cost, and the like, and to facilitate pattern design.
  • Fig. 114 shows the problems of power consumption, noise, and cost when the frequency doubling circuit makes it easy to supply multiple chips on a printed circuit board.
  • FIG. 115 shows an example in which a frequency doubling circuit is incorporated in a device so as to cover a wide frequency band as a solution to the problem of FIG.
  • FIG. 116 is a diagram showing a problem of supplying a clock to the CPU in the parallel processing computer.
  • FIG. 117 is a diagram showing an example in which a frequency doubling circuit and the phase adjustment circuits shown in FIGS. 79 to 81 are used in combination to solve the problem of FIG.
  • FIG. 118 shows an example in which the frequency division ratio of the frequency divider of the input clock of the timing generation circuit in FIG.
  • FIG. 119 is a diagram showing an example in which a change corresponding to FIG. 118 is added to FIG.
  • FIG. 120 is a diagram illustrating an example in which the frequency division ratio of the frequency divider of the input clock of the timing generation circuit in FIG. 9 is set to 1 / M.
  • FIG. 122 is a diagram showing an example in which a change corresponding to FIG. 120 is made in FIG.
  • Fig. 122 shows the whole circuit for measuring the arrival position of the external trigger in Fig. 9 (at which phase of the input clock C the EXTTRIG was input) and reproducing it.
  • FIG. 123 is a diagram showing an example in which the timing generation circuit in FIG. 122 is configured in three phases, the design magazine is enlarged, and the operation is stabilized.
  • FIG. 124 is a timing chart showing the operation of FIG.
  • FIG. 125 is a diagram illustrating an example corresponding to the entire circuit of FIG. 122 when the timing generation circuit in FIG. 9 is changed to three types of phase outputs.
  • FIG. 126 is a diagram showing an example of the timing generation circuit of FIG. 123 in which the phases are changed from three phases to polyphase.
  • -FIG. 127 is a diagram illustrating an example corresponding to the entire circuit of FIG. 122 or FIG. 125 when the timing generation circuit of FIG. 126 is applied.
  • FIG. 128 is a diagram showing an example of a duty determination circuit when the external synchronization circuit of FIG. 10 is applied to a double frequency doubler.
  • FIG. 129 is an example in which the external synchronous circuit of FIG. 10 is applied to a double frequency doubler circuit, and is a diagram showing an example in which the duty-one determination circuit of FIG. 128 is incorporated.
  • FIG. 130 is a diagram showing an example in the case of using in combination with the external synchronization circuit of FIG. 119 in FIG.
  • FIG. 13 1 is a diagram showing an example of the duty determination circuit in FIG.
  • FIG. 1332 is a diagram showing an example in which the multiple of FIG. 128 incorporated in FIG. 128 is changed to a generalized multiple.
  • FIG. 13 33 is a diagram showing an example in which FIG. 13 2 is modified to correspond to a generalized period measurement.
  • FIG. 134 is a diagram showing an example in which the external synchronization circuit of FIG. 10 is applied to a frequency multiplier circuit incorporating the duty determining circuit of FIG.
  • FIG. 135 is a diagram showing an example in which the external synchronization circuit of FIG. 10 is applied to a frequency doubling circuit incorporating the duty determination circuit of FIG. 100.
  • FIG. 136 is a diagram showing an example in which the duty decision circuit of FIG. 101 is incorporated in FIG.
  • FIG. 137 is a diagram showing an example in which the duty decision circuit of FIG. 102 is incorporated in FIG.
  • FIG. 138 is a diagram illustrating an example in which the external synchronization circuit of the present embodiment is applied to video.
  • the digital waveform shaping circuit 1 shown in FIG. 1 includes a timing generating circuit 2 for generating a required timing signal “CKF, 1 / 2CKW, 1 / 2CK, and CKW” from the input clock signal CK.
  • Timing signal 1/2 CKW, 1/2 generated by timing generator 2 C In response to the CKW, the duty determination circuit 3 that determines and indicates the timing position of the desired duty value of the clock signal to be output (here, the duty is 50%) and the duty determination circuit 3
  • a width generating circuit 5 that generates and outputs a clock signal (RS-FFQ) having a pulse width corresponding to the duty of 50% based on the instructed timing position.
  • CK is a clock signal input to the timing generation circuit 2, and is a clock signal whose repetition frequency is constant (period T) but whose duty may vary.
  • the input clock signal CK is exaggeratedly drawn as a waveform whose duty fluctuates halfway.
  • the timing generation circuit 2 generates necessary timing signals CKF, 1/2 CKW, 1 / 2CK, and CKW shown in FIG. 2 from the input clock signal CK.
  • CKF is a timing signal composed of short pulses generated at the leading edge of the input clock signal CK, and is used as an input of an RS flip-flop (hereinafter, referred to as RS-FF) 5 a constituting the width generating circuit 5. used.
  • RS-FF RS flip-flop
  • 1 / 2CK is a timing signal for determining the section (target measurement section) T1 to be measured as the length of one cycle T of the input clock signal CK.
  • the input clock signal CK is 1 / This is a signal obtained by dividing by two.
  • the odd-numbered one-period section T1 of this signal 1 / 2CK is used to establish the target measurement section.
  • 1 / 2CKW is a timing signal for establishing a section (actual measurement section) T3 for maintaining the measurement operation over the target measurement section T1.
  • This 1 / 2CKW is a signal whose fall is slightly delayed from the above 1 / 2CK, that is, it rises at the same time as the input clock CK and falls after the fall of the 1 / 2CK.
  • the width is slightly longer than one cycle T of the input clock signal CK. It is a long signal.
  • the 1 / 2CKW can be obtained, for example, by creating a signal obtained by slightly delaying the 1 / 2CK within the width of the 1/2 cycle, and ORing the signal with the 1 / 2CK.
  • CKW defines the oscillation reference interval for the signal CK, starting from the leading edge and ending before reaching the leading edge of the next input clock, every time the clock signal CK arrives
  • This signal is a timing signal for establishing a section (oscillation matching section) T4 for actually measuring the timing position with a duty of 50%.
  • This CKW is the beginning of the odd-numbered one-period period T1 of the 1 / 2CK in the period period in which the CK is not measured, that is, the even-numbered one-period period T2 of the timing signal 1 / 2CK.
  • the duty-one determining circuit 3 receives the timing signal 1 / 2CKW and measures the length of the odd-numbered one cycle T1, and the odd-numbered one-cycle length receiving the measurement result.
  • An arithmetic circuit 19 that calculates a half value of T1, that is, a timing position of 50% duty, and the above timing signal CKW, while the CKW is at the H level, a timing of 50% duty for the signal CK And an actual measurement circuit 20 for actually measuring the position.
  • the cycle measuring circuit 10 includes a delay line oscillator 11, a counter 17, and a latch circuit 18.
  • the parallel output of the latch circuit 18 is received by the arithmetic circuit 19, and the parallel output is received by the coincidence circuit 28.
  • the delay line oscillator 11 includes a NAND gate 12 that receives the timing signal 1 / 2CKW at one input terminal, and an odd-numbered C-MOS inverter 13 as a delay element connected to the output terminal of the NAND gate 12. And a simple inverter 15 for inversion inserted in a feedback loop 14 from the output terminal of the inverter 13 to the other input terminal of the NAND gate.
  • an ECL inverter As the inverter 13 as a delay element, an ECL inverter, an IIL inverter and the like can be used in addition to the C-MOS inverter.
  • the delay line oscillator 11 receives a timing signal 1 / 2CKW (actual measurement section T3) from the timing generation circuit 2 and generates an oscillation for measurement at its rising edge. Starts and stops oscillation at the falling edge. That is, the NAND gate 12 normally has one input terminal at a logic level L, an output at H, an inverter 13 at its output at L, and an inverter 15 at its output (NAND gate 12). (The other input pin) is in the H state, and oscillation is stopped.
  • a timing signal 1 / 2CKW actual measurement section T3
  • the delay line oscillator 11 starts oscillating at the rise of the timing signal 1 / 2CK obtained by dividing the input clock signal CK by 1/2 (start of the target measurement section T1). Then, oscillation stops after the falling edge of 1 / 2CK (after the end of the target measurement section T1). Therefore, oscillation continues during each odd-numbered one cycle of the timing signal 1 / 2CK (target measurement section T1).
  • the clock input terminal CK of the counter 17 is connected to the output terminal of the delay line oscillator 11, and the output DL—OSC 1 of the delay line oscillator 11 changes. The output change that occurs once is counted.
  • the timing signal 1 / 2CKW (actual measurement section T3) is input to the clear terminal CL of the counter 17.
  • the counter 17 starts powering simultaneously with the rise of the timing signal 1 / 2CK (target measurement section T1), in the same manner as the operation of oscillating and stopping the delay line oscillator 11; Stop counting after 2CK (target measurement section T1) falls. Therefore, the count of the number of oscillation cycles continues during each odd-numbered one cycle section of the timing signal 1 / 2CK (target measurement section T 1).
  • (c) Latch circuit 18 The latch circuit 18 receives the digit output of the counter 17 as an input, and the clock signal CK receives the timing signal 1/2 CK (target measurement section T1) created by the timing generation circuit 2 as its input. I have.
  • the latch circuit 18 latches the count value of the counter 17 (the number of oscillation cycles) when the timing signal 1 / 2CK (target measurement section T1) falls, that is, when the target measurement section T1 ends. I do.
  • the latch circuit 18 has a count value of the number of oscillation cycles corresponding to the length of each odd-numbered one cycle section (one cycle T of the input clock signal CK) of the timing signal 1 / 2CK (target measurement section T1). Is latched.
  • the arithmetic circuit 19 receives the output of the latch circuit 18 and receives a half of the count value of the number of oscillation cycles during the odd-numbered one cycle of the timing signal 1 / 2CK (target measurement section T 1), that is, 50% Calculate the duty value. This value is one input to the match circuit 28.
  • the measurement circuit 20 includes a delay line oscillator 21 configured in the same manner as in the case of the period measurement circuit 10, and a second counter 27.
  • the delay line oscillator 21 and the second counter 27 receive the timing signal CKW. Therefore, the delay line oscillator 21 keeps oscillating while CKW is at the H level (oscillation verification section T4).
  • the counter 27 counts the number of oscillations of the delay line oscillator 21 during the section # 4 in which the oscillation is performed. During the counting, the count value passes through the 50% duty timing position for signal C #.
  • the matching circuit 28 compares the two values with the calculated value corresponding to the duty of 50% obtained from the arithmetic circuit 19 as one input and the count value obtained from the counter 17 as the other input.
  • the first duty-one determination circuit 3 determines the timing position of the desired duty-one value (duty-one 50%) of the clock signal to be output, and uses this as the coincidence output SA to create the width. Instruct circuit 5.
  • the width generation circuit 5 receives the timing signal CKF at the set input terminal S of the RS-FF5a, and receives the coincidence output SA at the reset input terminal R. Therefore, RS-FF 5a of the width generation circuit 5 is set by the timing signal CKF generated at the leading edge of each cycle of the input clock signal CK, and the coincidence output generated at the timing position of 50% duty. Reset by SA.
  • the digital clock shaping circuit 1 always shapes it into a clean clock signal with a 50% duty waveform and outputs it. (RS—FF Q).
  • Fig. 3 shows the second basic form. This is because two sets of duty-determining circuits 3 and 4 having the same configuration are provided, and both circuits are shifted from each other by two cycles of the input clock signal CK as shown in FIG. 4 as operating cycles C1 and C2. It is designed to operate alternately. Note that the first duty determining circuit 3 is referred to as A side and the second duty determining circuit 4 is referred to as B side as necessary, and the reference numerals are appended with suffixes A and B to distinguish them. (i) Duty one decision circuit 3, 4
  • the first duty determination circuit 3 treats every four cycles (4T) of the input clock signal CK as one unit of repetition (operation cycle C1), of which the first cycle of the first half is performed.
  • Tl The length of one cycle of the input clock signal CK (target measurement section on the A side) T1A is measured, and using this measurement result, the value of half the length of one cycle T (timing with 50% duty) Position), and on the basis of this, in the third half (t 3) and the fourth half (t 4) of the second half, the calculated value matches the calculated value from the leading edge of the input clock signal CK, respectively. It measures the length T5A up to (ie, up to the 50% duty position), and outputs a coincidence signal SA indicating that it is the 50% duty position when they match.
  • the second duty cycle determining circuit 4 has its operation cycle C2 shifted from the first duty cycle determining circuit 3 by two cycles. That is, the second duty-one determination circuit 4 treats each of the four periods (4T) of the input clock signal CK shown as t3 to t6 in FIG. 4 as one unit of repetition (operation cycle C2), and the first half thereof.
  • operation cycle C2 the first cycle (t 3) of the above, the length of one cycle of the input clock signal CK (target measurement section on the B side) T1 B is measured, and the value of half the length T of one cycle is calculated using the measurement result.
  • the length T5B is measured until the calculated value becomes 1 or less (that is, up to the timing position with a duty of 50%), and when they match, a match signal SB indicating that the duty position is at a 50% duty position Is output.
  • Each of the duty determination circuits 3 and 4 simplifies the configuration of the duty determination circuit 3 described with reference to FIG. 1, and serves as both the period measurement circuit 10 and the actual measurement circuit 20 by a set of delay line oscillators 11 and 1.
  • RS-FF 6, 8 The first duty decision circuit 3 is preceded by RS-FF 6, and its Q output is input to the delay line oscillator 11 of the duty decision circuit 3 through the OR gate 7 (OR-A). And input to one input terminal of the OR gate 5b. Then, the output of the matching circuit 28, that is, the output of the duty-one determination circuit 3, is input to the reset terminal R of the RS-FF 6 preceding the output. Together with the OR gate 5 b, the RSF F 6 constitutes the width creating circuit 5.
  • This RS-FF6 is generated at the leading edge of the input clock signal CK when the QN ((8) in Fig. 4) of JK-FF in the timing generation circuit 2 is H, that is, when the A side is in the oscillation verification section. This is set by the short pulse SET-A ((9) in Fig. 4) and reset by the coincidence signal SA ((15) in Fig. 4) (see (11) in Fig. 4).
  • An RS-FF 8 and an OR gate 9 are provided in front of a second duty determining circuit 4 which is configured exactly the same as the first duty determining circuit 3 having such a configuration.
  • the signal is input to the delay line oscillator 11 of the duty determination circuit 4 through the gate 9 (OR-B), and is input to the other input terminal of the OR gate 5b.
  • the output of the matching circuit 28, that is, the output of the duty determination circuit 4 is input to the reset terminal R of the RS-FF 8 preceding the output.
  • This RS-FF 8 also forms the width creation circuit 5 together with the OR gate 5b.
  • This RS-FF8 is output before the input signal CK when the Q of the JK-FF ((7) in Fig. 4) in the timing generation circuit 2 is H, that is, when the B side is in the oscillation verification section. It is set by the short pulse SET-B (Fig. 4, (16)) generated at the edge, and reset by the coincidence signal SB ((21) of Fig. 4) (see (18) of Fig. 4).
  • the timing generation circuit 2 internally generates the timing signals SET-AB, 1 / 2CK, 1 / 2CK-DL, WC, JK-FF-Q, JK-FF-QN. These signals are used to create and output the timing signals SET-A, SET-B, 1 / 2CKA, 1 / 2CKB, WC-A, and WC-B.
  • SET-AB ((3) in Fig. 4) is a timing signal consisting of short pulses generated at the leading edge of the input clock signal CK.
  • 1 / 2CK ((4) in Fig. 4) is a timing signal for determining the section (target measurement section) T1 to be measured as the length of one cycle T of the input clock signal CK. This signal is obtained by dividing clock signal CK by 12.
  • WC ((6) in Fig. 4) is a timing signal for establishing the sections (actual measurement sections) T3A and T3B for maintaining the measurement operation over the target measurement section T1.
  • This WC is a signal whose fall is slightly delayed from the above 1 / 2CK, that is, a signal whose rise width is slightly longer than one cycle T of the input clock signal CK at the same time as the input clock CK.
  • This WC generates a signal 1 / 2CK-DL ((5) in Fig. 4) that is a half delay of 1 / 2CK within the width of 1/2 cycle, and ORs this with 1 / 2CK. It is obtained by
  • J KF FQ ((7) in Fig. 4) is the output Q signal of JK-FF in the timing generation circuit 2.
  • the A side is in the measurement section (B side is the oscillation verification section).
  • JK-FFQN ((8) in Fig. 4) indicates that when the output QN of JK-FF in the timing generation circuit 2 is H, the B side is the measurement section (A side is the oscillation verification section) Instruct.
  • SET—A ((9) in Figure 4) is the input clock signal when the QN ((8) in Figure 4) of JK-FF in the timing generation circuit 2 is H, that is, when the A side is in the oscillation verification section.
  • This is a timing signal consisting of a short pulse generated at the leading edge of the signal CK, and serves as a set input for RS-FF 6 on the A side.
  • -SET-B ((16) in Fig. 4) sets the input clock when the JK-FF Q ((7) in Fig. 4) in the timing generator 2 is H, that is, when the B side is in the oscillation verification section.
  • This is a timing signal consisting of short pulses generated before the signal CK, and serves as a set input for the RS-FF8 on the B side.
  • 1 / 2CKA ((14) in Fig. 4) is a signal for establishing the target measurement section T1A on the A side, and Q of JK-FF in the timing generation circuit 2 ((7) in Fig. 4).
  • Is H that is, the signal obtained by extracting 1 / 2CK while the A side is in the measurement section (B side is in the oscillation verification section).
  • the 1/2 CKB ((20) in Fig. 4) is a signal for establishing the target measurement section T1B on the B side, and the QN of JK-FF in the timing generation circuit 2 ((8) in Fig. 4) ) Is H, that is, the signal obtained by extracting 1/2 CK while the B side is in the measurement section (A side is the oscillation verification section).
  • the target measurement interval T1A, TlB to be measured as the length of one cycle T from the input clock signal CK is an integer multiple of one cycle T of the input clock signal CK, here, three times the interval T6A, T6B It is caused to open and instruct.
  • WC-A and WC-B are timing signals for the actual measurement sections T3A and T3B, and have a pulse width longer than T1.
  • the clock CK enters.
  • the timing generation circuit 2 starts to divide the input clock signal CK by 1/2 and the first SET-AB of the first cycle t1 occurs (a in Fig. 4),-? Output. ((7) in Fig. 4) is at the H level, which instructs the A-side duty-one determination circuit 3 to perform measurement operation.
  • the timing signal WC-A ((10) in Fig. 4) is input to the delay line oscillator 11 through the OR gate 7 to start oscillation, and is input to the clear terminal CL of the counter 17 at the rising edge.
  • the counter 17 starts counting the number of oscillation cycles.
  • the oscillation of the delay line oscillator 11 continues at least until the rising of the clock in the second cycle t2 is completed.
  • the oscillation of the delay line oscillator 11 is caused by the fall of WC-A that occurs before the rise of the clock of the third cycle t3, that is, the actual measurement section T 3 A, which has passed one cycle T of the input clock CK.
  • the process ends when the process ends (point c in Fig. 4).
  • the end of the target measurement section Tl A of 1/2 CK A having a length equivalent to one cycle T of the input clock CK has arrived (point b in FIG. 4), and the latch circuit 18
  • the arithmetic circuit 19 receives the output of the latch circuit 18, calculates a half of the force value having a length of one cycle, that is, a timing position with a duty of 50%, outputs the calculated result, and outputs a match. Input to one of the input terminals ⁇ 1 to ⁇ ⁇ of the circuit 28.
  • RS-FF6 is set by the arrival of SET-A ((9) in Fig. 4) (point d in Fig. 4).
  • the set output Q of RS-FF 6 ((11) in FIG. 4) appears at the output OUT through the OR gate 5b, and is applied to the delay line oscillator 11 on the A side through the OR gate 7 to oscillate this.
  • the coincidence circuit 28 Since the set output Q of the RS-FF 6 is added to the clear CL of the counter 17 on the A side through the OR gate 7 and is cleared, the count of the number of oscillation cycles is started.
  • the output of the counter 17 is input to the other input terminals A1 to An of the matching circuit 28, and the count value of the counter 17 increases step by step, and the value output from the arithmetic circuit 19 is output.
  • the coincidence circuit 28 At the moment (point e in FIG. 4) that coincides (half the length T of one cycle), the coincidence circuit 28 generates the coincidence output SA.
  • the coincidence output SA is input to the reset input terminal QN of RS-FF6, and resets the flip-flop. Therefore, when the coincidence output S A is generated, the set output Q of RS-FF 6 ((11) in FIG. 4) falls, and appears as a pulse P 1 at the OR gate 5b.
  • this output pulse P 1 is a pulse that rises at the leading edge of the external input clock CK whose period is T, and then falls at a position that is half the length T of one period (duty: 50 ° / o). Has become.
  • SET-A ((9) in Fig. 4) arrives again (point f in Fig. 4), and RS-F-F6 is set.
  • RS The set output Q of FF6 ((11) in FIG. 4) appears at the output OUT through the OR gate 5b, and is applied to the delay line oscillator 11 on the A side through the OR gate 7 to oscillate it. Also clears counter 17 and starts counting the number of oscillation cycles.
  • the count value of the counter 17 is the output value of the arithmetic circuit 19 (the length of one cycle (Half point) (point g in FIG. 4), the match circuit 28 again generates a match output SA. Since RS-FF6 is reset by the coincidence output SA, the set output Q of RS-FF6 ((11) in FIG. 4) falls, and appears as a pulse P2 on the OR gate 5b. Naturally, this output pulse P 2 also rises at the leading edge of the external input clock CK and falls at a position where the duty is 50%.
  • the timing signal WC-B ((17) in Fig. 4) rises (point h in Fig. 4), the oscillation is started by the OR gate 9 and the delay line oscillator 11 on the B side is started, and the counter is started. 17 is input to the clear terminal CL, and the counter 17 starts counting the number of oscillations at the rising edge.
  • the oscillation of the B-side delay line oscillator 11 continues at least until the rising edge of the clock in the fourth cycle t4 is completed.
  • the oscillation of the delay line oscillator 11 on the B side is caused by the falling edge of WC-B that occurs before the rising edge of the clock at the fifth period t5, that is, the one period T of the input clock CK
  • the operation ends when the actual measurement section T3 B, which has passed for a while, ends (point i in FIG. 4).
  • the end of the target measurement section T 1 B of 1/2 CKA which has a length equivalent to one cycle T of the input clock CK, has just arrived (point i in FIG. 4).
  • the arithmetic circuit 19 on the ⁇ side receives the output of the latch circuit 18 and calculates half the count value of the length ⁇ of one cycle, that is, the timing position of 50% duty, and calculates the arithmetic result. Is output to one of the input terminals ⁇ 1 to ⁇ of the matching circuit 28.
  • RS-FF 8 is set by the arrival of SET-B ((16) in FIG. 4) (point k in FIG. 4).
  • the set output Q of RS-FF 8 appears at the output OUT through the OR gate 5b, and is applied to the delay line oscillator 11 on the B side through the OR gate 9 to oscillate it.
  • the set output Q of the RS-FF 8 passes through the OR gate 9 and joins the clear CL of the counter 17 on the B side to release the clear, so that the counting of the number of oscillation cycles is started.
  • the output of the counter 17 on the B side is input to the other input terminals A1 to An of the match circuit 28, and the count value of the counter 17 increases in a stepwise manner.
  • the match circuit 28 At the moment when the value matches the output value of 9 (half of the length T of one cycle) (point q in FIG. 4), the match circuit 28 generates a match output SB.
  • the coincidence output SB is input to the reset input terminal QN of RS-FF8, and resets the flip-flop. Therefore, at the point when the coincidence output SB occurs, the set output Q ((18) in FIG. 4) of RS-FF8 falls and appears as a pulse P3 on the OR gate 5b.
  • the output pulse P3 is a pulse that rises at the leading edge of the external input clock CK and falls at the position where the duty is 50%.
  • SET-B ((16) in Fig. 4) arrives again (point r in Fig. 4), and RS-FF8 is set.
  • RS The set output Q of FF8 ((18) in Fig. 4) appears at the output OUT through the ⁇ R gate 5b, and is applied to the delay line oscillator 11 on the B side through the OR gate 9 to oscillate it. Also, clear counter 17 and start counting the number of oscillation cycles.
  • the match circuit 28 When the count value of the counter 17 matches the output value of the arithmetic circuit 19 (half the length of one cycle) (point s in FIG. 4), the match circuit 28 again generates a match output SB. Since the RS-FF 8 is reset by the coincidence output SB, the set output Q ((11) in FIG. 4) of the RS-FF 8 falls, and appears as a pulse P4 on the OR gate 5b.
  • this output pulse P4 also rises at the leading edge of the external input clock CK and falls at a duty of 50%.
  • the OR gate 5b it is synchronized with the input clock CK and the duty 50% output clock is obtained.
  • the above operation and effect can be obtained even when the duty of the input clock CK fluctuates around 50% or more, so that it is very effective as a digital waveform shaping, and is a semiconductor active device.
  • the operable range can be extended to very high frequencies.
  • Fig. 5 shows the third basic mode. This is because, in the circuit shown in Fig. 3, a presettable D-FF5c is provided in the width creation circuit 5, its QN and D terminals are directly connected, and SET-A and SET-B are connected to the preset input terminal PR. (That is, SET-AB) is input via the OR gate 5d, and the match outputs SA and SB are input via the OR gate 33 to the clock input terminal CK of D-FF5c.
  • AND gates 31 and 32 are provided to inhibit coincidence output during the measurement period. ANDed with the Q output.
  • Figure 6 shows the operation of the main elements of the circuit of Figure 5.
  • the timing signal WC—A ((10) in FIG. 6) passes through the OR gate 7 to the delay line oscillator 1 1 Is input to the counter 17 and the signal is input to the clear terminal CL of the counter 17.
  • the counter 17 starts counting the number of oscillation cycles. The oscillation of the delay line oscillator 11 continues at least until the rising of the clock in the second cycle t2 is completed.
  • the arithmetic circuit 19 receives the output of the latch circuit 18, calculates half of the force value of the length of one cycle (the timing position at the duty of 50%), and outputs the calculation result. Input to one of the input terminals ⁇ 1 to ⁇ ⁇ of the matching circuit 28.
  • RS-FF6 is set by the arrival of SET-A ((9) in Fig. 6) (point d in Fig. 6).
  • the set output Q of RS-FF 6 ((11) in FIG. 6) is input to the AND gate 31 and is applied to the delay line oscillator 11 on the A side through the OR gate 7 to oscillate this.
  • the set output Q of the RS-FF 6 is added to the clear CL of the counter 17 on the A side through the OR gate 7 and is cleared, so that the counting of the number of oscillation cycles is started.
  • the output of the counter 17 is input to the other input terminals A1 to An of the matching circuit 28, and the count value of the counter 17 increases step by step. At the moment when it matches the value (half of the length T of one cycle) (point e in FIG. 6), the match circuit 28 generates a match output SA.
  • This coincidence output SA is input to the reset input terminal QN of RS-FF6 to reset the flip-flop.
  • the set output Q of RS-FF6 ((11) in Fig. 6) falls and becomes the input of AND gate 31 in the form of pulse P1.
  • a short pulse AND—A—OUT ((16) in FIG. 6) is generated at the leading edge of the coincidence output SA from the AND gate 31 having the pulse P1 and the coincidence output SA as two inputs. , And becomes a clock input of D-FF5c through the OR gate 33.
  • D-FF 5c is preset by SET-AB every time, when the short pulse AND-A-OUT ((16) in Fig. 6) is added to D-FF 5c as a clock input, As a result, the Q output of D-FF5c falls and appears at the output terminal OUT as a panorama P1 '.
  • this output pulse P 1 ′ is a pulse whose one cycle rises at the leading edge of the external input clock CK of T, and then falls at half the length T of one cycle (50% duty). I have.
  • RS—Set output Q of FF6 ((11) in Fig. 4) is input to AND gate 31 and is applied to A-side delay line oscillator 11 through OR gate 7 and oscillates it. Clear 17 and start counting the number of oscillation cycles.
  • the match circuit 28 again generates a match output SA.
  • this coincidence output S A is generated, the set output Q of RS-FF 6 ((11) in FIG. 6) falls and becomes the input of the AND gate 31 in the form of pulse P2.
  • the AND gate 31 having the pulse P 2 and the coincidence output SA as two inputs provides a short pulse at the leading edge of the coincidence output SA.
  • Lus AND—A—OUT (6 in FIG. 6) is generated, and becomes the clock input of D—FF 5c through the OR gate 33.
  • D-FF 5c is preset by SET-AB every time, when the short pulse AND-A-OUT ((16) in Fig. 6) is added to D-FF 5c as a clock input, At this point, the Q output of D-FF5c falls and appears as pulse P2 'at the output terminal OUT. Naturally, the output pulse P 2 ′ also rises at the leading edge of the external input clock CK and falls at a position where the duty is 50%.
  • the timing signal WC-B ((18) in FIG. 6) rises (point h in FIG. 6), and is added to the delay line oscillator 11 on the B side through the OR gate 9 to start oscillation and the counter 17
  • the counter 17 starts counting the number of oscillation cycles at the rising edge.
  • the oscillation of the B-side delay line oscillator 11 is at least the clock of the fourth cycle t4 Continue until the rise of the is completed.
  • the arithmetic circuit 19 on the ⁇ side receives the output of the latch circuit 18 and calculates half the count value of the length ⁇ of one cycle, that is, the timing position of 50% duty, and calculates the arithmetic result. Is output to one of the input terminals ⁇ 1 to ⁇ ⁇ of the matching circuit 28.
  • RS-FF 8 is set by the arrival of SET-B ((17) in FIG. 6) (point k in FIG. 6).
  • the set output Q of RS-FF 8 ((19) in Fig. 6) is input to the AND gate 32, and is also applied to the delay line oscillator 11 on the B side through the OR gate 9 to oscillate it. Starts the count operation in addition to CL of the counter 17 on the side.
  • the output of the counter 17 on the B side is input to the other input terminals A1 to An of the match circuit 28, and the count value of the counter 17 increases in a stepwise manner. At the moment when it matches the output value of 9 (half of the length T of one cycle) (point q in Fig. 6), the matching circuit 28 generates a match output SB.
  • the coincidence output SB is input to the reset input terminal QN of RS-FF8, and resets the flip-flop. Therefore, at the time when the coincidence output SB is generated, the set output Q of RS-FF 8 ((19) in FIG. 6) falls and becomes the input of the AND gate 32 in the form of the pulse P3. Therefore, the AND gate 32 having two inputs, the pulse P 3 and the coincidence output SB, generates a short pulse AND—B-OUT ((25) in FIG. 6) at the leading edge of the coincidence output SB.
  • the input is D_FF5c through the OR gate 33. Since D-FF 5c is preset by SET-AB every time, when the short pulse AND-B-OUT ((25) in Fig. 6) is added to D-FF 5c as a clock input, At this point, the Q output of D-FF5c falls and appears as pulse P3 'at the output terminal OUT.
  • this output pulse P 3 ′ is a pulse whose one cycle rises at the leading edge of the external input clock CK of T, and then falls at a position half the length T of one cycle (duty 50%). Since the coincidence pulse SB 1 ((22) in FIG. 6) generated in the third cycle t 3 is generated while the Q output of RS-FF 8 is low, the AND gate 32 No output, D-FF 5 c does not switch. Therefore, the effect of the coincidence pulse SB1, which occurs when the B side is in the measurement period (the QN pin of JK-FF is at the H level) is removed by the AND gate 31, and does not appear on the output OUT side.
  • a short pulse AND—B—OUT ((23) in FIG. 6) is generated at the leading edge of the coincidence output SB from the AND gate 32 having the pulse P4 and the coincidence output SA as two inputs.
  • the clock is input to the D-FF 5c through the OR gate 33.
  • D-FF 5c is preset by SET-AB every time, when the short pulse AND-B-OUT ((23) in Fig. 6) is added to D-FF 5c as a clock input, D— FF 5 c Q output falls, and the output terminal OUT Appears as P4 '. Naturally, this output pulse P4 ' also rises at the leading edge of the external input clock C # and falls at a position where the duty is 50%.
  • the output clocks ⁇ 1 ′, ⁇ 2 ′, P 3 ′, ⁇ 4 ′, ... synchronized with the input clock CK and having a duty of 50% are obtained from the Q output of the D-FF 5 c.
  • the above effects can be obtained even when the duty ratio of the input CK fluctuates around 50% or more, so it is very effective for shaping digital waveforms,
  • the operable area of the device can be extended to very high frequencies.
  • the frequency doubler 201 in FIG. 7 includes two sets of duty determining circuits 3 and 4 having the same configuration, and both circuits input clock signals to each other as shown in FIG. 8 as operating cycles Cl and C2. It operates alternately with a shift of two CK cycles.
  • the first duty determining circuit 3 is referred to as A side and the second duty determining circuit 4 is referred to as B side as required, and the reference numerals are appended with suffixes A and B to distinguish them.
  • the frequency doubling circuit 201 separates the target measurement sections T1A and TIB to be measured as the length of one cycle T from the input clock signal at intervals of an integral multiple of one cycle T of the input clock signal CK.
  • a timing generation circuit 2 for generating a required timing signal including the following.
  • the duty cycle determining circuits 3 and 4 receive and receive the timing signal to determine and designate a timing position of a 50% duty cycle of a clock signal to be output, wherein the duty cycle determining circuits 3 and 4 overlap at least one cycle with each other. It has a first duty determination circuit 3 and a second duty determination circuit 4 which operate with a shift by a period.
  • Each of the two duty determining circuits 3 and 4 includes a delay line oscillator 11, a counter 17 for counting the number of oscillations, and a latch for latching the contents of the counter 17.
  • the first matching circuit 222, the second matching circuit 223, and the third matching circuit 224 are provided for each of the circuits 219, 220, and 221.
  • the delay line oscillator 11 includes a NAND gate 12 having one input terminal as an input terminal of the oscillator, and an odd-numbered stage C-MOS inverter connected to the output terminal of the NAND gate 12 as a delay element. And a simple inverter 15 for inversion inserted in a feedback loop 14 from the output terminal of the inverter 13 to the other input terminal of the NAND gate.
  • an ECL inverter As the inverter 13 as a delay element, an ECL inverter, an IIL inverter, or the like can be used in addition to the C-MOS inverter.
  • the delay line oscillator 11 receives the timing signals WC-A and WC-B (actual measurement sections T3A and T3B) from the timing generation circuit 2 and starts oscillation for measurement at the rising edge and at the falling edge. Stop oscillation. That is, normally, the NAND gate 12 has one input terminal at the logic level L, the output at H, the inverter 13 at its output at L, and the inverter 15 at its output (the other input terminal of the NAND gate 12). H state and oscillation is stopped. Normally, when one of the input terminals of the NAND gate 12 is changed to the logic level H, the output of the NAND gate 12 is L, the output of the inverter 13 is H, and the output of the inverter 15 is H.
  • the rise of WC-A, WC-B is the same as the rise of timing signal 1 / 2CK (target measurement section T1A, TIB), and the fall is the same timing signal. Slightly behind the falling edge of 1 / 2CK.
  • the delay line oscillator 11 generates the rising edge of the timing signal 1 / 2CK obtained by dividing the input clock signal CK by 1/2 (for the target measurement sections T1A and T1B). Oscillation starts at the beginning), and stops after the fall of 1 / 2CK (after the end of the target measurement section T1A, TIB).
  • the clock input terminal CK of the counter 17 is connected to the output terminal of the delay line oscillator 11 and the output of the delay line oscillator 11 changes DL—OSC—A.
  • the output change that occurs twice is counted.
  • the same input signal as the delay line oscillator 11 described above, that is, the timing signals WC-A and WC-B (actual measurement sections T3A and T3B) are input to the clear terminal CL of the power counter 17. Is done.
  • the counter 17 starts counting at the rising edge of the timing signal 1 / 2CK (target measurement section T1A, TIB), in the same manner as the operation of oscillating and stopping the delay line oscillator 11; Stop counting after the falling edge of 2CK (target measurement section T1A, T1 B). Therefore, the count of the number of oscillation cycles is maintained during one period of the timing signal 1 / 2CK (target measurement section T 1 A, T 1 B).
  • the latch circuit 18 receives the digit output of the counter 17 as an input, and the timing signal 1/2 CK (target measurement section T1) created by the timing generation circuit 2 is input to the clock input terminal CK. .
  • the latch circuit 18 outputs the counter 1 Latch the count value of 7 (the number of oscillation cycles). Therefore, the latch circuit 18 counts the number of oscillation cycles corresponding to the length of one cycle section (one cycle T of the input clock signal CK) of the timing signal 1 / 2CK (target measurement section T1A, T1B). The value is latched.
  • the first arithmetic circuit 219, the second arithmetic circuit 220, and the third arithmetic circuit 221 each receive the parallel output of the latch circuit 18 and receive a 1/4 value of the latched oscillation frequency force value, Calculate the values of 2-4 and 3/4, that is, 25%, 50%, and 75% duty values. Of these, a 25% duty value is one input to the first match circuit 222, a 50% duty value is one input to the second match circuit 223, and 75. The duty value of / ⁇ is one input of the third-matching circuit 224.
  • the first matching circuit 222, the second matching circuit 223, and the third matching circuit 224 are respectively provided with the parallel output (calculation) of the first arithmetic circuit 219, the second arithmetic circuit 220, and the third arithmetic circuit 221.
  • One of the results 1/4 value, 2/4 value and 3 Z4 value) is used as the negative input, and the output of the counter 17 is used as the other input.
  • SR flip-flops (abbreviated as FF) 6 and 8 are respectively provided before the first duty determination circuit 3 and the second duty determination circuit 4.
  • FF flip-flops
  • the oscillation verification section T6A, T6B between the section and the next target measurement section it is set every time in synchronization with the leading edge of one cycle T of the input clock signal CK. Reset by A3 and SB3.
  • OR gates 7 and 9 are provided before each of the first duty determination circuit 3 and the second duty determination circuit 4, and the SR-FFs 6 and 8 are passed through the OR gates 7 and 9.
  • the signals WC-A and WC-B indicating the actual measurement section T3A and T3B and the duty-determining circuits 3 and 4 belonging to the force.
  • the reset signal is reset every time in synchronization with the leading edge of one cycle T of the input clock signal CK, and the match signals SA1, SA2, and SA2 obtained from the first duty decision circuit 3 and the second duty decision circuit 4 are obtained.
  • Status is switched by SA3 or SB1, SB2, SB3 Equipped with a flip-flop 5c for force.
  • the first duty-determining circuit 3 is preceded by RS-FF 6, and its Q output is supplied to the delay line oscillator of the duty-determining circuit 3 through the OR gate 7 (OR-A). 11 While being input to 1, it is input to one input terminal of the AND gate 31.
  • the output of the matching circuit 224 that is, the matching output with a duty of 75% is input to the reset terminal R of the RS-FF 6 preceding the output.
  • This RS-FF 6 constitutes a part of the width creating circuit 5 together with the output D-FF 5 c.
  • This RS-FF 6 is generated at the leading edge of the input clock signal CK when the QN ((8) in Fig. 8) of the JK-FF in the timing generation circuit 2 is H, that is, when the A side is in the oscillation verification section.
  • the pulses Pl and P2 generated at the output terminal Q of RS-FF6 in the third cycle t3 and the fourth cycle t4 are applied to one of the AND gates 31, and the pulses P1 and P2 are output.
  • the coincidence outputs SA1, SA2, 383 are applied to the clock input terminal CK of the presettable D-FF 5c through the 01 gate 33 (OR-2).
  • An RS-FF 8 and an OR gate 9 are provided in front of the second duty determining circuit 4 which is configured exactly the same as the first duty determining circuit 3 having such a configuration. Is input to the delay line oscillator 11 of the duty determination circuit 4 through the OR gate 9 (OR-B), and is input to one input terminal of the AND gate 31. The output of the matching circuit 28, that is, the output of the duty determination circuit 4 is input to the reset terminal R of the RS-FF 8 provided before the output.
  • This RS-FF8 also constitutes the width creation circuit 5 together with D-FF5c.
  • This RS-FF8 is generated at the leading edge of the input clock signal CK when the Q ((7) in Fig. 8) of the JK-FF in the timing generation circuit 2 is H, that is, when the B side is in the oscillation verification section. Is set by the short pulse SET-B ((16) in Fig. 8), and the last one of the above-mentioned coincidence signal SB ((23) in Fig. 8) same (See (18) in Fig. 8).
  • the pulses P3 and P4 generated at the output terminal Q of RS-FF8 at the fifth cycle t5 and the sixth cycle t6 are applied to one of the AND gates 32, and the pulses P3 and P4 are output.
  • the coincidence outputs SB1, SB2 and SB3 are applied to the clock input terminal CK of the presettable D-FF 5c through the OR gate 33 (OR-2).
  • the width creating circuit 5 has a presettable D-FF 5c, and its QN terminal and the D terminal are directly connected.
  • the preset input terminal PR receives the SET-A and SET-B signals (that is, SET-AB) through the OR gate 5d and the D-FF 5c clock input terminal CK.
  • Match outputs SA1, SA2, SA3 or SB1, SB2, SB3 are input via OR gate 33.
  • an AND gate 31 is provided to inhibit coincidence output during the measurement period. The AND with the Q output from FF6 and 8 is taken.
  • an AND gate 32 is provided in the line from the coincidence output terminals SB1, SB2, SB3 of the coincidence circuits 222, 223, 224 to the OR gate 33 to inhibit the coincidence output during the measurement period. , RS-ANDed with the Q output from FF6,8.
  • the timing generation circuit 2 internally generates the timing signals SET-AB, 1 / 2CK, 1 / 2CK-DL, WC, JK-FF-Q, JK-FF-QN, and further uses these signals. Creates and outputs timing signals SET-A, SET-B, 1 / 2CKA, 1 / 2CKB, WC-A, WC-B.
  • SET—AB ((3) in Figure 8) is a timing signal consisting of short pulses generated at the leading edge of the input clock signal CK.
  • 1 / 2CK ((4) in Fig. 8) is a timing signal to determine the section (target measurement section) T1 to be measured as the length of one cycle T of the input clock signal CK. Is a signal obtained by dividing the input clock signal CK by 12.
  • WC ((6) in Fig. 8) is a timing signal for establishing sections (actual measurement sections) T3A and T3B for maintaining the measurement operation over the target measurement section T1.
  • This WC is a signal whose fall is slightly delayed from the above 1 / 2CK, that is, a signal whose rise width is slightly longer than one cycle T of the input clock signal CK at the same time as the input clock CK.
  • This WC creates a signal 1 / 2CK-DL ((5) in Fig. 8) that is slightly delayed from 1 / 2CK within the width of 1/2 cycle, and ORs this with 1 / 2CK. This has been gained.
  • J K-FF-Q ((7) in Fig. 8) is the output Q signal of J K_FF in the timing generation circuit 2.
  • the A side is the measurement section
  • the B side is the oscillation verification JK-FFQN ((8) in Fig. 8) indicates that when the output QN of JK-FF in the timing generation circuit 2 is H, the B side is the measurement section (A side is the oscillation verification section)
  • SET-A ((9) in Fig. 8) is the input clock signal when the JK-FF QN ((8) in Fig. 8) in the timing generation circuit 2 is H, that is, when the A side is in the oscillation verification section.
  • This is a timing signal consisting of a short pulse generated at the leading edge of the signal CK.
  • SET-B ((18) in Fig. 8) is the input clock when the Q of JK-FF in the timing generator 2 ((7) in Fig. 8) is H, that is, when the B side is in the oscillation verification section.
  • This signal is a timing signal consisting of short pulses generated at the leading edge of the signal CK.
  • the 1 / 2CKA ((14) in Fig. 8) is a signal for establishing the target measurement section T1A on the A side, and the Q of the JK-FF in the timing generation circuit 2 ((7) in Fig. 8). ) Is H, that is, the signal obtained by extracting 1 / 2CK while the A side is in the measurement section (B side is in the oscillation verification section).
  • 1 / 2CKB ((20) in Fig. 8) is a signal for establishing the target measurement section T1B on the B side, and the QN of JK-FF in the timing generation circuit 2 ((8) in Fig. 8) ) Is H, that is, 1 / 2CK is taken while the B side is in the measurement section (A side is the oscillation verification section). This is the output signal.
  • the target measurement interval T1A, TlB to be measured as the length of one cycle ⁇ from the input clock signal CK is an integral multiple of one cycle T of the input clock signal CK, here a triple interval T6 A, T 6 It is caused to open B and instruct.
  • WC-A and WC-B are timing signals for the actual measurement sections T3A and T3B, and have a pulse width longer than T1.
  • the first duty decision circuit 3 treats every four cycles (4T) of the input clock signal CK as one repetition unit (operating cycle C1), and In the first cycle (tl), the length of one cycle of the input clock signal CK (target measurement section on the A side) T1A is measured, and 1/4, 2 / Calculate the values of 4 and 3/4 (timing positions of 25%, 50% and 75% duty) and, based on this, based on this, the third period (t3) and the fourth period (t4) of the latter half In this case, the length from the leading edge of the input clock signal CK to the position matching the calculated value, that is, the timing position of the duty of 25%, 50%, and 75% (Figure 8 shows the timing of the maximum 75% The length to the position is indicated by T5A), and when they match, the duty is 25%, 50%, 75% each time.
  • the second duty-one determining circuit 4 has its operation cycle C2 shifted from the first duty-one determining circuit 3 by two periods. That is, the second duty determination circuit 4 treats every four cycles of the input clock signal CK shown as t3 to t6 in FIG. 8 as one repetitive unit (operating cycle C2).
  • the length of one cycle of the input clock signal CK (target measurement section on the B side) T1 B is measured, and 1Z4, Calculate the values of 2/4, 3Z4 (timing position of duty 25%, 50%, 75%) and, based on this, the third period (t5) and the fourth period (t5)
  • the length from the leading edge of the input clock signal CK to the calculated value that is, the distance from the leading edge of the input clock signal CK to the timing positions of 25%, 50%, and 75%, respectively (Fig. Up to 75.
  • the length to the timing position of / o is indicated by T5B), and when they match, the coincidence signals SB1, SB2 indicating that the timing positions are at the duty of 25%, 50%, and 75% Outputs SB2 and SB3.
  • Figure 8 shows the operation of the main elements of the circuit of Figure 7.
  • the timing signal WC-A ((10) in Fig. 8) is passed through the OR gate 7 to the delay line oscillator 1 1 Is input to the counter 17 and the signal is input to the clear terminal CL of the counter 17.
  • the counter 17 starts counting the number of oscillation cycles. Oscillation of the delay line oscillator 11 continues at least until the start-up of the second period t2 is completed.
  • the arithmetic circuits 219, 220, and 221 receive the output of the latch circuit 18, and receive the values of 1/4, 2/4, and 34 of the count value of the length 1 of one cycle (25. / 0 , 50%, 75% duty timing), output the calculation result, and input it to one of the input terminals ⁇ 1 to ⁇ of the matching circuits 222, 223, 224.
  • RS-FF6 is set by the arrival of SET-A ((9) in Fig. 8) (point d in Fig. 8).
  • the set output Q ((11) in FIG. 8) of RS-FF6 is input to the AND gate 31 and is applied to the delay line oscillator 11 on the A side through the OR gate 7 to oscillate this.
  • the set output Q of the RS-FF 6 is added to the clear CL of the counter 17 on the A side through the OR gate 7 and is cleared, so that the count of the number of oscillation cycles is opened.
  • the output of the counter 17 is input to the other input terminals A1 to An of the matching circuits 222, 223, and 224, and the count value of the counter 17 increases in a stepwise manner.
  • 220, 221 e1, e2, e3 in Fig. 8 at the moment when the output values of (1/4, 2/4, 3Z4 values of the length T of one cycle) match Point
  • the match circuits 222, 223, 224 generate match outputs SA1, SA2, SA3 each time.
  • the largest SA3 of the coincidence outputs SA1, SA2, and SA3 is input to the reset input terminal R of RS-FF6 to reset the flip-flop.
  • the output Q of RS-FF6 ((11) in FIG. 8) falls and becomes the input of the AND gate 31 in the form of the pulse P1.
  • the AND gate 31 having two inputs, the pulse P1 and the coincidence outputs SA1, SA2, and SA3, outputs the coincidence outputs SA1, SA2, and SA3 only within the width of the pulse P1. — Generated as OUT ((17) in Figure 8) and passed through OR gate 33 to D—FF 5c clock input.
  • S A3 is a short pulse generated at the leading edge of the coincidence output S A3.
  • the output flip-flops D-FF5c are preset by SET-A or SET-B (that is, SET-AB) each time, so they correspond to the above-mentioned matched outputs SA1, SA2, and SA3.
  • SET-A or SET-B that is, SET-AB
  • the Q output of D— FF 5 c is inverted each time, and pulse xl, Appears as x2.
  • this output pulse xl, x2 is a digital signal whose one cycle rises in synchronization with the leading edge of the external input clock CK of T and whose frequency is double, and the output waveform is one cycle long.
  • the AND gate 31 having two inputs, the pulse P1 and the coincidence output SA, outputs the coincidence outputs SA1, SA2, and SA3 only within the width of the pulse P1. 8 (17)), and becomes the clock input of D — FF 5 c through the OR gate 33.
  • DF F 5 c is preset every time by SET-AB, so the short pulse AND— A— OUT ((17) in FIG. 8) corresponding to the coincidence output SA1, SA2, and SA3 is D—FF5c
  • the Q output of D-FF5c is inverted at that point and appears as pulses x3 and x4 at the output terminal OUT.
  • these output pulses x3 and x4 are also digital signals whose one cycle rises in synchronization with the leading edge of the external input clock CK of T and whose frequency is doubled, and the output waveform has the length of one cycle. Just half (duty 50%) of the input waveform The pulse falls at the position of 14 T in the period.
  • the timing signal WC-B ((19) in Fig. 8) rises (point h in Fig. 8), and is added to the delay line oscillator 11 on the B side through the OR gate 9 to start oscillation and the counter 17
  • the counter 17 starts counting the number of oscillation cycles at the rising edge.
  • the oscillation of the B-side delay line oscillator 11 continues at least until the rising edge of the clock in the fourth cycle t4 is completed.
  • the arithmetic circuits 219, 220, and 221 on the ⁇ side receive the output of the latch circuit 18 and calculate the 1Z4 value, the 24 value, and the 3-4 value of the count value of the length 1 of one cycle ( 2 5%, 50%, 75% duty timing), output the calculation result, and input to one of the input terminals ⁇ 1 to ⁇ ⁇ of matching circuits 222, -223, 224 I do.
  • RS-FF8 is set by the arrival of SET-B ((18) in FIG. 8) (in FIG. 8).
  • RS—FF8 Q output ((20) in Figure 8) is AN The signal is input to the D gate 32 and is applied to the delay line oscillator 11 on the B side through the OR gate 9 to oscillate it, and is also applied to the clear CL of the counter 17 on the B side to start the count operation.
  • the output of the counter 17 on the B side is input to the other input terminals A;! To An of the matching circuits 222, 223, and 224, and the count value of the counter 17 increases step by step.
  • the largest SB3 among the coincidence outputs SB1, SB2 and SB3 is input to the reset input terminal R of RS-FF8, and resets the flip-flop. Therefore, when the coincidence output SB3 is generated, the Q output of RS-FF8 ((20) in FIG. 8) falls and becomes the input of the AND gate 32 in the form of the pulse P3.
  • the coincidence outputs SB1, SB2, and SB3 are output from the AND gate 32, which has the pulse P3 and the coincidence outputs SB1, SB2, and SB3 as two inputs.
  • AND—B—OUT (FIG. 8) (24)), and becomes the D-FF 5c clock input through the OR gate 33.
  • SB3 is a short pulse generated at the leading edge of the coincidence output SB3.
  • D—FF 5 c is preset by SET—AB each time, the short pulses AND—B—OUT ((24) in FIG. 8) corresponding to the coincidence outputs SB1, SB2, and SB3 are D—FF
  • the Q output of D-FF 5c falls at that point and appears as pulses yl, y2 at the output terminal OUT.
  • the output pulses yl and y2 are digital signals whose -1 period rises in synchronization with the leading edge of the external input clock CK of T and whose frequency is doubled, and the output waveform has a length of one period ( It is a pulse that falls at a position that is exactly half (duty: 50%) of half of the original one cycle (12T), that is, 1 Z4T of the cycle of the original input waveform.
  • coincidence pulses SB1, SB2, and SB3 generated in the third cycle t3 (Fig. 8
  • RS-FF8 is reset by this coincidence output SB1, SB2, SB3, so the Q output of RS-FF8 ((20) in Fig. 8) falls, and AND in the form of pulse P4. Input to gate 32.
  • SB 1 and SB 2 occur before SB 3.
  • the coincidence outputs SB1, SB2, and SB3 are output only within the width of the pulse P4. It is generated as AND—B—OUT ((24) in FIG. 8) and becomes the clock input of D—FF 5c through OR gate 33.
  • the output pulses y3 and y4 are also digital signals whose one cycle rises in synchronization with the leading edge of the external input clock CK of T and whose frequency is doubled, and the output waveform is just half the length of one cycle. (The duty is 50%), that is, the falling edge at the position of 1 to 4 mm in the period of the original input waveform.
  • Figures 9 and 10 show the external synchronization circuit divided into left and right.
  • the external synchronization circuit receives the timing signals from the timing generation circuits 301 and 302 and the timing generation circuits 301 and 302, and receives an external trigger signal EXT—TRIG (the first one) in one cycle T of the input clock signal EXT—CK. 4) Measure the phase position from Fig. (1)) and create a reference internal trigger signal I NT-TR IG at the phase position corresponding to the phase position where the EXT-TR IG arrives at the next one cycle T.
  • the first timing generating circuit 301 receives the external trigger signal EXT—TR IG (FIG. 4 (1)) and converts the external trigger signal EXT—TR IG into a reference external trigger signal TR that is converted to a fixed pulse width.
  • IG—AB Fig. 4 (8)
  • one section (A section) defined by the arrival of the external trigger signal EXT—TR IG is called the next section (B section).
  • Generates and outputs external trigger section signals TRIG-STOP A, TRIG-STOP B D-FF-Q in Fig. 4 (2), D-FF-QN in Fig. 4 (3) for distinction.
  • the internal trigger signal generation circuit 310 receives the external trigger signal EXT—TR IG every time it is input.
  • the two system A and B internal trigger signals TR IG—A and TR IG—B (Fig. 5 (25) (26)), the second timing signal generating circuit 311, the first and second phase position providing circuits 312, 313, and the two phase position providing circuits 312, 313.
  • the timing generation circuit 301 detects the phase position from the leading edge within one cycle T of the input clock signal EXT—CK so that it is possible to know the phase position counted from the external trigger signal.
  • Create timing signals CK FA and CKFB phase position measurement section signals (Fig. 4 (10) (11)) indicating the measurement section.
  • the phase position measurement section signals CK FA and CKFB rise in synchronization with the input clock signal EXT-CK and fall within one cycle T of the input clock signal EXT-CK (pulse width T 2 in Fig. 4). It is. This is used so that the position can be measured and grasped regardless of the position of the external trigger signal EXT-TRIG at any position within one cycle T of the input clock signal EXT-CK.
  • CKFA and CKFB have a signal with the largest possible duty ratio (duty unit is 50% or more) so that the entire system within one cycle T can be covered by the two systems of CKF A and CKFB with the least number. ), And the phases are shifted by 180 °.
  • phase position measurement section signals CKFA and CKFB shift the phase position of the input clock signal EXT-CK little by little to DL1, DL2 and DL3.
  • CKFA is created by ORing and CKFB is created by ANDing.
  • the input clock signal EXT—CK is divided and its phase position is shifted slightly.
  • the phase position measurement section signals CK FA and CKFB whose basic unit is twice or more the period can be used.
  • the first and second phase position assigning circuits 312 and 313 have exactly the same configuration, and each includes a delay line oscillator 314, a counter 320 for counting the number of oscillations, and a counter for the counter.
  • 3 A latch circuit 3 2 1 that latches the content of 20 at the timing position (Gl, G2, G3 or G4 in Fig. 12) where the reference external trigger signal TR IG—AB is generated, and the latched value (xl , X2,..., Yl, y2,7)
  • the matching circuit 322 that generates an output when the output value of the counter 320 matches, and the phase position latched by the latch circuit 321 is inappropriate.
  • the output of the latch circuit is used to output a match stop signal.
  • An AND gate 324 having two inputs, the output of the gate 323 and the output of the matching circuit 322, is provided. Then, the phase position measurement section signal CKFA from the timing generation circuit 301 is input to the delay line oscillator 3 14 of the first phase position provision circuit 3 12, and the second phase position provision circuit 3 1 3 The phase position measurement section signal CKFB from the timing generation circuit 301 is input to the delay line oscillator 314.
  • the delay line oscillator 314 includes a NAND gate 315 having one input terminal as an oscillator input terminal, and an odd-numbered C-MOS inverter connected as a delay element to an output terminal of the NAND gate 315. And a simple inverter 3 inserted in the feedback loop 3 17 from the output terminal of the inverter 3 16 to the other input terminal of the NAND gate 3 15 It is composed of 1 and 8.
  • the delay element As the inverter 316, an ECL inverter, an IIL inverter and the like can be used in addition to the C-MOS inverter.
  • the delay line oscillator 314 receives the phase position measurement section signals CKFA and CKFB (FIGS. 4 (10) and (11)) from the timing generation circuit 301, starts oscillation for measurement at the rising edge, and falls. To stop oscillation. That is, normally, the NAND gate 315 has one input terminal at the logic level L, the output at H, the inverter 316 at its output at L, and the inverter 318 at its output (the other of the NAND gate 315). Input terminal is in the H state, and oscillation is stopped.
  • the clock input terminal CK of the counter 320 is connected to the output terminal of the delay line oscillator 314, and the output of the delay line oscillator 314 changes DL-OSC1 and DL-OSC2, that is, 1 for every cycle of oscillation. Output changes that occur multiple times are counted.
  • the same input signal as the delay line oscillator 314, that is, the phase index signals CKFA and CKFB is input to the clear terminal CL of the counter 320. Therefore, the counter 320 starts counting at the rising edge of the timing signals CKFA and CKFB, and stops counting at the falling edge of the timing signals CKFA and CKFB, similarly to the operation of oscillating and stopping the delay line oscillator 314.
  • the latch circuit 321 receives the digit output of the counter 320 as an input, and a clock input terminal CK receives the reference external trigger signal TRIG-AB generated by the timing generation circuit 301. Therefore, the latch circuit 321 counts the counter 320 when the reference external trigger signal TRI G-AB rises, that is, when the external trigger signal arrives (point G1, G2, G3 or G4 in FIG. 12). 02321
  • the latch circuit 321 has a force value of the number of oscillation cycles (the phase position X at which the external trigger signal arrives) counted from the rising of the input clock signal CK to the arrival of the reference external trigger signal TRI G-AB. Or y) is latched.
  • the matching circuit 322 has the parallel output of the latch circuit 321 as one input and the output SA of the counter 320 as the other input. Then, the coincidence circuit 322 outputs the coincidence signal SA when the count value of the power counter 320 increases to the output value of the latch circuit 321 (the phase position X or y at which the external trigger signal arrives).
  • the coincidence signal SA is taken out of the AND gate 324 while the output of the OR gate 323 (FIG. 4 (17)) is H, and the signal FSA 1 (pulse xl, x2, x3 ⁇ ) or FSB 1 (pulses y1, y2, ⁇ 3 ⁇ in (21) of Fig. 13), and are synthesized as a reference internal trigger signal INT_TRIG through an OR gate 325 to form a logic gate unit 326 Sent to Then, the reference internal trigger signal INT-TR IG passes through the logic gate section 326 to be extracted as the internal trigger signals TR IG-A and TRI IG-B into the A section and the B section (fifth section). Figures (25) and (26)).
  • an external trigger signal E XT An internal trigger signal generated in synchronization with the TRIG TR I-G_A and TRIG-B (Fig. 5 (25) (26)) were obtained.
  • FIG. 14 shows the circuit configuration of the timing generation circuit 302.
  • This third timing generation circuit 302 is a timing signal 1 / 2CK—A1 / B1, Create 1 / 2CK-A2 / B2, WC-A1 / B1, WC-A2 / B2, and give them to the duty decision circuits 3A, 4 inputs and 38, 4B.
  • each of the A system and the B system includes two duty determining circuits 3 and 4, respectively, the two duty determining circuits 3 and 4 constituting the A system and the B system, respectively.
  • a timing signal BLOCK—SEL for selecting one of the two alternatives is created, and this signal is inserted into each of the duty decision circuits 3A, 4A, 3B, and 4B.
  • 1 / 2CK-A1 / B1 ((9) in Fig. 15) and 1 / 2CK-A2 / B2 ((6) in Fig. 15) are measured as the length of one cycle T of the input clock signal CK.
  • Power section (target measurement section) This is a timing signal for determining T1, and specifically, a signal obtained by dividing the input clock signal CK by one to two.
  • WC-A1 / B1 ((11) in Fig. 15) and WC-A2 / B2 ((8) in Fig. 15) are sections for maintaining the measurement operation over the target measurement section T1 (actual measurement section). This is a timing signal for establishing T3.
  • WC—A1 / B1 and WC—A2 / B2 are signals that fall slightly later than 1/2 CK, that is, one cycle T of the input clock signal CK and the rising width at the same time as the input clock signal CK. It is a slightly longer signal.
  • This WC produces signals DL-AB1 ((10) in Fig. 15) and DL-AB2 ((7) in Fig. 15) that are slightly delayed from 1 / 2CK within the width of 1/2 cycle. This is obtained by ORing this with 1 / 2CK-A1 / B1 and 1 / 2CK-A2 / B2.
  • BLOCK—SEL ((12) in Figure 15) is inverted at the falling edge of the JK—FF output Q signal in the timing generation circuit 302, that is, the input signal EXT—CK every two cycles. This signal is used as an operation circuit switching signal for switching and using the duty one decision circuits 3 and 4.
  • This operation circuit switching signal B LOCK — SEL is used to determine the duty cycle of the duty-one determination circuit 3 (A1 / B1 side) during the measurement interval (duty determination circuit 4 (A2 / B2 side) when the output Q is H.
  • the duty determination circuit 4 side (A2 / B2 side) is the measurement section
  • duty 1 determination circuit 3 side (A1 / B1 side) is the oscillation verification section. ).
  • Mode switching signal creation circuit 330 The operation circuit switching signal B LOCK-SEL of the timing generation circuit 302 is a data input terminal D of D-FF 331, 332 (D-FF-RA, DF F-RB) constituting the mode switching signal generation circuit 330.
  • the internal trigger signals TRIG-A and TRIG-B are input to the clock input terminals CK of the D-FFs 331 and 332, respectively.
  • the D-FF 331 has an AND gate 333 connected to the QN output terminal and an AND gate 334 connected to the Q output terminal.
  • Each of the AND gates 333 and 334 has an internal trigger signal TRIG- A and the external trigger section signal TRI G-ST OP A are input.
  • the D-FF 332 has an AND gate 335 connected to the QN output terminal and an AND gate 336 connected to the Q output terminal. Both AND gates 335 and 336 have an internal trigger signal TRIG-B, respectively. And the external trigger section signal TRIG-STOP B are input.
  • AND gates 333, 334 are SET-Al, SET-A2 ((17) (15) in Fig. 15)
  • Power AND gates 335, 336 are SET-B1, SET-B2 ((21) and (20) in Fig. 15) are extracted.
  • the internal trigger signal is a timing signal consisting of a short pulse generated at the leading edge of the TRIGA, and the A1 side (the duty determination circuit 3A side) ) RS-FF6 set input.
  • the internal trigger signal TRIG is a timing signal consisting of a short pulse generated at the leading edge of A, and is set to RS-FF8 on the A2 side (duty-one determination circuit 4A side). Input.
  • SET-B 1 ((21) in Fig. 15) is used when the operation circuit switching signal BLOCK-SEL ((12) in Fig. 15) from the timing generation circuit 302 is L (A1 / B1 side performs oscillation verification).
  • this is a timing signal consisting of a short pulse generated at the leading edge of the internal trigger signal TRIG-B.
  • the RS-FF 6 on the ⁇ 1 side (duty-one decision circuit 3 ⁇ side) Becomes a set input.
  • S ⁇ - ⁇ 2 ((20) in Fig. 15) indicates that the operation circuit switching signal B LOCK-SEL ((12) in Fig. 15) from the timing generation circuit 302 is ⁇ In section ⁇ 6), this is a timing signal consisting of a short pulse generated at the leading edge of the internal trigger signal TRIG-—.
  • RS-FF 8 on the ⁇ 2 side (duty-one decision circuit 4 ⁇ side) Becomes a set input.
  • the duty determination circuits 3 and 4 are one set, and two sets of duty determination circuits 3 3, 4 ⁇ , 3 ⁇ , and 4 ⁇ are provided.
  • the delay line oscillator 41 includes a NAND gate 42 having one input terminal as an input terminal of the oscillator, an odd-numbered stage C-MOS inverter 43 connected as a delay element to an output terminal of the NAND gate 42, It is composed of a simple inverter 45 for inversion inserted in a feedback loop 44 from the output terminal of the inverter 43 to the other input terminal of the NAND gate.
  • the inverter 43 as a delay element, an ECL inverter, an IIL inverter, and the like can be used in addition to the C-MOS inverter.
  • the delay line oscillator 41 receives a timing signal WC—A1 / B1, WC-A2 / B2 (actual measurement section T3) from the timing generation circuit 302, and starts oscillation for measurement at its rising edge. Oscillation stops at the falling edge. That is, normally, the AND gate 42 has one input terminal at a logic level L, an output at H, an inverter 43 at its output L, and an inverter 45 at its output (N AND gate 42 The other input terminal is in the H state, and oscillation is stopped.
  • the rising of this WC-A1 / B1, WC-A2 / B2 is the rising of the timing signal 1 / 2CK-A1 / B1, 1 / 2CK-A2 / B2 (target measurement section T1).
  • the fall is slightly delayed from the fall of the same timing signal 1 / 2CK-A1 / B1, 1 / 2CK-A2 / B2.
  • the delay line oscillator 41 generates the rising edge of the timing signal 1/2 CK—A1 / B1 and 1 / 2CK—A2 / B2 obtained by dividing the input clock signal CK by 1/2 (the target measurement section T 1 The oscillation starts at the beginning of) and stops after the fall of 1 / 2CK-A1 / B1, 1 / 2CK-A2 / B2 (after the end of the target measurement section T1).
  • the counter 47 has its clock input terminal CK connected to the output terminal of the delay line oscillator 41, and generates a change in the output DL—OSC—A of the delay line oscillator 41, that is, once for each round of oscillation. The output change is counted.
  • the same input signal as the delay line oscillator 41 that is, the timing signals WC—A1 / B1, WC—A2 / B2 (actual measurement section T3) is input to the clear terminal CL of the counter 47 through the line 46. . Therefore, the counter 47 starts the timing signal 1 / 2CK—A1 / B1, 1 / 2CK-A2 / B2 (target measurement section T1) at the time when the timing signal 1 / 2CK rises, similarly to the operation of oscillating and stopping the delay line oscillator 41. Starts counting and stops counting after the timing signal 1 / 2CK—A1 / B1, 1 / 2CK-A2 / B2 (target measurement section T 1) falls.
  • (c) Latch circuit 48 The latch circuit 48 receives the digit output of the counter 47 as an input.
  • the clock input terminal CK has the timing signals 1/2 CK-A1 / B1, 1 / 2CK—A2 / B2 generated by the timing generation circuit 302. (Target measurement section T1) has been entered.
  • the latch circuit 48 falls at the timing signal 1 / 2CK—A1 / B1, 1 / 2CK—A2 / B2 (the target measurement section T 1), that is, when the target measurement section T 1 ends, Latch the count value of counter 47 (the number of oscillation cycles). Therefore, the latch circuit 48 has the length of one cycle section of the timing signal 1 / 2CK-A1 / B1, 1 / 2CK-A2 / B2 (target measurement section T1) (one cycle T of the input clock signal CK). The count value of the number of oscillation cycles corresponding to is latched.
  • the arithmetic circuit 49 receives the parallel output of the latch circuit 48 and calculates a 1Z2 value of the latched oscillation round count value, that is, a 50% duty cycle value. This 50% duty value is one input of the matching circuit 50.
  • the matching circuit 50 uses the parallel output (1/2 value of the calculation result) of the arithmetic circuit 49 as one input and the output of the counter 47 as the other input.
  • the coincidence circuit 50 outputs coincidence signals SA and SB when the count value of the counter 47 increases to a value that matches the operation result.
  • the duty determination circuit 3A receives the match signal SA1
  • the duty determination circuit 4A receives the match signal SA2
  • the duty determination circuit 3B receives the match signal SB1, and the duty cycle.
  • the decision circuit 4B outputs the coincidence signal SB2.
  • RS-FFs 6 and 8 are provided before the duty determination circuits 3 and 4 of each set of A and B, respectively.
  • the RS-FFs 6 and 8 are connected to the target measurement section and the next target measurement section, respectively.
  • the signals are set every time in synchronization with the above-mentioned signals SET-A1, SET-A2, SET-Bl, SET-B2, and the coincidence signals SA1, SA2, SB1, Reset by SB 2.
  • the RS-A1 and B1 The FFs 6 and 6 are set every time in synchronization with the above-mentioned signals SET-Al and SET-B1, and are reset by the coincidence signals SA1 and SB1.
  • the RS-FFs 8 and 8 on the A2 side and the B2 side are set each time in synchronization with the above-mentioned signals SET-A2 and SET-B2, and reset by the coincidence signals SA2 and SB2.
  • OR gates 7 and 9 are provided in front of each of the duty determination circuits 3 and 4 of each set of A and B. Through the OR gates 7 and 9, the outputs of the SR-FFs 6 and 8 and the actual measurement The signals WC—Al / Bl and WC-A2 / B2 indicating the section T3 are input to the duty determination circuits 3 and 4 to which they belong.
  • the ⁇ ⁇ creating circuit 5 is reset every time in synchronization with the signals SET-A1, SET-A2, SET-Bl, SET-B2.
  • An output flip-flop (D-FF) 54 whose state is switched by the obtained coincidence signals SA1, SA2, SB1, and SB2 is provided.
  • the first duty determining circuit 3A is preceded by RS-FF6.
  • the Q output is input to the delay line oscillator 41 of the duty-one determination circuit 3 through the OR gate 7 (OR-A 1) and to one input terminal of the AND gate 51.
  • the output of the match circuit 50 that is, the match output of 50% duty is input to the reset terminal R of the RS-FF 6 preceding the output, and the AND gate 51 and the OR Through the gate 53, it is input to the clock input terminal CK of D-FF54.
  • the D-FF 54 and the RS-FF6 together constitute a part of the width creating circuit 5.
  • This RS-FF 6 (RS-FF-A1-Q; (10) in Fig. 17) indicates that when Q of JK-FF in the timing generation circuit 302 is L, that is, when the A1 side is the oscillation verification section. Is set by the short pulse SET-A1 ((6) in Fig. 17) generated in synchronization with the internal trigger signal TRIG-A, and is set by the match signal SA1 ((13) in Fig. 17). It is reset (see (10) in Figure 17).
  • RS-FF 6 (RS-F F—Al—Q;
  • the coincidence signal SA 1 passes through the AND gate 51 due to the pulses P 3 and P 4 generated at the output terminal Q of (10) in FIG. 17 (AND—A 1; (14)), and becomes the D-FF 54 clock input for output through the OR gate 53. Therefore, the output terminal (OUT) of the output D-FF 54 is set up by the SET-A1 generated at the k and r points in Fig. 17 and the coincidence signal S Al (AND- Al; Pulses P 3 ′ and P4 ′ falling by (14) in FIG. 17 appear.
  • RS-FF 8 and OR gate 9 are provided in front of the second duty determination circuit 4 A configured exactly the same as the first duty determination circuit 3 # having this configuration,
  • the Q output is input to the delay line oscillator 41 of the duty determination circuit 4 A through the OR gate 9 (OR-A 2) and to one input terminal of the AND gate 52.
  • the output of the match circuit 50 that is, the match output of 50% of the duty of the duty determination circuit 4A is input to the reset terminal R of the RS-FF 8 preceding the output of the match circuit 50, and The signal is input to the clock input terminal CK of the D-FF 54 through the gate 52 and the OR gate 53.
  • the RS-FF 8 also forms the width creating circuit 5 together with the OR gate D-FF 54.
  • This RS-FF 8 (RS-FF-A2-Q; (17) in Fig. 17) indicates the timing when the timing of JK-1 FF in the generator circuit 302 is H, that is, the A2 side is the oscillation verification section. Is set by the short pulse SET-A2 ((7) in Fig. 17) generated in synchronization with the internal trigger signal TRIG-A, and the match signal SA2 ((19) in Fig. 17) ) (See (17) in Figure 17).
  • the pulses P1 and P2 generated at the output terminal Q of RS-FF8 (RS-A2-Q; (17) in Fig. 17) in the second cycle t2 and the third cycle t3 in Fig. 17 can be expressed as follows.
  • Two match signals SA2 will be generated.
  • the coincidence signal SA2 passes through the AND gate 52 (AND-A2; (20) in FIG. 17), and becomes the clock input of the output D-FF 54 through the OR gate 53. Therefore, the output terminal (OUT) of the output D-FF 54 rises due to SET-A2 generated at points d and f in Fig. 17 and the coincidence signal SA generated at points e and g in Fig. 17 2 (Accurately, the output AND— A 2; Pulses P 1 and P 2 ′ falling due to (20)) appear.
  • the second SET-A2 occurs because the second external trigger signal EXT-TRIG (G2 in Fig. 17) has arrived at the sixth cycle t6. No (see (15) in Fig. 15 and (7) in Fig. 17). Therefore, the second pulse P 2 (shown by a dotted line) does not occur.
  • the pre-FF and pre-OR gate for the duty decision circuits 3 and 4 (3 B, 4 B) of the B system (B side) are also configured in the same manner as above. That is, RS-FF 6 is prefixed to the first duty determination circuit 3B, and its Q output is supplied to the delay line oscillation circuit of the duty determination circuit 3B through the OR gate 7 (OR-B1). And input to one input terminal of the AND gate 51.
  • the output of the matching circuit 50 that is, the matching signal SB1 with a duty of 50% is input to the reset terminal R of the RS-FF6 preceding the signal, and the AND gate 51 and the OR gate 53 Through the clock input terminal CK of D-FF54.
  • the D-FF 54 and the RS-FF 6 together form a part of the width creating circuit 5. .
  • This RS-FF 6 (RS-FF-B 1-Q; (22) in Fig. 18) is used in the timing generation circuit 302: ? ⁇ 3, that is, when the B1 side is in the oscillation verification section, the short pulse SET-B1 generated in synchronization with the internal trigger signal TRIG-B ((18) in Fig. 18) Set and reset by the match signal SB1 ((24) in Fig. 18) (see (22) in Fig. 18).
  • RS-FF6 (RS-FF-B1-Q; (22) in Fig. 18)-occurs at the output terminal Q at t8 in the eighth cycle and t9 in the ninth cycle in Fig. 18.
  • the —Signal signal SB 1 passes through the AND gate 51 (AND—B 1; (25) in FIG. 18), and the clock input of the D—FF 54 for output through the OR gate 53 .
  • the output terminal (OUT) of the D_F F54 for output is connected to the coincidence signal SB generated at points q 2 and s 2 by rising from SET-B 1 generated at points k 2 and r 2 in FIG. Pulses P 7 ′ and P 8 ′ appearing at 1 (exactly AND—B 1; (25) in FIG. 18) appear.
  • the second duty determination circuit 4B is provided with an RS-FF 8 and an OR gate 9 in front thereof, and its Q output Is input to the delay line oscillator 41 of the duty determination circuit 4B through the OR gate 9 (OR-B2) and to one input terminal of the AND gate 52.
  • the output of the match circuit 50 that is, the match output of 50% duty of the duty-one determination circuit 4B is input to the reset terminal of the RS-FF8 preceding the output, and the AND gate
  • the clock is input to the clock input terminal CK of the D-FF 54 through the 52 and the OR gate 53.
  • This RS-FF8 also constitutes the width creating circuit 5 together with the OR gate D-FF54.
  • This RS-FF 8 (RS-FF-B 2 -Q; (27) in Fig. 18) indicates that when Q of JK-FF in the timing generation circuit 302 is H, that is, the B2 side is the oscillation verification section. Is set by the short pulse SET-B2 ((26) in Fig. 18) generated in synchronization with the internal trigger signal TRIG-B when the match signal SB2 ((29) in Fig. 18) Reset (see (27) in Figure 18).
  • the coincidence signal S A2 passes through the AND gate 52 (AND-B2; (20) in FIG. 17), and becomes the clock input of the D-FF 54 for output through the OR gate 53. Therefore, the output terminal (OUT) of the D-FF 54 for output rises due to SET-B2 generated at the d2 and f2 points in Fig. 18 and is generated at the e2 and g2 points in Fig. 18.
  • the falling pulses P 5 ′ and P 6 ′ appear due to the coincidence signal SB 2 (more precisely, the output AND—B 2; (30) in FIG. 18).
  • the pulse P 5 ′ is continuous with the previous pulse P 1 ′, It's getting longer.
  • the width creating circuit 5 has a presettable D-FF 54, and its QN terminal and the D terminal are directly connected.
  • the signals of SET-Al, SET-A2, SET-Bl, and SET-B2 are input to the preset input terminal PR via the OR gate 55, and the clock input terminals CK
  • the match outputs SA1, SA2, SB1, and SB2 are input to OR through the OR gate 53.
  • an external trigger signal EXT-TRIG (trigger G3 in Fig. 18) arrives immediately after the RS-FF6 or RS-FF8 Q output rises, that is, resets RS-FF6 or RS-FF8. If the external trigger signal EXT—TR IG arrives before the coincidence signals SA1, SA2, SB1, and SB2 are generated, the correct coincidence signal counted from the new external trigger signal EXT—TR IG (Fig. 18 Prior to the occurrence of point e at point 3), the older coincidence signal (point w in Fig. 18) occurs earlier in time, causing the Q output of D-FF 54 to fall.
  • EXT-TRIG Trigger G3 in Fig. 18
  • the external trigger section signal TR IG—S TOP A is applied to the input of the AND gates 51 and 52 of the ⁇ system, and the external trigger is input to the inputs of the AND gates 51 and 52 of the B system.
  • the partition signal TR IG—STOP B is added.
  • the first duty decision circuit 3 and the second duty—decision circuit 4 constituting each of the sets A and B are connected to each other as shown in FIGS. 17 and 18 as operation cycles C1 and C2. It operates alternately with a shift of two CK cycles. Then, when one group, for example, the group on the A side is processing, the external trigger signal EXT-TR I If the processing cannot be made in time due to the arrival time of G, the processing is automatically transferred to the other group on the B side.
  • the system is automatically switched between the A system and the B system every time the external trigger signal EXT-T RIG arrives.
  • the second duty-one decision circuit 4 A on the A side treats every four cycles (4T) of the input clock signal CK as one unit of repetition (operation cycle C 1),
  • the length of one cycle of the input clock signal CK (the target measurement section on the A2 side) T1 is measured in the first cycle (tl) of the first half of the period.
  • the value of 12 of the length T of one cycle (timing position of 50% duty) is calculated in advance.
  • the time when the signal SET-A2 synchronized with the internal trigger signal TRIG-A is generated (point d in Fig. 17) , Point)
  • the delay line oscillator 41 is oscillated, and the length ⁇ 5 is measured until it matches the above calculated value, that is, the timing position of the duty 50% is reached.
  • a coincidence signal SA2 points e and g in Fig. 17) indicating that the duty position is at the 50% timing position is output.
  • the first duty determining circuit 3A on the A side has its operation cycle C2 shifted by two cycles from the first duty determining circuit 3. That is, the first duty determination circuit 4 treats every four cycles of the input clock signal CK shown as t3 to t6 in FIG. 10 as one unit of repetition (operation cycle C2), and At the first cycle (t 3), the length of one cycle of the input clock signal CK (target measurement section) T 1 is measured, and the measurement result is used to calculate the value of 12 of the length T of one cycle (duty 50 % Timing position). In the subsequent fourth period (t 4) and fifth period (t 5) of the second half, the time when the signal SET-A 1 synchronized with the internal trigger signal TRIG-A is generated (points k and r in FIG. 17). ), The delay line oscillator 41 is oscillated.
  • the first external trigger signal G1 arrives at the first cycle t1 of the input clock signal CK.
  • the timing signal WC-A2 / B2 ((16) in Fig. 17) is input through the ⁇ R gate 9 to the duty cycle determining circuit 4A and the delay line oscillator 41 of 4B. Then, each of the delay line oscillators 41 starts oscillating, and is input to the clear terminal CL of the power counter 47. At the rising edge, the counter 47 starts counting the number of oscillations. Oscillation of the delay line oscillator 41 continues at least until the rising of the clock of the second cycle t2 is completed.
  • the arithmetic circuit 49 receives the output of the latch circuit 48, calculates the value of 12 of the force value of one cycle length (the timing position of the 50% duty), and outputs the calculation result. Then, the signals are input to one of the input terminals ⁇ 1 to ⁇ ⁇ of the matching circuit 50. (ii) 4 A side 2nd cycle t 2
  • RS-FF8 is set by the arrival of SET-A2 ((7) in Fig. 17) (point d in Fig. 17).
  • the Q output of RS-FF 8 ((17) in FIG. 17) is input to the AND gate 52, and is applied to the delay line oscillator 41 on the duty determination circuit 4A side through the OR gate 9 to oscillate this.
  • the Q output of RS-FF8 is added to the clear CL of the counter 47 on the 4A side through the OR gate 9 and cleared, so that the number of oscillation cycles starts counting.
  • the output of the counter 47 is input to the other input terminals A1 to An of the matching circuit 50, and the count of the counter 47 increases step by step, and the value (1 At the moment (the point e in FIG. 17) that coincides with the length of the cycle (12 value), the coincidence circuit 50 generates the coincidence output SA 2.
  • the coincidence output S A2 is input to the reset input terminal R of RS-FF8, and resets the flip-flop.
  • the Q output of RS-FF 8 ((17) in FIG. 17) falls and becomes the input of the AND gate 52 in the form of the pulse P1.
  • the coincidence output SA2 is narrow only within the width of the pulse P1.
  • the pulse is generated as AND-A 2 ((20) in FIG. 17), and becomes the clock input of D-FF 54 through the OR gate 53.
  • the output flip-flop D-FF54 is preset each time by SET-Al, SET-A2 or SET-Bl, SET-B2, the short pulse AND corresponding to the above match output SA2 —
  • A2 ((20) in Figure 17) is applied to D—FF 54 as a clock input
  • the Q output of D—FF 54 is inverted (falling operation) each time, and pulse P1 is output to the output terminal OUT. appear.
  • coincidence output SA2 When this coincidence output SA2 occurs, the Q output of RS-FF8 ((17) in Fig. 17) falls and becomes the input of the AND gate 52 in the form of pulse P2. Therefore, this pulse P1, coincidence output SA2 and external trigger section signal TRIG-STOPA
  • the coincidence output SA2 (AND—A2; (20) in FIG. 9) is output from the AND gate 52 as an input only within the width of the pulse P1, and the clock input to the D_F F 54 is input through the OR gate 53. Become.
  • D-FF 54 Since D-FF 54 is preset each time by SET-A2, the short pulse AND-A2 ((20) in Fig. 9) corresponding to the coincidence output SA2 is added to D-FF54 as a clock input. At that point, the Q output of D-FF 54 is inverted and appears as a pulse P 2 'at the output terminal OUT.
  • the above output pulses P1 'and P2' are digital clock signals which rise in synchronization with the external trigger signal ⁇ —TRIG and have the same period ⁇ as the external input clock CK.
  • the input clock signal ⁇ — CK is completely synchronized with the external trigger signal ⁇ XT— TRIG.
  • the waveform has a duty of 50%.
  • the same operation is performed on the 3A side (the 3A side of the first duty determination circuit of the A system) with a delay of two cycles. That is, when entering the third cycle t3, the signal WC—A1 / B1 ((9) in Fig. 17) indicating the actual measurement section (T3) rises (point h in Fig. 17), and the OR gate 7 Through the delay line oscillator 41 of 3 A, the oscillation of the delay line oscillator 41 is started, and is input to the clear terminal CL of the counter 47.At the rising edge, the counter 47 oscillates. Initiate a number of force events.
  • the arithmetic circuit 49 on the A1 side receives the output of the latch circuit 48, calculates the value of 1 to 2 of the count value of the length T of one cycle (timing position with a duty of 50%), and calculates the calculation result. Is output to one of the input terminals Bl to Bn of the matching circuit 50.
  • RS-FF6 is set by the arrival of SET-A1 ((6) in Fig. 17) (point k in Fig. 17).
  • the Q output of RS-FF 6 ((10) in Fig. 17) is input to the AND gate 51, and is applied to the delay line oscillator 41 on the 3A side through the OR gate 7 to oscillate it.
  • the coincidence output S A1 is input to the reset input terminal R of RS-FF6 to reset the flip-flop. Therefore, when this coincidence output S A1 occurs, the Q output of RS-FF6 ((10) in FIG. 17) falls and becomes the input of the AND gate 51 in the form of pulse P3.
  • the coincidence output SA 1 is output as AND—A 1 ((14) in FIG. 17). , And becomes the clock input of D_FF 54 through OR gate 53.
  • the output AND—A 1 is a short pulse generated at the leading edge of the coincidence output S A 1.
  • D-FF54 is preset by SET-A1 every time, so the short pulse AND-A1 ((14) in Fig.17) corresponding to the coincidence output SA1 becomes D-FF54.
  • the Q output of D-FF 54 falls at that point and appears as a pulse P 3 'at the output terminal OUT.
  • SET-A1 ((6) in Fig. 17) arrives again (point r in Fig. 17), and RS-FF6 is set.
  • the Q output of RS-FF 6 ((10) in Fig. 17) becomes the input of AND gate 51, and also passes through OR gate 7 to A1 side delay line oscillator 41, oscillating it. Also, the counter 47 is cleared and the counting of the number of oscillation rounds is started.
  • the match circuit 50 When the count value of the counter 47 matches the output value of the arithmetic circuit 49 (the value of 12 in the length of one cycle) (point s in FIG. 17), the match circuit 50 again generates a match output SA 1. Is done.
  • the coincidence output S A 1 resets RS-FF6
  • the Q output of RS-FF6 falls and becomes the input of the AND gate 51 in the form of pulse P4. Therefore, from the AND gate 51 having the pulse P4 and the coincidence output S A1 and TRIG-STOPA as three inputs, the coincidence output SA1 is output within the width of the pulse P4 and AND-A1 (FIG. 17). (14)), and becomes the clock input of D-FF 54 through the OR gate 53.
  • D-FF54 is preset by SET-A1 every time, so short pulse AND-A1 ((14) in Fig.17) corresponding to the coincidence output SA1 is added to D-FF54 as a clock input. At that point, the Q output of D-FF 54 is inverted and appears as a pulse P4 'at the output terminal OUT.
  • a digital clock synchronized with the external trigger signal EXT-TRIG and having the same period T as the external input clock EXT-CK , P2 ', P3', P4 ', etc. are obtained.
  • the waveform is always modified to a duty of 50%. The effects of the synchronization and the duty correction can be obtained even when the duty of the input clock CK fluctuates around 50% or more. Therefore, it is very effective as an external synchronization circuit with shaping of a digital waveform, and can extend the operable region of a semiconductor active device to a very high frequency.
  • the second external trigger signal G2 arrives at the sixth cycle t6 of the input clock signal CK.
  • the external trigger signal G2 arrives during the measurement of the 50% duty position started by SET-A2.
  • SET-Bl and SET-B2 are generated depending on whether the operating circuit switching signal BLOCK-SEL is H or L.
  • SET-B2 (d2, f2 in Fig. 15) occurs first, as shown in (20) and (21) in Fig. 15.
  • RS-FF8 on the 4B side (the second duty decision circuit 4B of the B system) is set (Fig. 18 d 2 points).
  • RS — Q output of FF 8 ((27) in FIG. 18) is input to AND gate 52 and is applied to delay line oscillator 4 1 on second duty decision circuit 4 B side through OR gate 9. Oscillate this.
  • the Q output of RS-FF 8 is added to the clear CL of the counter 47 on the 4B side through the OR gate 9 to release the clear, so that counting of the number of oscillation cycles is started. Since the measurement of one cycle T is always performed, The calculation result corresponding to the 50% duty has already been input to the matching circuit 50. The moment the count value of the counter 47 increases step by step, and coincides with the value output by the arithmetic circuit 49 (half the length of one cycle ⁇ ) (e in Fig. 18). 2) The match circuit 50 generates a match output SB2.
  • This coincidence output SB2 resets RS-FF8, and its Q output ((27) in FIG. 18) falls and becomes the input of the AND gate 52 in the form of pulse P5.
  • the AND gate 52 which has the pulse P5, the coincidence output SB2, and the external trigger section signal TR10-3 to 0-8 as three inputs, has a coincidence output SB2 with a narrow pulse A.
  • This signal is generated as ND-B 2 ((30) in FIG. 18), and becomes the clock input of D-FF 54 through the OR gate 53.
  • D-FF 54 Since D-FF 54 is preset by SET-B2 each time, the short pulse AND-B2 ((30) in Fig. 18) corresponding to the coincidence output SB2 is added as a clock input to D-FF54. Each time, the Q output of D-FF 54 is inverted (falling operation) and appears as a pulse P 5 'at the output terminal OUT. In the example shown in Fig. 8, in the sixth cycle t6, D-FF 54 has already been preset at the position of dl, so that P5 'is a little wider than the position of G2. It is a wide pulse.
  • RS-FF8 is set.
  • the Q output of RS-FF 8 ((27) in Fig. 18) is input to the AND gate 52, and is also applied to the delay line oscillator 41 on the 4B side through the OR gate 9 to oscillate it. Release 7 to clear and start counting the number of oscillation cycles.
  • D-FF54 is preset by SET-B2 each time, if the short pulse AND-B2 ((26) in Fig. 18) corresponding to the above-mentioned coincidence output SB2 is applied to D-FF54 as a clock input, At that point, the Q output of the D-FF 54 is inverted and appears at the output terminal OUT as a pulse P6 '.
  • the output pulse P 5 ′ rises in synchronization with the previous SET—A2 (dl point in FIG. 17) in the sixth cycle t 6,
  • the signal falls with the coincidence signal SB2 (point e2 in Fig. 17). This falling position coincides with the position of the 50% duty signal when the input clock signal EXT-CK rises at the same time as the arrival of the external trigger signal EXT-TRIG.
  • the above output pulse P 6 ′ rises in synchronization with the external trigger signal EXT—TRIG and is a digital clock signal having the same period ⁇ as the external input clock CK.
  • the clock signal EXT-CK is completely synchronized with the external trigger signal EXT-TRIG.
  • the waveform has a duty of 50%.
  • RS The Q output of FF6 ((22) in Figure 18) is input to the AND gate 51 and is also applied to the delay line oscillator 41 on the 3 B side (duty-one decision circuit 3 B side) through the OR gate 7. Oscillates, and starts the count operation in addition to the CL of the counter 47 on the 3B side. Count value of the counter 47 is gradually increased stepwise, q of the arithmetic circuit 49 outputs to that value (one cycle length Ding 1 / / 2 values) to the moment matching (Fig 8 2), the match circuit 50 generates the match output SB1.
  • This coincidence output SB1 is input to the reset input terminal R of RS-FF6, and resets the flip-flop. Therefore, when this coincidence output SB1 occurs, the Q output of RS-FF6 ((22) in FIG. 18) falls and becomes an input to the AND gate 51 in the form of a pulse P7.
  • the coincidence output SB1 is generated as the output AND-B1 ((25) in FIG. 18).
  • the clock is input to the D-FF 54 through the OR gate 53.
  • the output AND-B1 is a short pulse generated at the leading edge of the coincidence output SB1.
  • DF F 54 is preset by SET-B 1 every time, when the short pulse AND-B 1 ((25) in FIG. 18) corresponding to the coincidence output SB 1 is applied to D FF 54 as a clock input, At that point, the Q output of D-FF 54 falls and appears as a pulse P 7 'at the output terminal OUT.
  • the coincidence pulse SB1 (u3 in Fig. 18) generated in the third cycle t3, the seventh cycle t7, etc. is generated while the Q output of RS-FF6 falls to L. Therefore, no output appears at the AND gate 51, and D-FF 54 is not switched.
  • SET-B1 ((21) in FIG. 18) arrives again (point r2 in FIG. 18), so RS-FF6 is set.
  • the Q output of RS-FF6 ((22) in Fig. 18) becomes the input of the AND gate 51, and is applied to the delay line oscillator 41 on the 3B side through the OR gate 7 and oscillates it. Is cleared, and the counting of the number of oscillation cycles starts.
  • the coincidence circuit 50 outputs the coincidence output SB 1 again from the coincidence circuit 50. Is generated. Since RS-FF6 is reset by the coincidence output SB1, the Q output of RS-FF6 ((22) in FIG. 18) falls and becomes the input of the AND gate 51 in the form of a pulse P8.
  • the AND gate 51 having the pulse P8, the coincidence output SB1 and the TRIG-STOPB as three inputs generates the coincidence output SB1 as the output AND-B1 ((25) in FIG. 18).
  • the clock is input to the D-FF 54 through the OR gate 53.
  • D-FF 54 is preset every time by SET-B1, so the short pulse AND-B1 ((25) in Fig. 18) corresponding to the coincidence output SB1 is added as a clock input to D-FF54. At that point, the Q output of D-FF 54 is inverted and appears as a pulse P 8 'at the output terminal OUT.
  • a digital clock signal P 5 ′, P 6 ′, P synchronizes with the external trigger signal EXT—TRIG from the Q output of D—FF 54 and has the same period T as the external input clock EXT—CK.
  • ⁇ , P 8 '... are obtained.
  • the waveform is always modified to a duty of 50 ° / 0 .
  • the input clock signal At the tenth cycle t10 of K, the third external trigger signal G2 arrives.
  • the external trigger signal G2 arrives during the measurement of the 50% duty position started by SET-B1.
  • SET-Al (d3, f3 in Fig. 15) occurs first, as shown in (15) and (17) in Fig. 15.
  • RS-FF8 is set (d3 point in Fig. 17).
  • the Q output of RS-FF 8 ((17) in Fig. 17) is input to the AND gate 52, and is applied to the delay line oscillator 41 on the duty determination circuit 4A side through the OR gate 9. Oscillate this.
  • shaku 3? ? The output of 0 is added to the clear CL of the counter 47 on the 4 A side through the OR gate 9 and is cleared, and the count of the number of oscillation cycles is started.
  • This coincidence output S A2 resets RS-FF 8, and the set Q output ((17) in FIG. 17) falls, and becomes the input of the AND gate 52 in the form of pulse P9. From the AND gate 52, which has the pulse P5, the coincidence output S A2 and the external trigger section signal TRIG-STOP A as three inputs, the coincidence output SA2 has a narrow pulse AND—A2 (see FIG. 17). (20)), and becomes the clock input of D-FF 54 through OR gate 53.
  • D-FF 54 is preset every time by SET-A2, if the short pulse AND-A2 ((20) in Fig. 17) corresponding to the coincidence output SA2 is applied as a clock input to D-FF54, Each time, the Q output of D-FF 54 is inverted (falling operation) and appears as a pulse P 9 at the output terminal OUT.
  • the SR on the B2 side still has the Q output of the FF 8 '; and the previous SET-B2 at the 10th cycle t10 (d2 in Fig. 18). It remains up, so the 50% duty position is being measured until the SR-FF 8 force S on the B2 side is reset.
  • a coincidence output SB 2 (point w in FIG. 18) appears at one position of 50% duty counted from SET—B 2 (d 2 in FIG. 18). I will fall. That is, the output OUT falls at a position synchronized with the previous trigger G2 without being synchronized with the new trigger G3. Therefore, TRIG-STOP A is added to the AND gate 52. When the operation is performed on the A side, the corresponding AND gate is controlled so that the coincidence signal SB 2 generated on the B side does not affect the output side. Prohibition.
  • the external trigger section signal TR IG—STOP A is applied to the AND gate 51 on the A side
  • the external trigger section signal TR IG—STOPB is applied to the AND gates 51 and 52 on the B side. ing.
  • SA2 point w in FIG. 17
  • RS-FF8 is set.
  • the Q output of RS-FF 8 ((17) in Fig. 17) is input to the AND gate 52, and is also applied to the delay line oscillator 41 on the 4A side through the OR gate 9 to oscillate it. Clear 47 to start counting the number of oscillation cycles.
  • D-FF54 is preset every time by SET-A2, when the short pulse AND-A2 ((20) in Fig. 17) corresponding to the coincidence output SA2 is applied as a clock input to D_FF54 At that point, the Q output of D-FF 54 is inverted and appears as a pulse P 10 'at the output terminal OUT.
  • the output pulse P 9 ′ is synchronized with the previous SET-B 2 (point d 2 in FIG. 17) in the tenth period t 10. It rises, and after the external trigger signal EXT-TRIG (trigger G3) arrives, it falls with the coincidence signal SB2 (point e3 in Fig. 17).
  • This falling position coincides with the position of the 50% duty signal when the input signal EXT-CK rises at the same time as the arrival of the external trigger signal EXT-TRIG. .
  • the output pulse P 10 ′ is a digital clock signal that rises in synchronization with the external trigger signal EXT-TRIG and has the same period T as the external input clock CK.
  • the signal EXT-CK is completely synchronized with the external trigger signal EXT-TRIG.
  • the waveform is 50% duty.
  • the same operation is performed on the 3A side (the 3A side of the first duty-one decision circuit of the A system) with a delay of two cycles.
  • one cycle of measurement is performed by the oscillation, count, calculation, and coincidence operations.
  • RS-FF 6 is set (k3 point in Fig. 17).
  • RS The output Q of FF6 ((10) in Figure 17) is input to the AND gate 51, and is also applied to the delay line oscillator 41 on the 3 A side (duty determination circuit 3 A side) through the OR gate 7 And clear the counter 47 on the 3 A side CL To start the counting operation.
  • a match output SA1 is generated from the match circuit 50.
  • the coincidence output S A1 is input to the reset input terminal R of RS-FF6 to reset the flip-flop. Therefore, when the coincidence output S A1 is generated, the output Q of RS-FF6 ((10) in FIG. 17) falls and becomes an input to the AND gate 51 in the form of a pulse P11.
  • the coincidence output SA1 is generated as the output AND-A1 ((14) in Fig. 17).
  • the clock is input to the D-FF 54 through the OR gate 53.
  • the output AND—A 1 is a short signal generated at the leading edge of the matching output S A 1. Ruth.
  • D-FF 54 is preset by SET-A1 every time, when the short pulse AND-A1 ((14) in Fig. 17) corresponding to the coincidence output SA1 is applied to D-FF54 as a clock input, At that point, the Q output of the D-FF 54 falls and appears as a pulse P 1 at the output terminal OUT.
  • the coincidence pulses SA 1 and SA 2 (ul, u 2 in Fig. 17) generated at t9 in the ninth cycle, til in the first cycle, etc. Since this occurs during the falling, no output appears at the AND gates 51 and 52, and D-FF 54 does not switch. Therefore, the effects of the matching pulses u l and u 2 generated when the A1 side or A2 side is in the measurement section are eliminated by the AND gates 51 and 52 and do not appear on the output OUT side.
  • the digital clock signals P 9 ′, P 10 ′ and P 1 synchronized with the external trigger signal EXT—TRIG and having the same period T as the external input clock EXT—CK from the Q output of D—FF 54 1 ′, P 1 2 ′... are obtained.
  • the waveform has always been corrected to a duty of 50%.
  • a presettable D-FF 54 is used for the width generating circuit 5, but as shown in FIG. 20, an output OR gate 56 is provided instead of the D-FF 54, and the OR gate 56
  • the desired output ((33) in Fig. 18) can be obtained by extracting the Q outputs of SR-FFs 6, 8 preceding the duty-one decision circuits 3A, 4A, 3B, 4B. Obtainable.
  • CKFA and CKFB of the waveform which uses one cycle of the input clock signal EXT-CK shown in Fig. 19 (a) as a unit are used, but two cycles shown in Fig. 19 (b) are used.
  • CKFA and CKFB with the unit waveform can also be used.
  • a timing generation circuit is provided to achieve the purpose of providing a waveform shaping circuit that outputs a waveform with a duty of 50%, regardless of whether the input signal has a duty of 50%.
  • a duty-period determination circuit is provided to determine and indicate the timing position of the 50% duty cycle of the clock signal to be output, and set this to an integer multiple of one cycle T of the input clock signal CK.
  • a practical external synchronization method that can synchronize the input clock signal with an external trigger signal, has a simple configuration, and outputs the input digital signal after shaping it into a waveform with a duty of 50%
  • the internal trigger signal INT—TR IG synchronized with the external trigger signal EXT—TR IG is applied to the input clock signal until the next external trigger signal EXT—TR IG arrives.
  • a large number are created in period T, and are given to the first duty decision circuit 3 and the second duty decision circuit 4 separately before and after time (SET—Al, SET—A2)
  • SET—Al, SET—A2 Alternately, measure the timing position corresponding to 50% of the duty cycle of the input clock signal from the position of the internal trigger signal, and output pulses at the positions of the internal trigger signals SET—A1, SET-1A2. Start-up, with respect to the measured duty of 50% The output pulse falls at the corresponding timing positions SA 1 and SA 2 (see Fig. 7 ).
  • (C) Configuration is simple, yet in order to achieve the object of the practical frequency communication fold circuits are shaped Ru is output to duty 50% waveform timing created by the timing generation circuit 3 0 2
  • a duty determination circuit is provided to determine and instruct the 50% timing position of the duty cycle of the clock signal to be output upon receiving the signal, and this is set to an integer multiple of one cycle T of the input clock signal C.
  • the length of one cycle in the first cycle arriving every time is measured, and the values corresponding to the positions of 25%, 50%, and 75% of the duty are calculated based on the values, and the values within the above interval are calculated.
  • the length is measured in each of the second periods, and when the measured value matches the calculated value, the match signal SA 1, SA 2, SA 3 or SB 1, SB 2, SB 3 is used each time.
  • the operation basically first measures the period of the input clock CK to be subjected to the waveform shaping, Using the measurement result, output the coincidence output at half the period,
  • the present invention proposes an improved technique of such a waveform shaping circuit.
  • the present invention will be described focusing on differences from the above basic embodiment.
  • the cycle measurement of the input clock CK is performed in one cycle of the input clock, but in the present invention, the cycle measurement is performed in m cycles as shown in the circuit configuration diagram of FIG. (M is an integer of 2 or more).
  • M is an integer of 2 or more.
  • the timing generation circuit shown in FIGS. 1, 3 and 5 in order to measure the input clock CK specifically with m periods, the timing generation circuit shown in FIGS. 1, 3 and 5 must be used. It is necessary to change the frequency division ratio of the frequency divider that constitutes 2. According to the present invention, the period of the input clock CK is measured over a long period of time, and the average value is obtained.
  • the measurement accuracy of the cycle of the input clock CK is improved, and as a result, the accuracy of waveform shaping of the output signal obtained from the waveform shaping circuit can be improved. More specifically, it is possible to perform excellent waveform shaping such that the duty ratio can be made closer to 50% with higher accuracy.
  • the period measurement will be specifically described in the following embodiments.
  • FIG. 23 shows the configuration of a digital waveform shaping circuit
  • FIG. 24 shows a time chart showing the operation of the circuit of FIG. 23
  • FIG. 27 shows a timing generating circuit.
  • the input clock CK is divided by 1/4, and as a result, the measurement time of the cycle of the input clock CK is reduced to two cycles of the input clock. Has changed to a minute. Therefore, unlike the example of FIG. 1, the arithmetic circuit of the arithmetic circuit 19 in FIG. 23 needs to be 1 ⁇ 4.
  • the narrow pulse generation circuit 601 for CKF generation, the 1/4 counter 754 for 1 / 4CK generation, and Pulse width widening circuits 612 for CKW generation are connected in parallel.
  • the 1/4 counter 754 is connected to a 1/4 CKW generation pulse width widening circuit 6 11.
  • the length of two cycles of the external input clock CK is measured, and the result is multiplied by 1 to 4 times by the timing generation circuit 2 shown in FIG. To obtain a half cycle of the input clock CK. Then, the matching circuit 28 shown in FIG. 23 outputs the matching output SA when the value obtained from the timing generation circuit 2 is equal to the value obtained from the second counter 27.
  • CKF is a waveform obtained by extracting the edge of CK (narrowing the pulse width).
  • 1Z2CK and 1Z4CK are the divide-by-12 output and the divide-by-14 output of the input clock CK, respectively.
  • 1Z4CKW reduces the pulse width of 1/4 CK DL-OSC1 which received the high level signal of 14 CKW is a pulse that spread out, and oscillates during that period.
  • DL-OSC 1 oscillates, and the first counter 17 receiving the oscillation output counts because its CL input is also at the H level.
  • the falling edge of 1 / 4CK causes the latch 18 to perform a read operation and the count output of the first counter Read.
  • the read count number is multiplied by 14 by the arithmetic circuit 19, and the result is output to the matching circuit 28.
  • the matching circuit 28 the value multiplied by 1Z4 by the arithmetic circuit 19 and the number of counts of the second counter, which gradually increases in response to the signal when the CKW is at the H level DL—OSC 2 oscillates and If a match is found, a match output SA is output.
  • the accuracy of the period measurement is in principle twice as high as that of the basic form of FIG. 1, and as a result, the accuracy of the waveform shaping of the output signal is doubled (the duty is doubled). It can be close to 50% with high accuracy).
  • the cycle measurement of the input clock CK in the present invention is not limited to two cycles, as long as it can be performed at m cycles (m is an integer of 2 or more). That is, to measure the 1 / mCK and l / mCKW output from the timing signal generation circuit 2 shown in FIG. 23, that is, the period of the input clock CK, the DL-OSC 1 is oscillated to count.
  • the interval signal for measuring the number should just be an integral multiple of the period of the input clock CK. For example, in Fig. 25, the measurement time of the period of the input clock CK is changed from the basic form of Fig. 1 to m periods of the input clock, and the input clock CK is divided by 1ZM (M is an integer of 2 or more). are doing.
  • FIG. 28 shows a configuration example of the timing generation circuit 2 in the second embodiment. That is, the timing generation circuit 2 in Fig. 28 that divides the input clock CK by 1 / M is a narrow pulse generation circuit 61 for generating CKF and a 1 / M counter 75 for generating 1 / MCK. 9, and a pulse width widening circuit 6 12 for CKW generation are connected in parallel.
  • the 1 / M counter 759 is connected to a pulse width widening circuit 6 11 for 1 / MC KW generation.
  • the accuracy of the period measurement is in principle up to 2 ZM times higher than the basic form of FIG.
  • the accuracy of period measurement is in principle twice as high as that of the basic form of Fig. 1, and as a result, the accuracy of waveform shaping of the output signal can be increased up to 2 times M It is.
  • FIGS. 29 to 31 show a third embodiment of the present invention in which the waveform shaping circuit shown in FIG. 3 is improved.
  • 29 shows the configuration of the timing generation circuit 2
  • FIG. 30 shows the configuration of the duty determination circuits 3, 4 and the width creation circuit 5, and the like.
  • FIG. 31 shows the configuration of FIG. 4 is a time chart illustrating an operation of the circuit.
  • lines having the same signal name are connected to each other to form a waveform shaping circuit of the present embodiment.
  • the measurement of the input clock CK is performed in one cycle. As can be seen from FIG.
  • the measurement time of the period of the input clock CK remains unchanged from the conventional one, even though the frequency division ratio is larger than 12.
  • the measurement accuracy of the CK period has not increased. For this reason, the improvement of the accuracy to make the output duty closer to 50% has not been measured.
  • FIGS. 32 and 33 show a fourth embodiment of the present invention in which the waveform shaping circuit shown in FIG. 3 is improved.
  • FIG. 32 shows the configuration of the timing generating circuit 2.
  • the creation circuit 5 and the like are connected by lines having the same signal name in the figure to constitute a fourth embodiment of the present invention.
  • FIG. 33 is a timing chart showing the operation of the circuits shown in FIGS. 32 and 30.
  • This fourth embodiment is different from the third embodiment in which the combination of FIG. 29 and FIG. 30 is used, and as a result of dividing the input clock CK by / in the timing generation circuit 2, the cycle of the input clock CK is obtained. Measurement time is twice as long as before. Therefore, the measurement accuracy of the period of the input clock CK is doubled. In this embodiment, it is possible to increase the accuracy of the waveform shaping of the output signal to twice that of the basic mode in FIG. 3 regardless of the frequency division ratio of the input clock CK.
  • the timing generation circuit 2 in FIG. 34 and the duty ratio determination circuits 3 and 4 and the width generation circuit 5 in FIG. 35 are connected by lines having the same signal name in the figure. .
  • the fifth embodiment is a combination of the circuit shown in FIG. 29 and FIG. 30 (third embodiment) and the circuit shown in FIG. 32 and FIG. 30 (fourth embodiment).
  • An embodiment in which the division ratio of a counter 759 for dividing the input clock CK inside the circuit 2 is generalized will be described. As can be seen from FIGS. 29 to 33, if the division ratio of the counter 759 can be increased and the period measurement time can be increased, the measurement accuracy of the input clock period can be improved. As a result, the output duty can be closer to 50%.
  • FIGS. 36 to 38 show a sixth embodiment of the present invention in which the waveform shaping circuit shown in FIG. 5 is improved.
  • the frequency division ratio of the frequency divider constituting the timing generation circuit 2 shown in FIG. 5 is 1/4.
  • FIG. 36 shows the configuration of the timing generation circuit 2
  • FIG. 37 shows the configuration of the duty determination circuits 3, 4, the width creation circuit 5, etc.
  • FIG. 38 shows a time chart showing the operation of the circuit of FIG.
  • FIG. 49 is a time chart showing the operation of the circuit of FIG.
  • the sixth embodiment is different from the basic embodiment of FIG. 5 in that the input clock CK is divided by 1/4 in the timing generation circuit 2 and the measurement time of the period of the input clock CK is doubled compared to the conventional case.
  • the measurement accuracy of the period of the input clock can be doubled compared to the basic form shown in Fig. 5.
  • the duty of the output can be doubled with 50% in principle. Can be approached.
  • the present invention is characterized in that it has m stages (m is an integer of 2 or more). I have. Further, in the basic form shown in FIGS. 3 and 5, the duty determination circuits 3 and 4 have two sets of forces. This may be a three or more circuit configuration. In this way, for example, even if the period of the input clock CK suddenly fluctuates greatly (a fluctuation of more than half of the period), there is an advantage that an output corresponding to the input clock CK can be taken out instantaneously. Occurs. An embodiment of the present invention based on a powerful technical idea will be described below.
  • the configuration of FIG. 1 is changed, and the measurement circuits 20 and 20B have a two-stage configuration.
  • matching circuits 28 and 28B are provided. Things.
  • An OR gate 280 is provided between the matching circuits 28 and 28B and the width creating circuit 5. Even with such a configuration, it is possible to obtain a signal approaching a duty of 50% as an output signal, as in the basic embodiment of FIG. Also, the number of stages of the measurement circuit 20 can be further increased.
  • FIGS. 43 and 44 are timing charts showing the operation of each part in the circuit of this combination.
  • the configuration of FIG. 3 is modified and three-stage duty determining circuits 3, 4, and 4C are provided.
  • the timing generation circuit 2 adjusts the timing signals SET—A, SET-B, SET-C, 1 / 2CKA, 1 / 2CKB, 1 / 2CKC, WC-A, WC-B, WC-C were created and configured to output.
  • the output from the terminal QN of the first and second JK-FFs 781 and 782 is given to the OR gate 714 that outputs the timing signal SET-A via the OR gate 721 and the inverter 702.
  • OR gate 715 that outputs timing signal SET—B receives the output of terminal QN of the second JK—FF 782, and OR gate 715 C that outputs timing signal SET—C.
  • FF 78 1 Terminal QN output is given.
  • the OR gate 718 that outputs the timing signal 1 / 2CKA and the OR gate 718 that outputs WC_A are connected to the output from the terminal QN of the first and second JK-FFs 781 and 782 by the OR gate 721. Is given through.
  • OR gate 717 that outputs timing signal 1 / 2CKB and OR gate 719 that outputs mVC-B
  • the output from terminal Q of the first JK-FF and the timing signal 1 / 2CKC are output
  • the output from the terminal Q of the second JK-FF 782 is given to the OR gates 717C and 719C which output the OR gates 717C and WC-C.
  • FIGS. 45, 42, and 46 A ninth embodiment of the present invention obtained by modifying the waveform shaping circuit of FIG. 3 is shown in FIGS. 45, 42, and 46.
  • the ninth embodiment includes a combination of the timing generation circuit 2 shown in FIG. 45, the duty determination circuits 3 and 4 and the width creation circuit 5 shown in FIG. They are connected.
  • FIG. 46 is a timing chart showing the operation of each part in the circuit of this combination.
  • the ninth embodiment differs from the eighth embodiment in that the configuration in FIG. 3 is changed to provide three-stage duty determination circuits 3, 4, and 4C.
  • the configuration of the timing generation circuit 2 is different.
  • an OR gate 714, 717 which outputs each timing signal
  • the output from the terminal Q of the first JK—FF 781 is given to 719, and the output from the terminal QN of the first and second JK—FF 781, 782 is given to the OR gates 715, 717 C, and 719 C.
  • the OR gate is given via 721.
  • the duty cycle circuit of the ninth embodiment is provided in more stages.
  • FIG. 48 shows a timing generation circuit 2 portion
  • FIG. 49 shows a multi-stage duty circuit and a width generation circuit 5 and the like. The two are connected by lines with the same signal name.
  • the output of the narrow pulse generation circuit 601 is supplied to a first control gate 714A for outputting timing signals SET-A to SET-Y.
  • a second control gate 716 that outputs 1 / MCKA to 1 / MCK Y receives 1 / MCK from the 1 / M counter 759 and a third control gate that outputs WC—A to WC—Y.
  • the output from the pulse width widening circuit 613 is given to 718 A.
  • the output of the 1 / Y counter 758 which receives the output from the input clock CK and the 1 / M counter 759, is input to the timing gate creation circuit 725, and the timing obtained by the timing gate creation circuit 725 is obtained.
  • the signal is output to each control gate 714A, 716A, 718A.
  • the timing signals output from the respective control gates of the timing generation circuit 2 in FIG. 48 are input to the duty circuits 4 to 4Y in the respective stages in FIG. Is done. Then, the outputs of the duty circuits 4 to 4Y of the respective stages are guided to the OR gate 5B constituting the width generating circuit 5, and a desired output signal is obtained.
  • FIGS. 45 and 47 show a tenth embodiment of the present invention obtained by modifying the waveform shaping circuit of FIG.
  • the first embodiment is configured by combining the timing generation circuit 2 shown in FIG. 45 with the duty determination circuits 3 and 4 and the width generation circuit 5 shown in FIG. Name lines are connected to each other.
  • the circuit of FIG. 47 may be combined with the circuit of FIG.
  • the eleventh embodiment similarly to the ninth embodiment, three stages of duty decision circuits 3, 4, and 4C are provided. Is provided. Also, the first and second OR gates 5d, 3 3 provided in the preceding stage of the PD-FF 5C are configured to receive the outputs from the three-stage duty circuits 3, 4, and 4C. I have. Even with such a configuration, it is possible to obtain a signal having a duty ratio approaching 50% as an output signal, as in the basic mode of FIG.
  • the number of stages of the duty circuit of the 11th embodiment is further increased.
  • the same circuit of FIG. 48 as that used in the 10th embodiment is used for the timing generation circuit 2.
  • the multi-stage duty circuit is different from the tenth embodiment in that the output portion to the width generation circuit 5 is a resettable PD-FF5C, which is different from the tenth embodiment.
  • its operation is the same as that of the basic embodiment shown in FIG. As described above, even when the duty generating circuits are provided in multiple stages by using PD-FFs in the width creating circuit 5, the duty ratio can be made closer to 50% as the output signal, similarly to the basic form of FIG. .
  • FIGS. 51 and 52 show the power-on reset signal generation circuit 810 capable of outputting the L-level signal POWER RESET signal for a fixed time tr after the power is input, and the operation thereof. It is shown.
  • the present invention includes, for example, a combination of the power-on reset signal generation circuit 810 as a component of the timing generation circuit 2.
  • an embodiment of the present invention incorporating the power-on reset signal generation circuit 810 will be specifically described.
  • the thirteenth embodiment is a combination of a timing generation circuit 2 in FIG. 53 and a circuit such as a single duty circuit and width generation circuit 5 in FIG. 54, and these two circuits have the same signal name. Connected.
  • a power-on reset signal generation circuit 810 as shown in FIG. 53 is incorporated in the timing generation circuit 2 with respect to the basic form shown in FIG.
  • OR gates 81 1 and 812 are provided at the R terminals of RS-FF-A and RS-FF-B provided before the duty circuits 3 and 4, and power is supplied to these OR gates. The reset signal is input.
  • the L-level signal POWER ON RESET signal is output for a certain time tr, and the counter 17 of the duty determination circuit 3 is forcibly cleared for a certain time tr (that is, the count value).
  • tr that is, the count value
  • the number of stages of the duty determination circuit 3 may be two or more. In this case, an OR circuit is provided before the reset input R of the same RS-FF, and the same connection as in FIG. 54 is performed. Good.
  • the state is such that the cycle of the input clock CK is measured. Shortly before, by periodically resetting the output value of the counter 17 that performs the period measurement operation to the all-zero state, as shown in the time chart of FIG. Can be operated without any problem.
  • the latch circuit 18 constituting the duty cycle determining circuit 3 or 4 immediately after power-on, a very large count value compared to the cycle of the input clock CK to be used, even if the input clock CK has already been latched.
  • a coincidence output can be obtained at half the cycle, and the ideal initial state can be set immediately after power-on.
  • a coincidence output can be obtained at the half period of the input clock CK, as described above, and a clock with a desired 50% duty is always obtained. CK is obtained.
  • a power-on reset signal generation circuit 810 is incorporated in the timing generation circuit 2 in the basic form shown in FIG. That is, the timing generation circuit 2 of FIG. 53 is provided with the power-on reset signal generation circuit 810 as in the case of the thirteenth embodiment.
  • OR gates 811 and 812 are provided at the R terminals of RS-FF-A and RS-FF-B provided before the duty circuits 3 and 4 in Fig. 55. ON reset signal is input.
  • the width creating circuit 5 is a presettable PD-FF5C, similarly to the basic embodiment of FIG.
  • the L-level signal POWER ON RESET signal is output for a certain time tr, and the counter 17 of the duty determination circuit 3 is turned on for a certain time.
  • the data is forcibly set to clear (that is, all count values are at L level), and during this time, the data in latch 18 is always held at L level.
  • the operation is performed in the state according to the basic form in FIG.
  • the number of stages of the single duty determination circuit 3 may be two or more. In this case, an OR circuit is provided before the reset input R of the same RS-FF, and FIG. You can make the same connection.
  • FIGS. 56, 57, 59 Fifteenth embodiment: FIGS. 56, 57, 59
  • the operation is considered assuming that the cycle of the input clock CK does not change in the middle, but if the cycle of the input clock CK greatly fluctuates in a short time, the same In other words, it is assumed that a coincidence output cannot be obtained at a desired cycle corresponding to the multiplication content with respect to the cycle of the input clock CK, and a desired multiplication output cannot be obtained forever.
  • the configuration of the timing generation circuit 2 is slightly changed so that the operation of the input clock CK can be performed without any problem even when the input clock CK fluctuates. Shortly before the state of performing the period measurement, the output value of the counter 17 that performs the period measurement operation is periodically reset to a zero state.
  • the fifteenth embodiment is a combination of the timing generation circuit 2 shown in FIG. 56 and the circuits such as the one-duty circuits 3 and 4 and the width creation circuit 5 shown in FIG. 57, and both circuits have the same signal name. Are connected to each other.
  • a 1/3 counter 753 having first and second flip-flops 771 and 772 is provided at the subsequent stage through a JK FF 781 for the first and second reset signals.
  • Flip-flops (FD-FF-A, FD-FF-B) 818 and 819 are provided.
  • the reset signal RESET-A And RESET— B are obtained.
  • these reset signals RESET-A and RESET-B are connected to the R-terminals of the RS-FF-A and RS-FF-B provided before the duty circuits 3 and 4, respectively.
  • OR gates 81 1 and 812 provided are input.
  • the width creation circuit 5 is composed of an OR gate 5b, as in the basic embodiment of FIG.
  • the duty determination circuit is compared with the basic configuration of FIG. 3 after one of the duty determination circuits finishes the duty determination operation.
  • a low-level signal RESET signal is output every time or intermittently before the measurement of the cycle of the cycle is performed, and the power counter 17 of the duty determination circuit 3 is forcibly cleared for a certain time (that is, all the count values are cleared). L level)
  • the data force of the latch 18 is always held at the L level, and from the time the duty cycle determining circuit measures the period of the clock CK, the period measurement operation continues as usual. It is something to do.
  • FIG. 59 is a timing chart showing the operation of each part when FIG. 56 and FIG. 57 are operated in combination. Note that the number of stages of the duty determination circuit 3 may be two or more. In such a case, an OR circuit is provided before the reset input R of the same RS-FF, and a connection similar to that of FIG. Just do it.
  • FIG. 60 Sixteenth embodiment: FIG. 60, FIG. 57
  • FIG. 60 shows a generalized configuration when the frequency division operation of the input clock CK is changed in the timing generation circuit 2.
  • the circuits shown in FIGS. 60 and 57 are operated in combination.
  • the CKA in this case, 1- 3 CKA and 1-MCKA
  • CKB in this case, 1- 3 CKA and 1-MCKA
  • CKB in this case, 1- 3 CKA and 1-MCKA
  • CKB in this case, 1- 3 CKA and 1-MCKA
  • WC-A and WC-B are connected even if there is a slight difference between the front and rear displays.
  • the arithmetic circuit 1 in FIG. It is necessary to change the setting of the calculation value of 9.
  • the seventeenth embodiment is obtained by applying the fifteenth embodiment to the basic embodiment shown in FIG. 5, and includes a timing generation circuit 2 shown in FIG. 56, duty circuits 3 and 4 and a width generation circuit 5 shown in FIG. And the like. Both circuits are connected by the same signal name.
  • the first and second reset signal flip-flops are provided via the JK-FF 781 at the subsequent stage of the 1Z3 counter 753 having the first and second flip-flops 771 and 772. (FD-FF-A, FD-FF-B) 818 and 819 are provided.
  • the output signal of the terminal Q of the FD-FF-A818 and FD-FF-B 819 is guided to the AND gates 815 and 816 together with the output of the delay circuit and the output of the JK-FF 781 to generate the reset signal RESET.
  • a and RESET— B have been obtained.
  • the reset signals RESET-A and RESET-B OR gates 81 1 and 812 provided before the R terminal of RS-FF-A and RS-FF-B provided in the previous stage of circuits 3 and 4 are input.
  • the width creation circuit 5 is a PD-FF 5C that can be preset similarly to the basic form of FIG.
  • the seventeenth embodiment differs from the basic embodiment of FIG. 3 in that after one of the duty determining circuits has finished the duty determining operation,
  • the L-level signal RESET signal is output every time or intermittently before one decision circuit measures the clock CK cycle, and the power counter 17 of the duty decision circuit 3 is forcibly forced for a certain period of time.
  • Set to clear 1 that is, set all counts to L level
  • the data in latch 18 is always held at L level
  • the period measurement operation is performed in the conventional state.
  • FIG. 59 is a timing chart showing the operation of each part when FIG. 56 and FIG. 58 are operated in combination.
  • the number of stages of the duty determination circuit 3 may be two or more. In such a case, an OR circuit is provided before the reset input R of the same RS-FF, and the connection shown in FIG. 58 is made. Good.
  • FIG. 60 shows a generalized configuration of the timing generation circuit 2 when the frequency division operation of the input clock CK is changed.
  • the circuits shown in FIGS. 60 and 58 are operated in combination.
  • CKA in this case, 1/3 CKA and 1 MCKA
  • CKB in this case, 1/3 CKA and 1 MCKA
  • CKB in this case, 1/3 CKA and 1 MCKA
  • CKB in this case, 1/3 CKA and 1 MCKA
  • WC-A and UWC-B are connected even if there is a slight difference in the display before and after.
  • the arithmetic circuit 1 in FIG. It is necessary to change the setting of the calculation value of 9.
  • FIG. 1 is a timing chart showing the above problem.
  • the latch 18 performs the latch operation at the falling position of 1 Z 2 CK in FIG. 61, the latched data at that time is the delay time of each flip-flop of the counter 17.
  • the embodiment shown in FIG. 1 only reduces the frequency of inaccurate measurement of the delay time and reduces the occurrence of the inaccurate measurement to zero. Can not be.
  • the circuit configuration becomes more complicated and the power consumption tends to increase more than when the counter is not of the synchronous type.
  • the output of the delay line oscillator 11 is operated in two types of phase stages of positive and negative (operates in two types of phase stages of rising and falling). It uses a method of counting at the same time using two counters and latching the count result at the same time with two latches. It is also conceivable that the value obtained by the latch is calculated by two arithmetic circuits, and two matching circuits are similarly prepared.
  • the count output of the counter 27 receiving the output of the delay line oscillator 21 changes from a state where the count value is not an original count value due to a delay time inherent in the count operation to a pulse that is very narrow with the increase in the count number. May occur.
  • the state power of the increase of the count output merely reduces the frequency of the state where the count value is not the original count value. Can not.
  • the circuit configuration becomes more complicated and the power consumption is liable to increase as compared with the case of the non-synchronous counter.
  • the output of the delay line oscillator (DL-OSC) 21 is operated in two types of positive and negative phase stages (two types of rising and falling). Uses two counters and operates at the same time.
  • the arithmetic circuit 19 and another new arithmetic circuit are prepared, the counter 27 of the measurement circuit 20 and a new counter are prepared, and the output of the arithmetic circuit 19 is supplied to one input.
  • the other input is the output of the counter 27 of the measurement circuit 20 and the match circuit 28, the output of the new arithmetic circuit is one input, and the other input is the output of the new counter of the measurement circuit 20. It is assumed that a new match circuit is prepared, and when both the match circuit 28 and the new match circuit output a match output, a match output of a half cycle of the clock CK is obtained.
  • the nineteenth embodiment of the present invention shown in FIG. 62 shows an embodiment corresponding to FIG. 1 in which the above measures have been applied to the period measuring circuit 10 and the actual measuring circuit 20.
  • the inverter 705 uses the delay line oscillator (DL-OSC) 1
  • An output in which the output of (1) is inverted is also prepared, and both the inverted and non-inverted output operations are performed simultaneously.
  • the output side of the delay line oscillator 11 in the waveform shaping circuit of Fig. 1 operates in two types of phase stages, positive and negative (two types of phase stages, rising and falling).
  • Two counters 17 and 17 B and latches 18 and 18 B are provided.
  • two arithmetic circuits 19 and 19B and two matching circuits 28 and 28B are prepared.
  • the countermeasure to operate the counter at the two kinds of positive and negative phase stages is to use the inverter 706 to invert the DL-OSC 21 output. Outputs are also prepared, and a series of operations are performed simultaneously on both inverted and non-inverted ones.
  • the true match output is obtained only when the match outputs SA 1 of the match circuit 28 in FIG. 62 and the match output SA 2 of the new match circuit 28 B are simultaneously obtained. It is obtained as a coincidence output SA from the ND gate 7 24.
  • the timing chart shown in FIG. 642 is a generalization of the above relationship.
  • the signal represented by “′” such as the counter Q 1 ′ in FIG. 64 may be considered to be the signal counted by the inverter.
  • the output of the delay line oscillator (DL-OSC) 11 is counted at the same time using two counters 17 and 17B, and the count result is also 2 Latched by two latches 18 and 18 B at the same time. Then, the values obtained by the latch are operated by the operation circuits 19 and 19B, and the coincidence outputs are obtained from the coincidence circuits 28 and 28B.
  • the counter 17 and the latch 18 for performing the period measurement of the period measurement circuit 10 have a circuit-specific delay time, the period measurement can be performed accurately, and as a result, half of the clock CK A coincidence output can be obtained at the time of the cycle, and a clock CK having a desired duty of 50% can be obtained.
  • the circuit configuration becomes simpler and power consumption is reduced as compared with a case where the delay time of the circuit is dealt with using a synchronous power counter.
  • the output of the delay line oscillator (DL-OSC) 21 operates in two phase stages, positive and negative in the same manner as above (operates in two types of phase stages, rising and falling) )
  • Two counters 27 and 27 B are provided and count at the same time.
  • a matching circuit 28 having the output of the first arithmetic circuit 19 as one input and the other input being the output of the counter 27 of the measurement circuit 20; and the output of the second arithmetic circuit 19B. Is one input, and the other input is the output of the second counter 27 B of the measurement circuit 20.
  • both matching circuits 28 and 28 B output the matching outputs. In this case, it is assumed that a coincidence output of a half cycle of the clock CK is obtained.
  • FIGS. 3 and 5 The basic form shown in FIGS. 3 and 5 has the same problem as described in the above (d). That is, the counter 17 and the latch 18 for measuring the period of the clock CK do not accurately measure the period due to the delay time inherent to the circuit, and as a result, the coincidence output is obtained at the half period of the clock CK. Therefore, there is a problem that a clock CK having a desired duty of 50% cannot be obtained.
  • FIG. 63 and FIG. 64 show the above relations by generalizing the measurement conditions of the cycle of the input clock CK. Note that in FIG. 64, the counters Q1, hereinafter Q2, Q3, etc. represent the respective counter outputs of the counter 17 of FIG. 63, ie, FIGS. In this case, as in the case of FIG. 61, it can be seen that a match output is generated not only at the true match position PTA but also at a position PA that is significantly different.
  • the delay time of the counter 17 it is possible to reduce the delay time by using a synchronous counter than by using a non-synchronous counter, but the delay time itself cannot be reduced to zero. . Also, even if the delay time can be made very small, the basic form shown in Figs. 3 and 5 will only reduce the frequency with which the delay time measurement is not accurately performed, resulting in an inaccurate measurement. Can not be reduced to zero. In addition, when the counter 17 is configured by a synchronous counter, the circuit configuration becomes more complicated and the power consumption is more likely to be increased than when the counter is not of the synchronous type. Therefore, in order to solve the above problem, the present invention relates to the basic form shown in FIGS.
  • a counter 17 and a new counter are provided in the duty determination circuits 3 and 4, and the output of the counter 17 is latched by the latch 18 and the output of the new counter is a new latch. Latch.
  • the output of the latch 18 is sent to the arithmetic circuit 19, while the output of the new latch is sent to the new arithmetic circuit.
  • the output of the counter 17 is applied to one input of the matching circuit 28, and the output of the arithmetic circuit 19 is applied to the other input of the matching circuit 28.
  • the output of the new counter is applied to one input of the new matching circuit, and the other input of the new matching circuit is applied to the output of the new arithmetic circuit.
  • FIG. 65 shows an embodiment corresponding to FIGS. 3 and 5 in which the above measures have been taken.
  • an inverter 705 that inverts the output of the delay line oscillator (DL-OSC) 11 and outputs it is also available. The operation is simultaneously performed on both the counter and the counter that are not inverted.
  • DL-OSC delay line oscillator
  • the true match output is ANDed only when the match output of both the match output SA1 of the match circuit 28 in Fig. 65 and the match output SA2 of the new match circuit 28B is obtained at the same time. It is obtained from the gate 724 as the coincidence output SA.
  • Figure 64 shows This is a generalization of the above relationship. In the embodiment of FIG. 65, it is sufficient to consider that the signal represented by “′” such as the counter Q 1 ′ in FIG. 64 counts the signal inverted by the inverter.
  • FIG. 66 shows a new embodiment corresponding to a case where the setting of the cycle of the input clock CK is generalized by a new setting of the timing generation circuit 2.
  • the circuit configuration of each counter is simplified and the power consumption of each counter is reduced.
  • a coincidence output with a more accurate half cycle of the clock CK can be obtained, a clock CK having a more accurate duty of 50% can be obtained.
  • the outputs of the delay line oscillators 11 and 21 are connected to the inverter 705 using two types of phase stages (0 ° and 180 ° phase stages).
  • a phase stage consisting of a large number of delay circuits is prepared instead of an inverter, and a counter is prepared for each phase stage.
  • the same number of latches, arithmetic circuits, and matching circuits may be prepared. .
  • RS-FFs RS flip-flops
  • RS flip-flops are provided for the number of combinations of the prepared counters and the like (for example, 2 when the number of counters is two), and a plurality of matched outputs are prepared. Is applied to the input of each prepared RS flip-flop, and the time when all the RS flip-flops change due to the coincidence output is the time when the true coincidence output is obtained. According to the present invention, a true coincidence output having a stable pulse width can be obtained. (f-1) 21st embodiment... Figure 6 7
  • FIG. 67 shows an embodiment corresponding to FIGS. 3 and 5 in which the above measures have been taken.
  • the RS flip-flop 6 since the signal of SET-A always arrives, the RS flip-flop 6 is set, and the Q output thereof becomes the H level. Therefore, its output passes through the inverter 707 and is inverted, and as a result, the reset inputs of the two RS flip-flops 851 and 852 are both at the L level. That is, the two RS flip-flops 851 and 852 are both in a state of waiting for the coincidence output S A1 or S A2. And, for example, as shown in Fig.
  • the configuration of the delay line transmission circuit illustrated in the cycle measurement circuit 10 and the measurement circuit 20 in FIG. 1 and the duty determination circuits 3 and 4 in FIGS. 3 and 5 has the minimum configuration, that is, The device is composed of one NAND and two inverters.
  • the circuit configuration using only the delay line oscillator is simple, but the oscillation frequency becomes extremely high, so that there is a problem that the power consumption is inevitably increased.
  • the counter for counting the delay line oscillator must be a very high-speed counter, and the peripheral circuits of the delay line oscillator also consume much power.
  • the configuration of the above-mentioned delay line oscillator uses a circuit with a longer oscillation period, in which two or more combinations of one NAND and one inverter are prepared first.
  • the transmission cycle of the delay line oscillator becomes longer, the measurement accuracy of the cycle of the input clock CK is reduced to less than half, and the detection at 50% of the cycle of the input clock CK is performed. It is conceivable that the accuracy is reduced to less than half that of the conventional model.
  • Figure 69 illustrates the above measures.
  • one NAND and one inverter are regarded as one combination, and by utilizing the fact that the phase is slightly different for each combination, the delay line oscillator is connected to a large number of phases.
  • the delay line oscillator is connected to a large number of phases.
  • a counter is used to roughly measure several times the period of the delay line transmitter, and based on the results of the new latch outputs installed for each phase stage of the delay line transmitter, the delay line transmitter The fine phase result in one cycle of was also obtained.
  • the configuration of the delay line oscillator is composed of one NAND and two sets of the inverter 1, that is, two delay stages of the delay line oscillator are prepared.
  • each phase stage of the delay line oscillator is connected.
  • a phase result of at least one half cycle of the delay line oscillator can be obtained.
  • a phase result of 1/4 of one cycle of the delay line oscillator can be obtained.
  • FIG. 70 shows an embodiment of the present invention in which the above measures are taken.
  • the phase coincidence detection circuit 861 when a DL—OSC composed of a large number of NANDs and inverters is configured, taps (eg, OSC—dl, OSC— d2, OSC-dn), observe the output of each of them at the same time, and obtain a coincident output based on the results, to further improve the phase accuracy, that is, the duty ratio with 50% accuracy.
  • the operating speed of the counters 17 and 17B of the duty determination circuit can be reduced, so that the power consumption of these counters can be reduced.
  • FIG. 71 shows a specific embodiment in a case where the configuration of DL-OSC is two sets of NAND and inverter. With this configuration, the oscillation frequency can be reduced by half as compared with the DL-OSC having the configuration of FIG. 70 (a), so that when using a C-MOS IC, power consumption is reduced by half. it can.
  • the delay line transmitter Based on the result of the output of each latch connected to each phase stage of the device, a phase result of at least about 1/4 of one cycle of the delay line oscillator can be obtained. If the rising and falling states of each phase stage are also determined, it is possible to obtain a 1/8 phase result of one cycle of the delay line oscillator.
  • the contents from (a) period measurement to (g) period measurement circuit 10, actual measurement circuit 20, and delay line transmitters used in duty-one determination circuits 3 and 4 are described above. May be performed individually and independently, or may be performed simultaneously by combining all contents. For example, although (a) individually describes the number of stages of the period measurement and (b) individually describes the number of stages of the actual measurement circuit and the duty determination circuit, the number of stages may be increased by combining them. (i) Duty setting other than 50%
  • the operation of the waveform shaping circuit in each of the embodiments described so far has been based on the premise that the output duty is as close to 50% as possible.
  • the duty of a computer CPU is May require one different two-phase clock.
  • the two phases (two types) of clocks are in a phase relationship such that they are not simultaneously at the same level (H level or L level).
  • One of these two signals has a duty of 50. If it is set to / 0 , the other will be greatly deviated from the duty of 50%, so the clock frequency will apparently increase, which is not preferable. For this reason, we sometimes make the duty slightly different from 50%.
  • FIG. 72 illustrates the operation of the duty fine adjustment circuit 870 of the present invention, which can explain the above and take measures against it.
  • CK1 is a signal having a duty of 50%
  • CK2 is a signal having a relationship that cannot be at the same time as the H level.
  • CK10 and CK20 exemplify signals in which both of these two signals do not deviate from the 50% duty at the same time.
  • the values of 10 and 10 are set because of the inherent delay time trd of the transistor of the component. ! : 20 Both sides must be out of phase by more than this inherent delay time trd. Therefore, for example, in the duty fine adjustment circuit 870 in FIG.
  • the delay circuits 765 and 766 are each a delay circuit having a delay time inherent to the device, and the duty is 50 as CKF.
  • the signal at the head position of / 0 and the signal indicating that the duty has reached 50% as SA and using two RS flip-flops 871 and 872 with the same characteristics, QN and Q
  • the desired output is obtained in a phase relationship such that they are not at the same level (H level or L level) at the same time, and both are as close as possible to a duty of 50%.
  • FIG. 72 which is a timing chart showing the operation of FIG. 73, and as can be seen from the above description, CKF is the same as that of FIG. If the signal shown as F is used and the coincidence output is used as it is as the SA, the phase relation is such that both of the desired signals will not be at the same level (H level or L level) at the same time, and both are duplication. Note c output as close as possible to one tee one 50% is obtained, for reality to have some margin margin, it is desirable to use the inherent delay element three times from 2 inherent delay time, As an inherent delay element, a plurality of inverters may be used.
  • the CKF uses the output of OR-1 in the embodiment of FIG. 5 or a similar embodiment. be able to. Further, in general, one edge of the input clock CK (or EXTCK) is extracted. For example, in the timing generation circuit 2 of FIG. 3, a signal of a portion indicated as SET-AB may be used. This is the same in FIG. 3 or FIG. 5 and similar embodiments. On the other hand, S A (true match output) is used as it is in FIGS. 3 and 5 and similar embodiments.
  • FIG. 75 is a further simplification of the embodiment of FIG.
  • FIG. 76 shows a specific example of the timing generation circuit 2 of FIG. 75
  • FIG. 77 is a timing chart showing the operation of each unit of FIG.
  • FIG. 78 shows that the RS flip-flop 5a of the embodiment of FIG. 75 can be preset.
  • An example in which the D flip-flop is changed to 5c is shown.
  • the same effect as in the embodiment of FIG. 75 can be obtained.
  • the circuit configuration is simplified as compared with the embodiment shown in the figure, and the delay element for generating the CKW signal is completely unnecessary. Since there is no need to set the time, the operation of the circuit is stable, and furthermore, it is completely unaffected by fluctuations in the frequency of the input clock CK. That is, stable operation is possible regardless of the frequency in any frequency band in which circuit operation is basically possible.
  • FIG. 79 is an improvement (of two phases of positive and negative) in order to deal with the problems of the period measurement circuit 10 and the actual measurement circuit 20 described so far in the embodiments of FIG. 75 and FIG. This is an embodiment in which measures are taken.
  • connection method is the same as in the past, taking the period measurement circuit 10, actual measurement circuit 20, arithmetic circuit 19, and coincidence circuit 28 in the embodiment of FIG. 75 or FIG. Instead, connect the circuit of Figure 79 with the same signal name.
  • the SA output in Figure 79 is connected to the R input, which is the reset input of the RS flip-flop 5a in Figure 75, and to the clock input CK of the presettable D flip-flop 5c in Figure 78.
  • the input of DL-OSC2 in FIG. 79 is connected to the Q output of each flip-flop, which is the output terminal in FIGS. With this configuration, the accuracy of the duty of the output clock is improved as in the related art.
  • the phase of the output clock is arbitrarily and accurately formed by changing the-part of the waveform shaping circuit described so far, and furthermore, is constituted by an analog circuit.
  • 9 shows an embodiment of a delay circuit capable of setting a delay time stably over a wide frequency band without any problem.
  • the configuration of these circuits differs from the basic mode only in that a plurality of arithmetic circuits and a plurality of matching circuits are basically provided. The operation is different from the basic mode. Rather than obtaining a coincidence output only once for one lock cycle, use the coincidence output twice and use these two coincidence outputs to set the output delay time or phase. It is in.
  • FIG. 83 is a timing chart showing the operation of the main part of the embodiment shown in FIGS. 80, 81 and 82.
  • a desired delay output is obtained by obtaining two coincidence outputs S A1 and S A2 and supplying them to a flip-flop.
  • the operation value of the operation circuit 19 is set according to the measurement time of the cycle of the input clock CK, and the duty of the output is reduced.
  • the operation value of the operation circuit 192 is set in the same manner so as to be 50%.
  • the operation basically firstly determines the period of the input clock CK at which the frequency doubling is to be performed. Measure and use the measurement results to determine the phase position according to the multiple Outputs the coincidence output, and uses the coincidence output to invert the output of the width creation circuit to create the necessary multiply output.
  • an RS flip-flop is used as the width generation circuit 5, but in the embodiment of FIG. 7, a presettable D flip-flop that inverts each time a coincidence output is obtained is provided.
  • the output of the latch 18 is applied to one of the inputs of at least three or more sets of arithmetic circuits, and the output of the counter 27 of the measurement circuit 20 of FIG.
  • the other input of those matching circuits is connected to the output of the three or more sets of arithmetic circuits.
  • the width generation circuit composed of D flip-flops is inverted every time a coincidence output is obtained, so that it can be applied to a multiplier.
  • FIG. 84 shows an example in which the basic form of FIG. 1 is applied to a doubler circuit based on the above idea.
  • the configuration shown in FIG. 85 may be used. In this case, it is necessary to prepare an odd number of combinations of arithmetic circuits and matching circuits (for example, arithmetic circuits 219 and matching circuits 222).
  • arithmetic circuits 219 and matching circuits 222 for example, arithmetic circuits 219 and matching circuits 222.
  • the same signal names may be exchanged and connected.
  • the period measurement of the input clock CK is performed based on the input clock CK.
  • the lock was performed in one cycle, but this is not limited to one cycle and may be m cycles (m is an integer of 2 or more).
  • this is the new embodiment according to FIG. 1 and the embodiment of FIG. 7 incorporating the contents supplemented by the simpler circuit configuration of (a) above, and specifically for the measurement with m periods. It is necessary to change the frequency division ratio of the frequency divider constituting the timing generation circuit 2 shown in FIGS. 1 and 7.
  • the technical improvement by measuring the period of the input clock CK at m periods (m is an integer of 2 or more) is that the measurement accuracy of the period of the input clock CK is improved.
  • the signal accuracy of the output signal obtained from the circuit can be improved (the pulse interval between output pulses is maintained properly, and the pulse duty is more accurate, approaching 50%).
  • FIG. 86 shows an example in which the embodiment of FIG. 1 is applied to a doubler circuit based on the above idea.
  • the configuration shown in FIG. 87 may be used.
  • it is necessary to prepare an odd number of combinations of the arithmetic circuit and the matching circuit for example, the arithmetic circuit 219 and the matching circuit 222).
  • the same signal names may be exchanged and connected.
  • the circuit configuration of the part that functions to output the coincidence output at the phase position corresponding to the multiplication ratio is the minimum configuration.
  • it shows a circuit configuration that is equal to or more in performance than the one that operates with a circuit configuration larger than that of the illustrated circuit configuration, and that is the least expensive.
  • the circuit configuration becomes larger and the cost increases, but the performance (accuracy of the output signal after multiplication) does not increase.
  • the duty-one determination circuits 3 and 4 have two sets, but this may be three or more sets. In this case as well, as in the embodiment of FIG. 1, the circuit configuration becomes larger and the cost increases, but the performance (accuracy of waveform shaping after doubling) does not increase.
  • FIG. 88 shows an embodiment configured based on the above idea. Also in this configuration, proper multiplied output is possible.
  • a power-on reset signal generation circuit 810 that can output the power-on reset signal is prepared.
  • this power-on reset signal generation circuit 810 is combined as a component of the timing generation circuit 2. May be.
  • the output of this power-on reset is, like the one shown in FIG. 55, the RS-FF 6 of the duty determination circuit 3 and the RS-FF 8 of the duty-one determination circuit 4 in FIG.
  • An OR circuit may be newly inserted to make the same connection as in FIG.
  • the operation is considered assuming that the cycle of the input clock CK does not change in the middle, but if the cycle of the input clock CK fluctuates greatly in a short time, the same situation as above, that is, However, it was assumed that a coincidence output could not be obtained at a desired period according to the content of the input clock CK according to the content of the input clock CK, and a desired output of the output could not be obtained even at the result level. Therefore, in the present invention, the configuration of the timing generation circuit 2 is slightly changed so that the operation of the input clock CK can be performed without any problem even when the input clock CK fluctuates. Before that, the output value of the counter 17 that performs the period measurement operation is periodically reset to all zeros.
  • the L level signal RESET signal is output every time or intermittently, and the counter 17 of the duty decision circuit 3 is forcibly set for a certain period of time. Cleared (that is, all count values are set to L level), during which time the data of latch 18 is always held at L level, and the duty decision circuit sets the clock cycle of clock CK. From the time of measurement, the period measurement operation may be performed in the conventional state.
  • the reset input R of the RS-FF 6 of the duty determination circuit 3 and the two reset inputs of the RS-FF 8 of the other duty determination circuit 4 It is sufficient to insert an OR circuit into the circuit and make the same connection as in Fig. 58.
  • the RESET signal applied to this OR input may be supplied based on the embodiment of FIG.
  • FIG. 84 shows an example in which the embodiment of FIG. 1 is applied to a 2 delay multiplication circuit.
  • a counter 17 and a latch 18 for performing period measurement of the period measurement circuit 10 are circuit-specific. Period measurement is not performed accurately due to the existing delay time.As a result, a match output cannot be obtained at the desired period according to the content of the input clock CK, and the result is always desired. However, there is a problem in that the multi-level output cannot be obtained.
  • the delay time of the counter 17 it is possible to reduce the delay time by using a synchronous counter than by using a non-synchronous counter, but to make the delay time itself zero It is not possible. Also, even if the delay time can be made very small, the new embodiment which improves on FIG. 1 as shown in FIG. 84 only reduces the frequency with which the delay time is not accurately measured. However, the occurrence of the inaccurate measurement cannot be reduced to zero. In addition, when the counter 17 is configured by a synchronous counter, the circuit configuration becomes more complicated and the power consumption is more likely to be increased as compared with a non-synchronous counter.
  • two counters that operate the output of the delay line oscillator 11 in two types of phase stages (operating in two types of rising and falling phases) are used. Counting at the same time and using the two latches to latch the result at the same time. It is also conceivable that the value obtained by the latch is also calculated by two arithmetic circuits, and two matching circuits are similarly prepared.
  • FIG. 89 shows an embodiment of the present invention in which the above countermeasures are taken in FIG. 84, which is an embodiment in which the embodiment of FIG. 1 is applied to a doubler circuit.
  • the coincidence output of the match circuit 222 in Fig. 89 and the coincidence output of SA2 and the coincidence output of SA22 and the coincidence output of both SA2 are output only when they are obtained at the same time. It can pass through 7 26 and is obtained as a coincidence output SA from OR gate 2 25.
  • FIG. 90 shows an embodiment in which the measurement time of the cycle of the input clock CK is generalized as described in the waveform shaping circuit. As described in the waveform shaping circuit, the multiplied output obtained as the output is based on the input clock CK. The longer the period measurement time, the higher the signal purity (less spurious or low jitter).
  • the count output of the counter 27 receiving the output of the delay line oscillator 21 changes from a state where the count value is not an original count value due to a delay time inherent in the count operation to a pulse that is very narrow with the increase in the count number. May occur.
  • the state power of the increase in the count output merely reduces the frequency of the state where the count value is not the original count value, and the occurrence thereof is reduced to zero. Can not be.
  • the circuit configuration becomes more complicated and the power consumption is liable to increase as compared with the case of the non-synchronous counter.
  • the output of the delay line oscillator 21 is operated in two types of positive and negative phase stages (operating in two types of rising and falling phase stages). , And a method of counting at the same time can be considered. According to the above measures, a new arithmetic circuit is prepared separately from the arithmetic circuit 19, and a counter 27 and a new counter of the measurement circuit 20 are prepared.
  • the output of the arithmetic circuit 19 is used as one input, A matching circuit 28 that uses the other input as the output of the counter 27 of the measurement circuit 20 and an output of the new arithmetic circuit as one input and uses the other input as the output of the new counter of the measurement circuit 20 A new match circuit is prepared, and when both the match circuit 28 and the new match circuit output a match output, a match output of half the period of the clock CK can be obtained. .
  • the circuit configuration of each counter is simplified.
  • the power consumption is reduced, and a more accurate half-period coincidence output of the clock CK is obtained.
  • a multiplied clock CK can be obtained.
  • the power stage used is not an inverter, but a phase stage consisting of a number of delay circuits.A counter is provided for each phase stage. Similarly, the same number of latches, arithmetic circuits, and matching circuits are provided. It's okay to do that.
  • the outputs of the delay line oscillators 11 of the duty-one decision circuits 3 and 4 are operated in two types of positive and negative phase stages (rising It operates with two types of phase stages: falling and falling.)
  • Two counters are used to count at the same time, and the count result is also latched by two latches at the same time.
  • the values obtained by the latch are also calculated by a series of two sets of arithmetic circuits, and two sets of a series of matching circuits are similarly prepared.
  • the above is the problem of measuring the period of the clock CK.However, in the basic form shown in Fig.
  • the duty determination circuits 3 and 4 provide a counter 17 and a new counter, the output of the counter 17 is latched by the latch 18 and the output of the new counter is a new counter. Latch with latch. The output of the latch 18 is sent to the arithmetic circuit 19, while the output of the new latch is sent to the new arithmetic circuit. Further, the output of the counter 17 is applied to one input of the matching circuit 28, and the output of the arithmetic circuit 19 is applied to the other input of the matching circuit 28.
  • the output of the new counter is applied to one input of the new matching circuit, and the other input of the new matching circuit is applied to the output of the new arithmetic circuit.
  • the counters 17 of the duty-one determination circuits 3 and 4 do not have to be synchronous, so that the circuit configuration of each counter is simplified and the power consumption of each counter is reduced.
  • a coincidence output at a more accurate phase position corresponding to the content of the multiplication can be obtained with respect to the cycle of the clock CK, a more accurate multiplication output can be obtained.
  • the outputs of the delay line oscillators 11 and 21 are converted into two types of phase stages (phases of 0 ° and 180 °) using, for example, inverters 705 and 706.
  • phase stage consisting of a large number of delay circuits is prepared, and a counter is prepared for each phase stage.
  • a latch, an arithmetic circuit, and a matching circuit May be prepared in the same number.
  • RS-FF RS flip-flops
  • the configuration of the delay line transmission circuit illustrated in the cycle measurement circuit 10 and the measurement circuit 20 in FIG. 1 and the duty determination circuits 3 and 4 in FIGS. 3 and 5 has the minimum configuration, that is, The device is composed of one NAND and two inverters.
  • the circuit configuration using only the delay line oscillator is simple, but the oscillation frequency becomes extremely high, so that there is a problem that the power consumption is inevitably increased.
  • the counter for counting the delay line oscillator must be a very high-speed counter, and the peripheral circuits of the delay line oscillator also consume much power.
  • the delay time per stage of the flip-flop constituting the inside of the counter is one NAND as exemplified here. This is almost the same time as the transmission cycle of the minimum delay line transmitter consisting of two inverters.
  • the output frequency of the delay line transmitter may exceed the frequency that can be counted by the counter, and may not operate.
  • Figure 91 illustrates the above problem. Therefore, it is conceivable that the configuration of the above-mentioned delay line oscillator uses a circuit with a longer oscillation period, in which two or more combinations of one NAND and one inverter are prepared first. .
  • the transmission period of the delay line transmitter becomes longer, the measurement accuracy of the period of the input clock CK is reduced to less than half, and the frequency of the input clock CK is twice as long. It is conceivable that the detection accuracy at the phase position according to the content will be reduced to less than half.
  • the delay line oscillator is assumed to be an oscillator with many phase stages, and a new latch is combined for each phase stage to generate the input clock CK. Along with the latch performed when measuring the period, a new latch is also latched simultaneously for each phase stage of the delay line oscillator.First, roughly several times the period of the delay line oscillator is measured by a counter, and further delay is performed. Based on the results of the new latch outputs installed for each phase stage of the line transmitter, a fine phase result within one cycle of the delay line transmitter is also obtained.
  • the delay line transmitter is one set of NAND and two inverters 1, that is, if two phase stages of the delay line transmitter are provided, the delay line Based on the output of each latch connected to each phase stage of the transmitter, a phase result of at least one half cycle of the delay line transmitter can be obtained. Further, if the rising and falling states of each phase stage of the delay line oscillator are also determined, it is possible to obtain a phase result of 1/4 of one cycle of the delay line oscillator.
  • FIG. 92 and FIG. 93 show an embodiment in which the above measures are taken.
  • a DL—OSC composed of a large number of NANDs and inverters is configured in the phase coincidence detection circuit 861
  • taps for example, OSC_dl, OSC—d
  • OSC-dn observe the output of each of them at the same time, and obtain a coincident output based on the results, to further improve the phase accuracy, that is, the duty to 50% with high accuracy. Since the operating speeds of the counters 17 and 17B of the duty determination circuit can be reduced, the power consumption of these counters can be reduced.
  • FIG. 92 shows a specific embodiment in the case where the configuration of DL-OSC is two sets of NAND and inverter. With this configuration, the oscillation frequency can be reduced by half compared to the DL-OSC configuration shown in Fig. 93 (a), so that when using a C-MOS IC, the power consumption can be reduced by half. .
  • the configuration of the delay line oscillator consists of one NAND and four inverters.
  • each phase stage of the delay line oscillator is Based on the result of the output of each connected latch, a phase result of at least about one-fourth of one cycle of the delay line oscillator can be obtained, and similarly, the rise and fall of the delay line oscillator can be obtained. If the state is also determined, it is possible to obtain a 1/8 phase result of one cycle of the delay line oscillator.
  • the number of combinations is three according to the multiple, for example, in the embodiment of FIG. If the embodiment of FIG. 7 is applied to three delay times, if one arithmetic circuit and one matching circuit are considered as one combination, five combinations are required, and if the multiple becomes four times, Seven combinations are required.
  • FIG. 94 shows an example in which the above-described countermeasures are taken to improve the embodiment shown in FIGS. 86 and 87. Specifically, the part of the matching position detection circuit 890 in FIG. 86 is changed.
  • the arithmetic coefficient setting circuit 217 causes the arithmetic circuit 218 to sequentially perform an arithmetic operation to obtain a required coincidence output. Note that even if the counter 57 counts up to the maximum value and then returns to the initial state, no coincidence output is already obtained under the conditions at this time. After that, the initial state, that is, the clock input CK arrives again, and CKF is input again as in the original initial state. In this way, a desired multiplied output can be obtained.
  • FIG. 95 shows an example in which the other embodiments of FIGS. 86 and 87 are improved. In this case as well, specifically, the part of the coincidence position detection circuit 890 in FIG. 86 is changed.
  • the part of the coincidence position detection circuit 890 in FIG. 94 can be replaced with that in FIG.
  • the latch 2 15 Holds the first operation result from the operation circuit 19 that has been applied to the An side.
  • the SA output advances the counter 57 by one count.
  • the latch 2 15 is activated by the edge of the match output SA output from the matching circuit 28.
  • the adder 2 16 obtains the first operation result held by the arithmetic circuit 19 and the match output SA from the match circuit 28 for the first time.
  • a value twice as large as the value initially held by the arithmetic circuit 19 is input to the A 1 to A n inputs of the matching circuit 28. Will be added.
  • the arithmetic circuit 19 first holds and checks the value, and then sequentially matches one of the values of one of the match circuits 28 Since the input value changes, the edge position output of the multiplied output can be obtained as many times as necessary.
  • the Qn output of the counter 57 changes from the H level to the L level, As a result, since the AND gate 727 is closed, even if an erroneous coincidence output SA is output, the multiplying output no longer changes. In this way, a desired multiplied output can be obtained.
  • FIG. 96 shows an embodiment in which the multiple of the embodiment of FIG. 7 is generalized.
  • FIGS. 97 and 98 show an embodiment in which the multiple number is generalized and also generalized to include the measurement time of the period of the input clock CK as described above.
  • FIG. 99 as described in FIG. 94, the operation value of the operation circuit 218 is controlled using the operation coefficient setting circuit 217, and the entire circuit configuration is shown in FIG. It shows an embodiment that can be configured more simply than the embodiment. Note that, in this embodiment, unlike the case of FIG. 94, when the last coincidence output for obtaining the required delay multiplication output is obtained by the counter 57 the required number of times, the count output of the counter 57 is output. Through the gate 2 14 to reset the RS flip-flop 6.
  • FIG. 100 also shows an embodiment in which the period measurement time of the input clock CK is generalized, similarly to the related art.
  • the value to be matched by the matching circuit is sequentially increased by the action of the adder 216 every time an output edge, that is, a matched output SA is obtained.
  • the circuit configuration can be made much easier than in the embodiment.
  • FIG. 102 also generalizes the measurement time of the cycle of the input clock CK as in the conventional description.
  • FIG. 103 is a further simplified version of the circuit of FIG. 1 and shows an embodiment applied to a multiplication circuit. Things.
  • the advantage of this circuit is that unlike the circuit of Fig. 86 applied to the multiplier circuit of Fig. 1, there is no need to prepare a CKW that requires a delay circuit, as described in the embodiment of the waveform shaping circuit. Therefore, stable operation can be performed over a wide frequency band.
  • FIG. 104 shows an embodiment in which the measurement time of the cycle of the input clock CK is generalized in the embodiment of FIG. 103.
  • FIG. 105 (i-10) Forty-fourth embodiment: FIG. 105
  • FIG. 105 shows a case where the operation value of the operation circuit 218 is controlled using the operation coefficient setting circuit 217 in the same manner as described with reference to FIG. 94, and the overall circuit configuration is compared with the embodiment of FIG. 9 illustrates an embodiment that can be configured more simply.
  • the count output of the counter 57 is changed to the logical output. It is passed for the first time using a logic gate 214 composed of an integrated circuit, at which time the coincidence output SA from the coincidence circuit 28 is passed for the first time by the AND gate 215, and the RS flip-flop 892 is reset.
  • Fig. 106 also shows a generalized version of the input clock CK period measurement time, as in the past. This is an embodiment of the present invention.
  • the number of lines to be matched by the matching circuit is sequentially increased by the operation of the adder 216 each time an output edge, that is, a matched output SA is obtained.
  • the circuit configuration can be simplified much more than the embodiment of FIG. 87.
  • FIG. 108 also shows an embodiment in which the period measurement time of the input clock CK is generalized as in the conventional case.
  • the matching circuit and the arithmetic circuit need only be one set irrespective of the multiplication factor. There is.
  • the function of the arithmetic circuit may be the same as the conventional one.
  • a new adder and a new latch are provided, and the output of the arithmetic circuit 219 is once added to the conventional matching circuit 222 through the adder, and the newly provided latch is provided.
  • the output of the new latch is applied to the other input of the new latch, and the new latch latches each time a match output from the conventional match circuit 222 is obtained.
  • the contents from (a) period measurement to (j) improvement of the arithmetic circuit and the matching circuit described above may be performed individually and independently, or may be performed simultaneously by combining all the contents. However, depending on the combination, not only the performance does not return but also the cost increases due to the power. For example, in (a), the duplexer having a simpler configuration and in (b), the period measurement are individually described, but the number of stages may be increased by combining them.
  • the operation of the duplexer described so far has been based on the premise that the output duty is as close to 50% as possible.
  • two-phase clocks with different duties are used. May need. These two phases (two types) of clocks have a phase relationship such that they are not simultaneously at the same level (H level or L level). If one of the two kinds of signals has a duty of 50%, the other greatly deviates from the duty of 50%, so that the frequency of the clock apparently increases, which is not preferable. Therefore, in both cases, the duty may be slightly shifted from 50% for output.
  • FIG. 109 and FIG. 110 explain the above and show the operation of the duty fine adjustment circuit 871, which can take countermeasures.
  • Fig. 7 2 and Fig. 7 As described in the duty fine adjustment circuit 870 of Fig. 3, also in the duty fine adjustment circuit 871 of Fig. 109, the delay circuits 765 and 766 are replaced by delay circuits with delay times unique to this device.
  • OR-1 is directly used, that is, an OR gate, 5d output is used.
  • the output of OR-2 in the case of FIG. 7 or a similar embodiment, the output of OR-2, that is, the output of the OR gate 33 is used as it is.
  • the coincidence output SA is used.
  • FIG. 110 which is a timing chart showing the operation of FIG. 109, and, as can be seen from the above description, a combination of the duplexer of the present invention and the duty fine adjustment circuit 871, By doing so, the CK-110 output and the CK-120 output of the duty fine adjustment circuit 871 have a phase relationship such that the desired two do not become the same level (H level or L level) at the same time. In addition, both of them can obtain an output as close as possible to a duty of 50%.
  • the input CK described so far has been considered on the assumption that the CK has a very high accuracy, such as a crystal oscillator.However, the phase accuracy, such as the horizontal synchronization signal obtained from a VTR, decreases. Such a signal may be used. When handling such a signal, the phase position of the horizontal synchronizing signal may fluctuate due to, for example, extension of the video tape, fluctuations in the number of revolutions of the motor, and the like. However, in order to generate a signal that can be displayed on a liquid crystal display, for example, from such a signal, a signal that is synchronized with the edge position of the horizontal synchronizing signal and that is a positive multiple of the horizontal synchronizing signal may be required.
  • the frequency division ratio of the timing generation circuit 2 may be set to be larger than that of the basic mode of FIG. Then, by setting the required multiplied number and outputting the desired multiplied output from the edge position of the horizontal synchronizing signal, it becomes possible to capture signals such as RGB signals. And a flat panel display such as an EL display can be accurately displayed.
  • the horizontal sync signal phase position is slightly deviated, it is considered that a display problem may occur.
  • the left end that is, the horizontal sync signal
  • the display is sequentially performed to the right, so that the vertical lines of the displayed pixels are not disturbed. That is, in the case of the present invention, a stable dot clock of 3 ⁇ 4m times the horizontal synchronization signal is obtained, and the phase is instantaneously synchronized with the position of the edge of the horizontal synchronization signal, which is not a function of the conventional PLL.
  • the output function is also provided.
  • FIG. 11 shows an embodiment of the present invention in which an actual circuit is configured based on the above.
  • the narrow pulse generation circuit 600 After receiving the horizontal synchronization signal H—SYNC, the narrow pulse generation circuit 600 removes an erroneous signal such as noise, and sets the edge of the horizontal synchronization signal to S—TRIG. Supplied to delay multiplication circuit 201. When it is not necessary to consider that an erroneous signal such as noise is mixed in the horizontal synchronizing signal, the narrow pulse generating circuit 600 is not necessary.
  • the frequency doubling circuit 201 of the present invention which receives S-TRIG from the narrow pulse generating circuit or directly receives the horizontal synchronizing signal H-SYNC, is capable of stabilizing the period of the dot clock to be reproduced as much as possible. After the period of the horizontal synchronizing signal is measured for as long a period as possible, that is, over as many periods as possible, a predetermined multiplying output is output. As a result, without using a PLL circuit, it is possible to output a dot clock that is stable, has a very wide bandwidth, does not require adjustment, and can have an appropriate response characteristic. Become.
  • reference numerals 206, 207, and 208 denote AZD converters that can convert the RGB output, which is a so-called color signal, from analog to digital.
  • the obtained multiplied output is output as a dot clock and also supplied as a clock signal for these AZD converters.
  • FIG. 112 is a timing chart showing the above relationship.
  • FIG. 11A shows an example in which a clock signal required for the CPU is supplied at a high frequency.
  • the distance 1 from the clock generator 351 to the CPU is far and the clock frequency is very high, problems such as noise generation, increased power consumption, and difficulty in handling occur. I was.
  • FIG. 113 (b) is an embodiment of the present invention which solves the above problems.
  • the frequency doubling circuit 201 of the present invention is used. This solves the above problem.
  • the frequency delay doubler of the present invention may be used in combination with the duty fine adjustment circuit 871 described with reference to FIG.
  • FIG. 14 shows a state in which the CPU 361, the counter 57, the A / D converter 206, etc. are connected by the same board or cable, and the same clock generator 351 supplies a high frequency clock CK. Things. In the case of such a configuration, there is the same problem as described with reference to FIG.
  • FIG. 115 is an embodiment of the present invention for solving the above problem.
  • the CPU 361, the counter 57 and the A / D converter 206 Alternatively, the frequency doubler 201 of the present invention is used by integrating with those devices. This solves the above problem.
  • FIG. 114 shows the state of a so-called parallel computer in which the CPUs 361, 362 and 363 are connected by the same board or cable and supply a high-frequency clock CK from the same clock generator 351. .
  • This configuration also has the same problem as described with reference to FIG. At the same time, unlike the conventional case, it is necessary to make the same including the phase of the input clock CK supplied to each CPU.
  • FIG. 117 shows an embodiment of the present invention for solving the above problem.
  • the frequency multipliers 201, 201 B, and 201 C of the present invention are used near the CPU 361, the counter 57, and the A_D converter 206, or integrated with those devices, and In order to make the phases the same, the phase adjustment circuits (delay circuits) 202 and 202C described in FIGS. 80 to 82 are used. This solves the above problem.
  • FIGS. 9, 10, 14, and 20 which show the basic form of the external synchronization method and the external synchronization circuit, the components have been described so far. Many of the elements are almost the same as those used in the waveform shaping circuit and the frequency multiplier circuit. That is, in the external synchronization method and the external synchronization circuit, the improvement performed in the waveform shaping circuit and the frequency doubling circuit and the like may be similarly performed.
  • the circuit excluding the timing generation circuit 2 is basically the same as the circuit of FIG. 5 showing the embodiment of the waveform shaping circuit.
  • the configuration used was a pair. If the output is not multiplied, this is one of the circuits in FIG. 3 showing an embodiment of a simpler configuration of the waveform shaping circuit. It can be seen that the configuration may be such that four sets of circuits are removed, excluding the ringing generation circuit 2.
  • the accuracy of the output signal is slightly lowered (duty becomes 50% in principle), and if it does not cause a serious problem, a diagram showing an embodiment having a simpler configuration of the waveform shaping circuit will be described.
  • a set of circuits except for the timing generation circuit 2 is first prepared, and then only the measurement circuit 20 and the matching circuit 28 in the same embodiment of FIG. 1 are extracted. It is also possible to adopt a configuration integrated with the initially prepared circuit. In this case, one input of the newly added matching circuit is connected in parallel with the connection from the already prepared arithmetic circuit to the already connected matching circuit. The output of the counter 27 of the newly added measuring circuit 20 is connected to the other input of the newly added matching circuit. If these two coincidence outputs are used as new coincidence outputs via a newly added OR gate, an external synchronization method and synchronization circuit with a simpler configuration can be realized. An external synchronization method and an external synchronization circuit having a simpler configuration based on the above may be used.
  • the cycle measurement of the input clock CK was performed in one cycle of the input clock, but this is not limited to one cycle, and may be m cycles (m is an integer of 2 or more).
  • This can be applied to a new embodiment in which the new circuit configuration incorporating the contents supplemented by the simpler circuit configuration (a) is applied to the circuit of FIG.
  • the frequency division of the frequency divider forming the timing generation circuit 2 shown in FIG. It is possible to respond by changing the ratio.
  • the technical improvement by measuring the period of the input clock CK at m periods (m is an integer of 2 or more) is that the accuracy of the measurement of the period of the input clock CK is improved.
  • the duty ratio of the pulse of the output signal obtained from the external synchronization circuit can be made closer to 50% with higher accuracy.
  • FIG. 118 and FIG. 119 show the input clock applied to the external synchronizing circuit, that is, EXT-TRIG in this embodiment. This shows an embodiment in which the measurement time of the clock cycle is twice as long as the conventional one.
  • the embodiment illustrated here is a diagram that is shown as an embodiment that operates as a combination of FIG. 9, FIG. 10 and FIG.
  • the operation is performed by using FIG. 118 instead of FIG. 9, and by using the embodiment of FIG. 119 instead of FIG.
  • the input clock EXT-CK applied to the external synchronization circuit is divided by one to four by two flip-flops 771 and 772.
  • lines with the same signal name are connected.
  • the input clock that is, the EXT-CK cycle is measured in two cycles, unlike the past, so that the cycle measurement accuracy is in principle higher than in the past.
  • the pulse duty of the output signal obtained from the external synchronization method and the external synchronization circuit should be closer to 50% with higher accuracy and in principle twice as accurate as before Can be.
  • FIG. 120 and FIG. 121 show the measurement time of the period of the input clock EXT-CK applied to the external synchronization circuit in the same manner as described above and the waveform shaping circuit and the frequency multiplication circuit.
  • the embodiment in the case of hit is shown.
  • the connection is made by a combination of FIG. 120, FIG. 121, and FIG. 9, and the connection method is the same as in the conventional case. Just connect the names. If this connection is made and operation is performed, the measurement of the input clock, that is, the EXT-CK cycle is performed for m (m is an integer of 2 or more) cycles, which is different from the conventional method.
  • (b-3) 56th embodiment FIG. 120, FIG. 121, and FIG.
  • FIG. 119 which includes the duty determination circuit 3 is similar to the external synchronization circuit shown in FIG. Even if the configuration is changed to another basic embodiment, that is, FIG. 20, the same operation can be performed as an external synchronization circuit.
  • the same effect as when the external synchronization circuit is configured by the combination of FIG. 118, FIG. 119 and FIG. 9 can be obtained.
  • the measurement time of the clock cycle indicated as EXT-TRIG has been extended twice as long as before, so that the measurement accuracy of the clock cycle can in principle be doubled as compared with the conventional one.
  • the pulse duty of the output signal obtained from the external synchronization method and the external synchronization circuit can be closer to 50% with higher accuracy and in principle twice as accurate as the conventional one.
  • FIG. 120, FIG. 9 and FIG. 20 also operates as an external synchronization circuit as in the case of the combination of FIG. 118, FIG. 20 and FIG. Is possible.
  • this combination in the case of the wave type circuit and the frequency doubler circuit, and similarly to the embodiment by the combination of FIG. 120, FIG. 121 and FIG. An embodiment in which the measurement time of the XT-CK cycle is generalized will be described.
  • the lZMCK-A2ZB2 in Fig. 120 goes to 1K2CK-A2NOB2 in Fig. 20 and the WCM-A1 in Fig. 120.
  • B1 connects to WC-Al / B1 in FIG. 20
  • WCM-A2 / B2 in FIG. 120 connects to WC-A2 / B2 in FIG.
  • TRIG-STOP A and TRIG-STOPB in Fig. 9, which have no other similar signal names, are left open (no connection is made).
  • the input clock EXT-CK is synchronized with the external trigger EXT-TRIG to output a CK with a desired duty cycle.
  • the circuit configuration of the part that functions to output the coincidence output by multiplying the frequency as necessary is the minimum configuration, It shows a circuit configuration that is equivalent in terms of performance and that is the least expensive compared to one that operates with a larger-scale circuit configuration than the one that operates.
  • the duty determination circuit 3 of the component is Although it has a four-stage configuration, this may be an m-stage configuration (m is an integer of 5 or more). In that case, however, the circuit configuration becomes larger and the cost increases, but the performance (accuracy of the output signal after doubling) does not increase so much. For example, assuming a case where EXT-TRIGs continuously arrive in a very short time, even in such a situation, a large number of duty determination circuits are sequentially assigned. Since the required clock can be reproduced and output, there is an advantage that circuit operation flexibility is enhanced.
  • the duty determination circuits 3 and 4 each have two sets of configurations, but it is also possible to use three or more sets of circuit configurations. However, in this case, the circuit configuration becomes larger and more complicated, and the cost increases, but the performance Waveform shaping accuracy).
  • an L level signal and a POWER ON RESET signal are output.
  • a power-on reset signal generation circuit 810 capable of outputting the same signal may be prepared.
  • the power-on reset signal generation circuit 810 may be used in combination as a component of the timing generation circuit 14. More specifically, the output of the power-on reset signal generation circuit 810 is controlled by the RS of the duty-one determination circuit 3 in the embodiment shown in FIGS. — An RS circuit should be inserted before the reset input R of FF 6 and RS of the duty decision circuit 4 and RS — FF 8, and the same connection as in FIG. 55 should be made.
  • the latch circuit that constitutes the duty decision circuit 3 or 4 in Fig. 48 can operate without retaining data, which is erroneous immediately after power-on. Makes it possible to obtain a stable output.
  • FIGS. 119 and 121 and similar circuits performing the same operation are similar circuits performing the same operation.
  • (d-2) Fifty-ninth embodiment: Figs. 56, 58 and 60
  • the operation is considered assuming that the cycle of the input clock CK does not change in the middle, but if the cycle of the input clock CK fluctuates greatly in a short time, the same situation as described above, namely, With respect to the cycle of the input clock CK, a coincidence output was not obtained at the time of the desired cycle, and as a result, a situation was assumed in which the desired output could not be obtained forever.
  • the configuration of the timing generation circuit 302 shown in FIG. 14, FIG. 118 or FIG. It is necessary to periodically reset the output value of the counter 47, which performs the period measurement operation, to a state of all zeros shortly before the state in which the period of the input clock EXT-CK is measured.
  • the duty one decision circuit 3 completes the operation of determining the duty 1, for example, in the example of FIG.
  • the L level signal RESET signal is output every time or intermittently, and the counter 4 of the duty decision circuit 3 7 is forcibly set to the clear level for a certain period of time (that is, all count values are at the L level).
  • the data of the latch 48 is always held at the L level, and the duty is determined again.
  • the period measurement operation may be performed in a state according to the basic mode.
  • each RS-FF 6 of the two duty determination circuits 3 and the reset input of each RS-FF 8 of the two duty determination circuits 4 An OR circuit may be inserted before each input to make the same connection as in Fig. 58. Also, the R ESET signal to be added to the OR input should be supplied based on the embodiment of FIG. The same applies to FIG. 20, FIG. 119 and FIG. 121, and their similar circuits that perform the same operation.
  • the new embodiment improved from FIG. 9 only reduces the frequency at which the measurement of the phase position of the incoming EXT-TRIG is not performed accurately, and the The occurrence of inaccurate measurements cannot be zero.
  • the counter 312 is constituted by a synchronous counter, the circuit configuration becomes more complicated and the power consumption is more likely to be increased than when the counter is not synchronous.
  • the output of the delay line oscillator 314 is operated in two types of positive and negative phase stages by using an inverter (two types of phases, rising and falling). It uses two counters to count at the same time, and the counting result is also latched at the same time by two latches. It is also conceivable to prepare two matching circuits in the same way. The above can be specifically performed by referring to the embodiment shown in FIG.
  • the delay line oscillator 3 14, which is output without using the inverter of the phase position assigning circuit 3 12, performs the counting operation with the conventional counter 3 2 0 and latches 3 2 1
  • the matching circuit 3 2 2 has the same connection.
  • the signals output by inverting the delay line oscillators 3 14 using an inverter are counted by a new counter 2 and are similarly connected to a new latch and a new delay circuit.
  • the desired coincidence output was obtained. There is a way to do it.
  • the counters 3 0 of the phase position assigning circuits 3 12 and 3 13 do not have to be synchronous, so that the circuit configuration of each counter is simplified, and Each power consumption is also reduced, and a coincidence output at an accurate phase position with respect to the clock EXT-CK period is obtained, so that an output with higher synchronization accuracy is obtained.
  • the outputs of the delay line oscillators 11 and 21 are operated in two types of phase stages (0 ° and 1-80 ° phase stages) using an inverter. More delay circuits may be prepared, counters may be prepared for each delay circuit, and similarly, the same number of latches and matching circuits may be prepared.
  • FIG. 122 is a diagram in which an entire circuit for measuring the arrival position of the external trigger (in which phase of the input clock C the EXT TRIG was input) and reproducing the same in FIG. 9 is extracted.
  • the number of stages of the phase position providing circuits 312 and 313 is two.
  • the conventional timing generation circuit 311 may have a configuration in which the timing generation circuit is configured to have three phases to stabilize the operation by increasing the design margin.
  • FIG. 124 is a diagram showing the operation of each part of the new timing generation circuit 311.
  • FIG. 125 is a diagram corresponding to the overall view of FIG. 122 when the timing generation circuit is changed to three types of phase outputs.
  • the configuration of the phase position providing circuit 312 may be changed so as to be further generalizable, and may be configured as shown in FIG. 126 and FIG. 127.
  • the merit of such a configuration is that the operation of the circuit is more stable because the delay time setting margin can be wider than when the configuration of the phase position providing circuit is only two stages. Also, since the phase given by the phase position assigning circuit may be smaller than in the conventional case with a small number of stages, the accuracy of the phase assigning can be improved in principle, and consequently the output signal synchronization Accuracy can be increased.
  • the delay time of the counter 47 it is possible to reduce the delay time by using a synchronous counter than by using a non-synchronous counter, but to make the delay time itself zero It is not possible. Also, even if the delay time can be made very small, the embodiment shown in FIGS. 10 and 20 only reduces the frequency with which the delay time measurement is not accurately performed, and increases the inaccuracy. The occurrence of measurement cannot be reduced to zero. In addition, when the counter 47 is configured by a synchronous counter, the circuit configuration becomes more complicated and the power consumption is more likely to be increased than when the counter is not synchronous.
  • the outputs of the delay line oscillators 41 of the duty determination circuits 3 and 4 are converted into two types of positive and negative phases using an inverter. Operates in two stages (operates in two types of phase stages, rising and falling). A method is used in which two counters are used to count at the same time, and the count result is also latched by two latches at the same time. It is also conceivable that the value obtained by the latch is also calculated by two arithmetic circuits, and two matching circuits are similarly prepared. The above is the problem of measuring the period of the clock CK.However, in the embodiment of FIG. 10, since the same circuit generates the phase position signal according to the setting conditions, the problem of the counter delay time has already been solved. Have been.
  • the duty determination circuits 3 and 4 provide a counter 47 and a new counter.
  • the output of the counter 47 is latched by the latch 48, and the output of the new counter is output by the new latch. Latch.
  • the output of the latch 48 is sent to the arithmetic circuit 49, while the output of the new latch is sent to a new arithmetic circuit.
  • the output of the counter 47 is applied to one input of the match circuit 50, and the other The output of the arithmetic circuit 49 is added to the input of.
  • the output of the new counter is applied to one input of the new matching circuit, and the other input of the new matching circuit is applied to the output of the new arithmetic circuit.
  • phase stages (0 ° and 180 ° phase stages) are prepared by using the output of the delay line oscillator 41 using an inverter, and the operation such as counting is performed.
  • a delay stage composed of a large number of delay circuits may be prepared, a counter may be prepared for each phase stage, and similarly, the same number of latches, arithmetic circuits, and matching circuits may be prepared.
  • RS-FF RS flip-flops
  • a method can be considered in which the time when all RS flip-flops are changed by the coincidence output in addition to the input of the flip-flop is the time when a true coincidence output is obtained.
  • a true coincidence output with a stable pulse width Is obtained.
  • the configuration of the illustrated delay line transmission circuit is the minimum configuration, that is, the element is configured with one NAND and two inverters.
  • the circuit configuration using only the delay line oscillator is simple, there is a problem that the power consumption is inevitably increased because the oscillation frequency is extremely high.
  • the counter for counting the delay line transmitter must be a very high-speed counter, and the peripheral circuits of the delay line transmitter also consume much power.
  • the delay time per flip-flop constituting the inside of the counter is equal to one NAND shown in this example. The transmission time is almost the same as the transmission cycle of the delay line transmitter with the minimum configuration consisting of two inverters.
  • the output frequency of the delay line transmitter may exceed the frequency that can be counted by the counter, and may not operate. Therefore, it is conceivable that the above configuration of the delay line oscillator uses a circuit with a longer oscillation period, in which two or more combinations of one NAND and one inverter are prepared first.
  • the measurement accuracy of the cycle of the input clock CK decreases to less than half, and the cycle of the input clock CK depends on the content of the input clock CK. It is conceivable that the detection accuracy at the shifted phase position is also reduced to less than half.
  • the delay line transmitter consists of one NAND and two inverters, i.e., two phase stages of the delay line transmitter are provided, the delay line transmitter Based on the result of the output of each latch connected to each phase stage of the device, a phase result of at least one half cycle of the delay line oscillator can be obtained. Furthermore, if the rising and falling states of the delay line oscillator are also discriminated, it is possible to obtain a phase result of 1 Z4 of one cycle of the delay line oscillator.
  • the delay line oscillator Based on the results of the outputs of the latches connected for each phase stage, at least a phase result of about 1 to 4 in one cycle of the delay line oscillator can be obtained. By judging the falling state and the falling state, it is possible to obtain the phase result of 1Z8 of one cycle of the delay line oscillator.
  • FIG. 128 is an embodiment showing that the external synchronization circuit and the external synchronization method described so far can be applied to a doubling circuit.
  • the reason why the multiplication circuit can be realized is also briefly described.
  • FIG. 7 which is the embodiment of the multiplication circuit
  • FIG. 10 which is the embodiment of the external synchronization circuit
  • the basic difference in the operation of the output part is that after the arrival of the externally applied reference clock input EXT-CK, the duty determination circuit 3 performs the desired phase position only once. The only difference is whether the coincidence output SA was output or the odd number (three times in FIG. 7) of the coincidence output SA was output.
  • FIG. 10 assumes that the coincidence output is obtained a plurality of times. Also, unlike in Fig. 10, the final output section outputs a coincidence output SA every time it arrives. Since there is no changeable flip, in the method based on this circuit, even if the internal configuration of the duty decision circuit 3 is changed to that shown in FIG. You cannot have it.
  • the duty ratio determining circuit 3 in FIG. 7 which is basically an embodiment of the duplexer, and FIG. 10 which is an embodiment of the external synchronization circuit diagram are combined as an external synchronization method and an external synchronization circuit.
  • 3 shows a new embodiment of the synchronization circuit.
  • the duty determination circuit 3 shown in FIG. 128 can be applied to the embodiment of FIG. 10 and similar embodiments. It shows that. More specifically, for example, in the circuit of FIG. 129, if the duty-one determination circuit 3 is replaced with the embodiment of FIG. 128, the external trigger and EXT-TRIG can be synchronized and the stable input from the outside can be achieved. It is possible to output a stable clock at a frequency that is an integral multiple of the clock EXT-CK. As a more detailed overall circuit configuration, a circuit may be configured by combining the embodiments shown in FIGS. 128, 129, 14, and 9.
  • FIG. 14 which is a specific example of the timing generation circuit 302 in the embodiment of FIG. It is possible to generalize the measurement time of the period of the external input clock EXT-CK by replacing the configuration shown in FIG. As described in the operation of the waveform shaping circuit, the measurement accuracy of the input clock EXT-CK can be improved if the measurement of the period of the input clock EXT-CK is set longer than the period of the conventional embodiment.
  • the duty determination circuit 3 by adopting the following configuration of the duty determination circuit 3 in these embodiments, the accuracy of the multiplied output waveform (frequency purity, phase fluctuation , Pulse width variation, Furthermore, the duty ratio can be closer to 50%).
  • the operating speed of the counter 47 shown in FIG. 130 can be reduced, and the power consumption can be reduced. Note that if the delay line oscillator has a multi-stage configuration, the accuracy of the output of this duplexer will decrease, so the same measures as described in the multipliers 92 and 93 and the waveform shaping circuit diagram 69 will be taken. It is desirable.
  • the combination of the matching circuit 501 and the arithmetic circuit 491 is replaced with a combination of many odd-numbered circuits. If changed, it becomes possible to output with a higher magnification ratio, instead of the triple magnification shown in FIG. In this case, the specific combinations of the circuits are as shown in FIGS. 129, 132, 14 and 9.
  • FIG. 120, FIG. 130, FIG. 133, and FIG. 9 Sixty-fifth embodiment: FIG. 120, FIG. 130, FIG. 133, and FIG. 9
  • a circuit is configured by a combination of FIG. 120, FIG. 130, FIG. 133, and FIG. Since it can be set arbitrarily and the measurement time of the period of the external input clock EXT-CK can be generalized, the measurement of the period of the input clock E can be one cycle of the conventional embodiment. Rather, setting it longer will increase the measurement accuracy of the input clock EXT-CK, so the accuracy of the multiplied output waveform (frequency purity, phase variation, pulse width variation, Duty ratio approaching 50%).
  • the measurement time of the cycle of the input clock EXT-CK is set arbitrarily and the measurement is performed as described above. If the time is set longer, rather than one cycle of the basic form, the measurement accuracy of the input clock EXT-CK will be higher, so the accuracy of the waveform of the multiplied output (frequency purity, phase fluctuation, pulse Width fluctuation, and the duty ratio is closer to 50%), and without increasing the number of combinations of matching circuits and arithmetic circuits, it is possible to increase the duty ratio of the signal taken out as an output. It becomes possible.
  • FIG. 13 4 was changed to the embodiment of FIG. 13 36, and accordingly, the duty-one determination circuit 3 of FIG. 13 6 was changed to that shown in the embodiment of FIG. Even in the same manner as described above, it is possible to obtain an output clock with an arbitrary magnification ratio without increasing the number of combinations of matching circuits and arithmetic circuits.
  • Fig. 1336 is replaced with the embodiment of Fig. 13 37, and the internal duty determination circuit
  • the measurement accuracy of the input clock EXT-CK is further improved as described above, so that the accuracy of the multiplied output waveform (frequency purity, phase Fluctuations, pulse width fluctuations, and even closer to 50% duty), and without increasing the number of matching circuits and arithmetic circuit combinations, it is possible to multiply the signal taken out as an output.
  • the ratio can be arbitrarily increased.
  • FIG. 7 showing the embodiment of the duplexer, the coincidence output which is the basic for performing the multiplier is shown.
  • a combination of an arithmetic circuit and a matching circuit consisting of at least three sets of a matching circuit 222 to 224 and an arithmetic circuit 219 to 221 is used.
  • three combinations are prepared according to the multiple, for example, in the embodiment of FIG. If the embodiment of FIG. 7 is applied to three times, if one arithmetic circuit and one matching circuit are considered as one combination, five combinations are required, and if the number of times becomes four times, Seven combinations are required.
  • the conventional method has a problem that the circuit scale becomes large in the number of combinations of the arithmetic circuit and the matching circuit described above (k). Delete the arithmetic circuits 2 0 and 2 2 of 7, and also delete the —matching circuits 2 2 3 and 2 2 4. By improving the function of the remaining arithmetic circuit 219, a new arithmetic that can control the coefficient of the operation from outside (for example, the coefficient of division.
  • the coefficient is 2; if divided by 4, the coefficient is 4) It would be good if the circuit was replaced with a circuit, and furthermore, by using the coincidence output obtained from the coincidence circuit, for example, a circuit could be set so that the coefficient of a new arithmetic circuit could be set each time a coincidence output was obtained. Since there is only one match circuit, there is only one match output. Then, by adding this coincidence output to the D flip-flop's peak input of the width creation circuit, the desired multiply output can be obtained.
  • the matching circuit and the arithmetic circuit need only be one set irrespective of the multiplication factor. There are very advantages in terms of.
  • the function of the force arithmetic circuit may be the same as the conventional one.
  • a new adder and a new latch are provided, and the output of the arithmetic circuit 219 is temporarily added to the conventional matching circuit 222 through the adder, and also added to the input of the newly provided latch, and the output of the new latch is added.
  • the new latch latches each time a match output from the conventional match circuit 222 is obtained, and as a result, the signal to be multiplied is multiplied.
  • addition is performed by a new adder, and addition is sequentially performed so that a coincident output is obtained at a new phase position.
  • the contents from (a) the simpler circuit configuration described above to the period measurement to the improvement of the arithmetic circuit and the matching circuit may be performed individually, or all the contents may be combined simultaneously. You may go. Depending on the combination, some combinations may not only increase performance but also increase cost.
  • the input CK described so far has been considered on the assumption that the CK has a very high accuracy, such as a crystal oscillator.However, the phase accuracy, such as the horizontal synchronization signal obtained from a VTR, decreases. Such a signal may be used. When dealing with such a signal, the phase position of the horizontal synchronizing signal may fluctuate due to, for example, expansion or contraction of the video tape, fluctuation in the number of rotations of the motor, and the like. However, in order to generate a signal that can be displayed on a liquid crystal display, for example, from such a signal, a signal that is synchronized with the edge position of the horizontal synchronizing signal and that is a positive multiple of the horizontal synchronizing signal may be required.
  • the division ratio of the timing generation circuit 2 is set to the value of the embodiment of FIG. Should be larger than Then, by setting the required multiplied number and outputting the desired multiplied output from the edge position of the horizontal synchronization signal, it becomes possible to capture video signals such as RGB signals, and the This makes it possible to display the touch panel display with high accuracy.
  • connection shown in the embodiment of FIG. 138 may be performed.
  • reference numeral 205 denotes an external synchronization method and an external synchronization circuit of the present invention, to which a horizontal synchronization signal H-SYNC is added as EXT-TRIG.
  • the horizontal synchronizing signal is passed through the narrow pulse generation circuit 601 in advance, and the noise on the whisker is reduced. After removing the signal, the signal may be changed to S-TR IG and then applied to the EXT-TR IG input.
  • a clock such as a crystal oscillator having a very high frequency stability is prepared and connected. Just do it.
  • the output terminal OUT 205 of the present invention has the same frequency as that applied to the input terminal CK 205, or the desired multiplied frequency, and is synchronized with the horizontal synchronization signal edge. It is possible to obtain a constant (duty, frequency, and phase accuracy is very stable) dot clock.
  • the dot clock is supplied to AZD converters 206, 207, and 208 for converting three types of video signals, so-called RGB, into analog digital signals.
  • AZD converters 206, 207, and 208 for converting three types of video signals, so-called RGB, into analog digital signals.
  • a flat panel display such as an EL display can be accurately displayed.
  • the present invention as described above, it is possible to provide a waveform shaping circuit that is shaped into a waveform with a duty of 50% and output, regardless of whether or not the input signal has a duty of 50%. . Further, according to the present invention, it is possible to provide a practical frequency doubling circuit which has a simple configuration and is shaped into a waveform with a duty of 50% and output.
  • the input signal can be synchronized with the external trigger signal, the configuration is simple, and a practical external synchronization in which the input digital signal is shaped into a 50% duty waveform and output.
  • Method and external synchronization circuit Can be provided. According to the present invention, even if the external trigger signal fluctuates, it is possible to provide an external synchronization method and an external synchronization circuit that can automatically synchronize the output clock following the fluctuation.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne un circuit de mise en forme d'onde, permettant d'émettre un signal possédant une forme d'onde à 50 % de service à partir d'un signal de sortie, indépendamment du fait que ce signal soit utilisable ou non à 50 %. Un circuit de définition de service calcule et spécifie la position de temporisation d'un signal d'horloge à émettre à 50 % de service, lors de la réception d'un signal de temporisation produit par un circuit de génération (2) de temporisation. Le circuit de définition de service comprend un circuit de mesure de période (10) destiné à mesurer la longueur de chaque période apparaissant à intervalles réguliers, chacune étant égale à un multiple entier des N périodes d'un signal d'horloge (CK) d'entrée émis, un circuit de calcul (19) permettant de calculer la moitié du temps des N périodes, à partir de la longueur de chaque période, un circuit de mesure (20) permettant de mesurer la longueur de chaque période pour chaque intervalle, et un circuit de coïncidence (28) permettant d'émettre un signal de coïncidence égal à la position de temporisation du service à 50 %, lorsque la valeur mesurée coïncide avec la valeur calculée. Un signal d'horloge possédant une largeur d'impulsion correspondant au service à 50 % est produit sur la base d'un signal synchronisé avec le bord avant du signal d'horloge (CK), et la position de temporisation est déterminée et spécifiée par le circuit de définition de service et émise.
PCT/JP1999/002321 1998-05-05 1999-04-30 Circuit de mise en forme d'onde numerique, circuit de multiplication de frequence, circuit de synchronisation exterieure, et procede de synchronisation exterieure WO1999057811A1 (fr)

Applications Claiming Priority (2)

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JP10137742A JPH11317662A (ja) 1998-05-05 1998-05-05 デジタル波形整形回路、周波数逓倍回路並びに外部同期回路及び外部同期方法
JP10/137742 1998-05-05

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WO1999057811A1 true WO1999057811A1 (fr) 1999-11-11

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JP2010136002A (ja) * 2008-12-03 2010-06-17 Renesas Electronics Corp 遅延回路

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200925U (fr) * 1987-06-15 1988-12-23
JPH01287697A (ja) * 1988-05-16 1989-11-20 Oki Electric Ind Co Ltd パルス変換回路
JPH02202217A (ja) * 1989-01-31 1990-08-10 Nec Corp クロックデューティ自動調整回路
JPH02294113A (ja) * 1989-05-09 1990-12-05 Canon Inc パルス発生回路
JPH0366847B2 (fr) * 1986-06-07 1991-10-18 Nippon Denki Hoomu Erekutoronikusu Kk
JPH10135795A (ja) * 1996-10-30 1998-05-22 Akira Yokomizo デジタル波形整形回路
JPH10135796A (ja) * 1996-10-30 1998-05-22 Akira Yokomizo 外部同期方法及び外部同期回路
JPH10135793A (ja) * 1996-10-30 1998-05-22 Akira Yokomizo 周波数逓倍回路

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0366847B2 (fr) * 1986-06-07 1991-10-18 Nippon Denki Hoomu Erekutoronikusu Kk
JPS63200925U (fr) * 1987-06-15 1988-12-23
JPH01287697A (ja) * 1988-05-16 1989-11-20 Oki Electric Ind Co Ltd パルス変換回路
JPH02202217A (ja) * 1989-01-31 1990-08-10 Nec Corp クロックデューティ自動調整回路
JPH02294113A (ja) * 1989-05-09 1990-12-05 Canon Inc パルス発生回路
JPH10135795A (ja) * 1996-10-30 1998-05-22 Akira Yokomizo デジタル波形整形回路
JPH10135796A (ja) * 1996-10-30 1998-05-22 Akira Yokomizo 外部同期方法及び外部同期回路
JPH10135793A (ja) * 1996-10-30 1998-05-22 Akira Yokomizo 周波数逓倍回路

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