Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/31051—Planarisation of the insulating layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/31051—Planarisation of the insulating layers
  • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/32115—Planarisation

Definitions

• TITLE DEPOSITING A MATERIAL OF CONTROLLED, VARIABLE THICKNESS ACROSS A
• This invention relates to the field of semiconductor processmg and, more particularly, to an integrated circuit and method of making the same in which a layer of varying thickness is deposited upon a topographical surface of a semiconductor topography to compensate for elevational variations across the surface.
• An integrated circuit consists of electronic devices electrically coupled by conductive trace elements, i.e., interconnect Interconnect are patterned from conductive layers formed above the surface of a semiconductor substrate in which impurity regions have been formed.
• An mtegrated circuit can compnse multiple levels of interconnect spaced from each other by mterlevel dielect ⁇ c layers and electrically linked by contact structures extending through the mterlevel dielect ⁇ c layers. The use of multiple levels of interconnect within an mtegrated circuit mcreases the density of active devices placed upon a smgle monolithic substrate.
• an increase m the number of interconnect levels leads to a corresponding mcrease in the elevational disparity of the resulting surface (l e., an mcrease m the difference between the peaks and valleys of the resultmg upper surface).
• an mcrease m the difference between the peaks and valleys of the resultmg upper surface.
• CVD chemical- vapor deposition
• the dielectric layer climbs to a higher elevation when it crosses over an interconnect line and falls to a lower elevation m between interconnect lmes.
• elevation disparity across the upper surface of an ensumg mtegrated circuit can lead to many problems. Exemplary problems mclude strmgers arising from mcomplete etchmg over severe steps, failure to open vias due to mterlevel dielect ⁇ c thickness disparity, and poor adhesion to underlymg mate ⁇ als.
• Elevation dispa ⁇ ty also causes step coverage problems of, e.g., interconnect placed over an mterlevel dielect ⁇ c peak and valley area as well depth-to-focus problems when patterning, e.g., interconnect upon an mterlevel dielect ⁇ c.
• CMP Chemical-mechanical polishing
• a typical CMP process involves placmg a semiconductor wafer face-down on a polishing pad which is fixedly attached to a rotatable table or platen Elevationally extending portions of the downward-directed wafer surface contact with the rotatmg pad.
• a fluid-based chemical often referred to as a "slurry" is deposited upon the pad possibly through a nozzle such that the slurry becomes disposed at the interface between the pad and the wafer surface.
• the slurry initiates the polishing process by chemically reacting with the surface mate ⁇ al bemg polished.
• the problems identified above are, in large part, addressed by an improved method for substantially plana ⁇ zmg a surface havmg surface dispanty
• the profile of the upper surface of a semiconductor topography is detected m order to quantify the elevational va ⁇ ations across the surface and store the elevational va ⁇ ations in a database
• a deposition tool is then used to deposit a profile layer of varying thickness across the topographical surface, wherem the thickness of the profile layer is controlled as a function of the elevation of the topographical surface, as mdicated by the database
• the thickness of the profile layer is made thicker upon the more recessed regions of the topographical surface than upon the more elevated regions of the topographical surface
• the profile layer compensates for elevational vanations, resultmg m a substantially planar upper surface
• the present planarization method may be used to replace CMP planarization techniques or to compensate for recesses formed in a surface as a result of CMP
• a profile detection tool e g , a stylus profilometer,
• elevational variations across a topographical surface are used to dictate the openmg and closmg of piezo valves disposed within a conduit leadmg to shower head openmgs.
• the piezo valves control the flow of reactant species through the openmgs mto a PECVD chamber in which the semiconductor topography comprising the topographical surface is placed.
• a database created from measurements taken by a profile detection tool of the topographical surface is provided to a control system which regulates the piezo valves A larger quantity of reactant species is allowed to pass from those openmgs positioned directly above the more recessed regions of the topographical surface.
• the upper surface of the resultmg semiconductor topography is thus substantially planar.
• Fig. 1 is a flow chart descnbmg a method for plananzing an upper surface of a semiconductor topography
• Fig. 2 is a partial cross-sectional view of a semiconductor topography showing a recess formed m the upper surface of the semiconductor topography
• Fig. 3 is a side plan view of a stylus profilometer used to detect a profile of the upper surface of the semiconductor topography
• Fig. 4 is a table havmg an exemplary list of locations on the upper surface of the semiconductor topography and the corresponding elevation of the upper surface at each location;
• Fig. 5 is a side plan view of the PECVD tool used to deposit a profile layer upon the upper surface of the semiconductor topography
• Fig. 6 is a plan view of the base of a shower head from which reactant species pass into a chamber of the
• Fig. 7 is a partial cross-sectional view of a semiconductor topography showmg a deposited profile layer of varying thickness arranged upon the upper surface of the semiconductor topography, wherem the surface of the resultmg semiconductor topography is substantially planar While the mvention is susceptible to va ⁇ ous modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herem be described m detail. It should be understood, however, that the drawings and detailed desc ⁇ ption thereto are not mtended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling withm the spirit and scope of the present mvention as defined by the appended claims.
• Fig 1 shows a flowchart descnbmg a process for obtaining a semiconductor topography with a substantially planar upper surface.
• a semiconductor topography is first provided with an upper surface having elevational variations Thereafter, as shown m block 20, a profile of the upper surface of the semiconductor topography is detected usmg a tool that can trace the elevational changes of the upper surface
• a database is then created to quantify these elevational va ⁇ ations across the upper surface of the semiconductor topography as a function of location.
• the created database is then provided to a deposition tool, e g., a PECVD tool
• a deposition tool e g., a PECVD tool
• the deposition tool is programmed to deposit a profile layer upon the upper surface of the semiconductor topography, wherem a thickness of the profile layer is a function of the elevation of the topography. After deposition, an upper surface of the resulting topography is substantially planar.
• FIG. 1 a cross-sectional view of semiconductor topography 100 is shown.
• Upper surface 110 of semiconductor topography 100 is shown to have elevational variations.
• Upper surface 110 is recessed as a result of, e.g., usmg the CMP process to plananze the surface.
• upper surface 110 may also have other types of elevational vanations.
• Fig. 3 depicts a stylus profilometer which may be used to detect the profile (elevational vanations) of upper surface 110 of semiconductor topography 100.
• the stylus profilometer includes a profilometer tip 120 attached to supporting base 130, the supporting base being attached to supporting structure 140.
• Profilometer tip 120 is free to move m the vertical direction, enablmg it to detect elevational changes
• the elevational changes are recorded by electronic control unit 150 which is attached to supporting structure 140.
• Electronic control unit 150 is also connected to positioning unit 160.
• Positioning unit 160 is able to control the motion of stage 170 m the x-y plane.
• Semiconductor topography 100 may be placed upon stage 170, and as positioning unit 160 moves stage 170 m the horizontal plane, profilometer tip 120 detects the elevational variations m the upper surface 110 of topography 100
• the elevational vanations detected by profilometer tip 120 are recorded by electronic control unit 150 as a function of the horizontal position of stage
• stage 170 The location of stage 170 is given m x and y coordmates. It is to be understood that other profile detection tools, e.g., an mterferometer, a scanning capacitance microscope, and a ThermowaveTM microscope, may be used as well
• a table of exemplary data collected by electronic control unit 150 is illustrated
• the elevation (z) detected by profilometer tip 120 is shown m the second column of the table.
• the location of positioning unit 160 corresponding to each vertical position of profilometer tip 120 is recorded by control unit 150.
• a PECVD deposition tool Prior to the deposition of a profile layer across the upper surface of semiconductor topography 100, the topography is positioned withm a reaction chamber 180 Vapor phase compounds that contam the required reactant species to form the desired matenal across topography 100 are passed mto reaction chamber 180 An rf power 190 with a frequency of approximately 40 kHz to 40 MHz is applied to water-cooled rf electrode 200 while electrode 210 is mamtamed at ground The applied rf power establishes a plasma m gas chamber 180 The establishment of a plasma enables the chemical- vapor deposition to be performed at lower than typical deposition temperatures (approximately 200° C to 400° C) During the deposition, heater 220 mamtams reaction chamber 180 and the reactant species at a constant temperature According to one embodiment, a voltage bias film 230 is placed against the backside of semiconductor top
• Fig 6 depicts a plan view of a shower head 270 which may be used for the deposition of a profile layer across a non-planar surface of a semiconductor topography
• shower head 270 may be positioned above the semiconductor topography withm a reaction chamber of a PECVD tool similar to the one shown m Fig 5
• shower head 270 mcludes a plurality of piezo valves 280 through which the gas compnsmg the reactant species may pass into the reaction chamber
• Each of the piezo valves 280 communicates with an electronic control unit 290
• Electronic control unit 290 receives mput from electronic control unit 150 (see Fig 4) that controls the profilometer tool Based on the x, y, and z coordmates of the database stored by electronic control unit 150, electronic control unit 290 determines which piezo valves 280 to open and which to close
• Each piezo valve 280 is positioned at an x and y coordmate corresponding to an x and y coord
• Electronic control unit 290 controls the openmg and closmg of piezo valves 280 by adjustmg the electronic voltage applied to each valve Specifically, control unit 290 controls which valve withm the array of valves is to be opened Also it determines the amount by which a selected valve is opened In order to control the thickness of the profile layer deposited across the semiconductor topography, electronic control unit 290 causes those valves positioned directly above the more recessed regions of the topography to be m the open position for the longest duration of time.
• valves can control localized areas of deposition by virtue of material flowing through those values or absence thereof.
• valves can remam open more so directly above recessed regions of the semiconductor topography to fill those regions A resultmg surface of the profile layer topography can therefore be made substantially planar.
• semiconductor topography 100 is shown with deposited profile layer 300 formed accordmg to either of the previously descnbed embodiments.
• Profile layer 300 has a vanable thickness across the surface 110 of semiconductor topography 100 m which the thickness is thinner over higher elevations of surface
• profile layer 300 therefore compensates for elevational vanations across surface 110 of semiconductor topography 100.
• upper surface 310 of profile layer 300 is substantially planar.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Chemical Vapour Deposition (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)
• Formation Of Insulating Films (AREA)

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• 1998
  • 1998-04-06 US US09/056,024 patent/US6033921A/en not_active Expired - Fee Related
  • 1998-10-19 EP EP98953682A patent/EP1070343A1/en not_active Withdrawn
  • 1998-10-19 WO PCT/US1998/022003 patent/WO1999052133A1/en not_active Ceased
  • 1998-10-19 KR KR1020007011118A patent/KR20010042493A/ko not_active Withdrawn
  • 1998-10-19 JP JP2000542790A patent/JP2002510877A/ja active Pending
• 1999
  • 1999-11-15 US US09/441,222 patent/US6184986B1/en not_active Expired - Lifetime

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