KR20010042493A - 표면 평탄화를 위하여 그 표면 전반에 대한 제어되는 가변두께 물질의 증착 - Google Patents

표면 평탄화를 위하여 그 표면 전반에 대한 제어되는 가변두께 물질의 증착 Download PDF

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Publication number
KR20010042493A
KR20010042493A KR1020007011118A KR20007011118A KR20010042493A KR 20010042493 A KR20010042493 A KR 20010042493A KR 1020007011118 A KR1020007011118 A KR 1020007011118A KR 20007011118 A KR20007011118 A KR 20007011118A KR 20010042493 A KR20010042493 A KR 20010042493A
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South Korea
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semiconductor topography
topography
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database
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KR1020007011118A
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English (en)
Korean (ko)
Inventor
도슨로버트
메이찰스이.
Original Assignee
토토라노 제이. 빈센트
어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Application filed by 토토라노 제이. 빈센트, 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 토토라노 제이. 빈센트
Publication of KR20010042493A publication Critical patent/KR20010042493A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Vapour Deposition (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Formation Of Insulating Films (AREA)
KR1020007011118A 1998-04-06 1998-10-19 표면 평탄화를 위하여 그 표면 전반에 대한 제어되는 가변두께 물질의 증착 Withdrawn KR20010042493A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US9/056,024 1998-04-06
US09/056,024 US6033921A (en) 1998-04-06 1998-04-06 Method for depositing a material of controlled, variable thickness across a surface for planarization of that surface
PCT/US1998/022003 WO1999052133A1 (en) 1998-04-06 1998-10-19 Depositing a material of controlled, variable thickness across a surface for planarization of that surface

Publications (1)

Publication Number Publication Date
KR20010042493A true KR20010042493A (ko) 2001-05-25

Family

ID=22001674

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020007011118A Withdrawn KR20010042493A (ko) 1998-04-06 1998-10-19 표면 평탄화를 위하여 그 표면 전반에 대한 제어되는 가변두께 물질의 증착

Country Status (5)

Country Link
US (2) US6033921A (enExample)
EP (1) EP1070343A1 (enExample)
JP (1) JP2002510877A (enExample)
KR (1) KR20010042493A (enExample)
WO (1) WO1999052133A1 (enExample)

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* Cited by examiner, † Cited by third party
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US6033921A (en) * 1998-04-06 2000-03-07 Advanced Micro Devices, Inc. Method for depositing a material of controlled, variable thickness across a surface for planarization of that surface
US6503767B2 (en) * 2000-12-19 2003-01-07 Speedfam-Ipec Corporation Process for monitoring a process, planarizing a surface, and for quantifying the results of a planarization process
US6996235B2 (en) * 2001-10-08 2006-02-07 Pitney Bowes Inc. Method and system for secure printing of documents via a printer coupled to the internet
JP2007525822A (ja) * 2003-05-30 2007-09-06 アヴィザ テクノロジー インコーポレイテッド ガス分配システム
JP6109224B2 (ja) * 2015-03-30 2017-04-05 株式会社日立国際電気 半導体装置の製造方法、プログラムおよび基板処理装置
JP6133347B2 (ja) * 2015-03-30 2017-05-24 株式会社日立国際電気 半導体装置の製造方法、基板処理システム及びプログラム
JP6072845B2 (ja) * 2015-03-31 2017-02-01 株式会社日立国際電気 半導体装置の製造方法、基板処理システム、基板処理装置及びプログラム
JP6126155B2 (ja) * 2015-03-31 2017-05-10 株式会社日立国際電気 半導体装置の製造方法、プログラムおよび基板処理装置
JP6321579B2 (ja) 2015-06-01 2018-05-09 株式会社日立国際電気 半導体装置の製造方法、基板処理システム、基板処理装置及びプログラム
US20170040233A1 (en) * 2015-08-04 2017-02-09 Hitachi Kokusai Electric Inc. Substrate Processing Apparatus and Substrate Processing System
JP6151745B2 (ja) * 2015-08-04 2017-06-21 株式会社日立国際電気 基板処理装置、基板処理システム、半導体装置の製造方法、プログラム及び記録媒体
JP6153975B2 (ja) * 2015-08-07 2017-06-28 株式会社日立国際電気 半導体装置の製造方法、基板処理システム、プログラム、記録媒体および基板処理装置
JP6549074B2 (ja) 2016-09-28 2019-07-24 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置およびプログラム
JP7540864B2 (ja) 2020-06-15 2024-08-27 東京エレクトロン株式会社 シャワープレート及び成膜装置
CN114075661B (zh) * 2020-08-14 2022-11-18 长鑫存储技术有限公司 半导体沉积方法及半导体沉积系统

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6479399A (en) * 1987-09-22 1989-03-24 Nippon Steel Corp Production of metallic plate having colored pattern
JPH04212414A (ja) * 1990-08-16 1992-08-04 Fuji Electric Co Ltd プラズマ処理装置
EP0582724A1 (de) * 1992-08-04 1994-02-16 Siemens Aktiengesellschaft Verfahren zur lokal und global planarisierenden CVD-Abscheidung von SiO2-Schichten auf strukturierten Siliziumsubstraten
JP3103227B2 (ja) * 1992-12-09 2000-10-30 株式会社日立製作所 半導体装置の製造方法
US5419803A (en) * 1993-11-17 1995-05-30 Hughes Aircraft Company Method of planarizing microstructures
KR100203995B1 (ko) * 1995-02-16 1999-06-15 나가시마 카쭈시게, 노미야마 아키히코 입자충전방법 및 장치
US5665199A (en) * 1995-06-23 1997-09-09 Advanced Micro Devices, Inc. Methodology for developing product-specific interlayer dielectric polish processes
JPH0922795A (ja) * 1995-07-04 1997-01-21 Sony Corp プラズマｃｖｄ装置およびプラズマｃｖｄ方法
KR0165320B1 (ko) * 1995-12-27 1999-02-01 김광호 반도체 산화 공정의 소크타임 설정 방법
JPH09205049A (ja) * 1996-01-23 1997-08-05 Kokusai Electric Co Ltd 成膜装置
US6033921A (en) * 1998-04-06 2000-03-07 Advanced Micro Devices, Inc. Method for depositing a material of controlled, variable thickness across a surface for planarization of that surface

Also Published As

Publication number Publication date
JP2002510877A (ja) 2002-04-09
WO1999052133A1 (en) 1999-10-14
US6184986B1 (en) 2001-02-06
EP1070343A1 (en) 2001-01-24
US6033921A (en) 2000-03-07

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PA0105 International application

Patent event date: 20001006

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid