WO1999017354A1 - Systeme d'identification de dispositifs electroniques defectueux - Google Patents

Systeme d'identification de dispositifs electroniques defectueux Download PDF

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Publication number
WO1999017354A1
WO1999017354A1 PCT/SG1997/000048 SG9700048W WO9917354A1 WO 1999017354 A1 WO1999017354 A1 WO 1999017354A1 SG 9700048 W SG9700048 W SG 9700048W WO 9917354 A1 WO9917354 A1 WO 9917354A1
Authority
WO
WIPO (PCT)
Prior art keywords
defective
contacts
machine
wire
information
Prior art date
Application number
PCT/SG1997/000048
Other languages
English (en)
Inventor
Kaleambur Rajarathinam Vadivazham
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to AU49753/97A priority Critical patent/AU4975397A/en
Priority to KR1020007003253A priority patent/KR20010015630A/ko
Priority to EP97912629A priority patent/EP1029348A1/fr
Priority to JP2000514321A priority patent/JP2001518631A/ja
Priority to PCT/SG1997/000048 priority patent/WO1999017354A1/fr
Publication of WO1999017354A1 publication Critical patent/WO1999017354A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/01—Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a system for identifying defective electronic devices, and in particular, a system to enable the identification of defective electronic devices during manufacture .
  • a silicon wafer having a number of electronic circuits thereon is attached to a plastic adhesive tape and the silicon wafer is cut into individual electronic circuits, each of which is known as a "die" .
  • the dies are held in position with respect to each other by the adhesive tape which is not cut during the silicon wafer cutting process.
  • the dies attached to the adhesive tape then pass to a die attach machine which transfers each die from the adhesive tape to a mounting surface (or stage) on a lead frame.
  • the dies are mounted on the mounting surfaces usually by some form of adhesive, such as an epoxy adhesive.
  • the die attach machine Prior to placing each die on the respective mounting surface, the die attach machine carries out an inspection (known as a pre-bond inspection) which checks that the epoxy has been dispensed correctly onto the stage and also ensures that the lead fingers associated with each stage are not damaged. After each die has been attached, the die attach machine carries out a further inspection (known as a post-bond inspection) to ensure that each die is correctly positioned on the respective stage and that, for example, the die is not too close to an edge of the stage and that the die is mounted squarely on the stage.
  • a pre-bond inspection which checks that the epoxy has been dispensed correctly onto the stage and also ensures that the lead fingers associated with each stage are not damaged.
  • the die attach machine carries out a further inspection (known as a post-bond inspection) to ensure that each die is correctly positioned on the respective stage and that, for example, the die is not too close to an edge of the stage and that the die is mounted squarely on the stage.
  • IQC Integrated Quality Control
  • the lead frame with the dies attached is positioned in a magazine with a number of other lead frames and passed to an oven in which the epoxy adhesive is cured by heating.
  • the magazine then passes to a wire bond machine which bonds wire from the circuit contacts on each die to respective lead finger contacts on the lead frame.
  • VBI Visual Bond Inspection
  • the magazine After wire bonding, the magazine passes to a moulding stage where black resin is moulded around each stage and die on the lead frame .
  • the wire bond machine In the conventional system, if a defect is identified during the die attach process the defect is indicated manually by a marking on the lead frame for visual identification by an operator.
  • the wire bond machine is not aware of the defect and is unable to determine a defective device from the marking on the lead frame. Accordingly, the wire bond machine will try to bond wire to the die and the lead fingers until it determines that it is unable to do so correctly. Only then does the wire bond machine become aware of a defective device and then signals to an operator that there is a problem with a particular die or wire bond process and ask the operator for further instructions. The operator then has to instruct the wire bond machine to skip or reject that particular device. This double detection of defective devices reduces the efficiency of the assembly process and wastes machine time.
  • defects in a device are no longer visible.
  • defective devices have to be manually marked, for example by scoring the resin moulding to indicate that they are defective, prior to singulation of the devices from the lead frames, so that defective devices may be identified and removed after singulation.
  • a method of indicating defective electronic semiconductor devices comprises identifying a defective device and electrically connecting a wire between two contacts on the device to short circuit the two contacts.
  • a system for identifying defective electronic devices comprises an inspection device located at a first location during manufacture of electronic devices, the inspection device determining whether a device is defective, a memory device receiving information relating to a defective device from the inspection device and storing the information, the information being sufficient to identify the defective device at a second location in a subsequent stage of manufacture, and a machine at the second location retrieving the stored information from the memory device to identify a defective device at the second location.
  • An advantage of the invention is that by storing information relating to the defective device and passing the information to a later stage in the assembly process, duplication of identification and documentation of defective devices is reduced and the efficiency of the assembly process is increased.
  • Another advantage of the invention is that it is not necessary to visually mark defective devices, as defective devices can be detected by testing the devices for a short circuit which is a normal part of the testing process .
  • the later stage in the process to which the information is sent is a wire bond process and in response to the information, the wire bond machine electrically connects two respective contacts on the device to short circuit the contacts .
  • the contacts which are electrically connected are two contacts on the lead frame and typically, two lead fingers.
  • the information stored which identifies the defective device includes information relating to the stage number on the lead frame strip on which the defective device is located, information relating to the position of the lead frame in a magazine and information relating to the identity of the magazine in which the lead frame is located.
  • the defective devices are then rejected during the testing stage as any devices which have two contacts short circuited will fail the test stage and be rejected.
  • the contacts short circuited by the wire bond machine are predetermined.
  • Figure 1 is a schematic diagram of an assembly process for electronic semiconductor devices in which the invention is incorporated.
  • Figure 1 shows an assembly process for electronic semiconductor devices from a die attach stage through to moulding.
  • a die attach machine 1 removes individual dies from an adhesive tape on which the silicon wafer is mounted and positions each die on a respective stage on a lead frame .
  • Each lead frame has a number of stages so that a number of dies are mounted on each lead frame.
  • the die attach machine 1 carries out a pre-bonding inspection 2 in which the machine 1 ensures that the adhesive, which is normally an epoxy adhesive, has been correctly applied to the central portion of the respective stage. The machine 1 also ensures that the lead fingers associated with each stage are not broken or otherwise damaged.
  • a defective device signal is sent to a memory device 4 which stores information on defective devices as a "reject map" 10.
  • the die attach machine 1 If the die attach machine 1 detects that the epoxy adhesive has been dispensed properly and that the lead fingers are not damaged, the die attach machine 1 removes a die from the adhesive tape and places the die on the stage on the epoxy adhesive .
  • the die attach machine 1 then carries out a post-bond inspection 3 in which the machine 1 checks that the attached die is not too close to the edge of the stage and that the die is not twisted or skewed on the stage. If the die is not positioned properly, a defective device signal is passed to the memory 4 and the reject map 10 is updated.
  • the lead frame After a die is attached to each stage on the lead frame, the lead frame is inserted into a magazine which has a unique identification code.
  • the identification code of that magazine is stored in the memory 4 and associated in the reject map 10 with each of the defective devices which are located on lead frames that are in that magazine.
  • a number of magazines containing lead frames with dies attached are then passed to a curing oven 5 in which the lead frames and the dies are heated to cure the epoxy adhesive and to properly bond each die to the respective mounting stage.
  • the magazines are passed to wire bond machines 6.
  • wire bond machines 6 Typically one magazine is passed to each wire bond machine 6.
  • Each wire bond machine 6 identifies the magazine it has received and retrieves the reject map 10 containing the defective device information for that magazine from the memory 4.
  • the wire bond machine 6 determines from the reject map 10 whether the device is a defective device. If the device is defective, the wire bond machine bonds the wire between two predetermined lead fingers to short circuit the lead fingers and no further wire bonding is performed on that device.
  • the wire bond machine 6 sends a defective device signal to the memory device 4 to report that the device is defective and the reject map 10 for that magazine is updated.
  • the information that passes to the memory 4 to update the reject map 10 is the location of the defective device on the lead frame, the position of the relevant lead frame in the magazine, and the magazine identification code.
  • the wire bond machine 6 also bonds a wire between the two predetermined lead fingers to short circuit the lead fingers. Typically, the lead fingers between which the wire is bonded are always the same two so that all defective devices have a wire bonded between the same two lead fingers. After the wire bonding process, all the defective device information and the relevant lot or batch identification may be stored in a memory 7.
  • the magazines are passed to a moulding machine which moulds black resin around each device.
  • the devices are then singulated and tested for short circuits at an short open circuit testing machine 9.
  • the short circuit testing machine 9 rejects all devices which contain short circuits and therefore rejects all the defective devices as short circuits in all the defective devices were generated by the wire bond machine 6 bonding wires between the two predetermined lead fingers.
  • the invention has the advantage that by creating a reject map 10 of each magazine containing the relevant positions of each defective device on each lead frame in the magazine, defective chips may be identified by the wire bond machine 6 and indicated appropriately by bonding wires between two lead fingers .

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Système permettant d'identifier des dispositifs électroniques défectueux, qui comporte un dispositif d'inspection (2, 3) situé en un premier emplacement pendant la fabrication desdits dispositifs électroniques. Ledit dispositif d'inspection (2, 3) détermine si un dispositif est défectueux. Une mémoire (4) reçoit du dispositif d'inspection (2, 3) des informations concernant les dispositifs défectueux et stocke ces informations. Les informations reçues par la mémoire sont suffisantes pour identifier le dispositif défectueux en un second emplacement situé à un stade ultérieur de la fabrication. Une machine (6) située sur le second emplacement récupère dans la mémoire (4) les informations stockées (10) pour identifier un dispositif défectueux au niveau du second emplacement.
PCT/SG1997/000048 1997-09-30 1997-09-30 Systeme d'identification de dispositifs electroniques defectueux WO1999017354A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AU49753/97A AU4975397A (en) 1997-09-30 1997-09-30 A system for identifying defective electronic devices
KR1020007003253A KR20010015630A (ko) 1997-09-30 1997-09-30 결함있는 전자 장치 식별 시스템
EP97912629A EP1029348A1 (fr) 1997-09-30 1997-09-30 Systeme d'identification de dispositifs electroniques defectueux
JP2000514321A JP2001518631A (ja) 1997-09-30 1997-09-30 欠陥のある電子装置を識別するシステム
PCT/SG1997/000048 WO1999017354A1 (fr) 1997-09-30 1997-09-30 Systeme d'identification de dispositifs electroniques defectueux

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG1997/000048 WO1999017354A1 (fr) 1997-09-30 1997-09-30 Systeme d'identification de dispositifs electroniques defectueux

Publications (1)

Publication Number Publication Date
WO1999017354A1 true WO1999017354A1 (fr) 1999-04-08

Family

ID=20429570

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SG1997/000048 WO1999017354A1 (fr) 1997-09-30 1997-09-30 Systeme d'identification de dispositifs electroniques defectueux

Country Status (5)

Country Link
EP (1) EP1029348A1 (fr)
JP (1) JP2001518631A (fr)
KR (1) KR20010015630A (fr)
AU (1) AU4975397A (fr)
WO (1) WO1999017354A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4255851A (en) * 1978-12-06 1981-03-17 Western Electric Company, Inc. Method and apparatus for indelibly marking articles during a manufacturing process
US4801869A (en) * 1987-04-27 1989-01-31 International Business Machines Corporation Semiconductor defect monitor for diagnosing processing-induced defects
US5038035A (en) * 1988-08-05 1991-08-06 Mitsubishi Jukogyo Kabushiki Kaisha Automatic structure analyzing/processing apparatus
WO1995016923A1 (fr) * 1993-12-16 1995-06-22 Philips Electronics N.V. Controle separe des courants de repos du trajet de signal et du trajet de polarisation dans un circuit integre
JPH07270335A (ja) * 1994-03-29 1995-10-20 Sekisui Chem Co Ltd 撮像式検査方法および装置
US5504438A (en) * 1991-09-10 1996-04-02 Photon Dynamics, Inc. Testing method for imaging defects in a liquid crystal display substrate
JPH08137093A (ja) * 1994-09-16 1996-05-31 Toshiba Corp 欠陥検査装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4255851A (en) * 1978-12-06 1981-03-17 Western Electric Company, Inc. Method and apparatus for indelibly marking articles during a manufacturing process
US4801869A (en) * 1987-04-27 1989-01-31 International Business Machines Corporation Semiconductor defect monitor for diagnosing processing-induced defects
US5038035A (en) * 1988-08-05 1991-08-06 Mitsubishi Jukogyo Kabushiki Kaisha Automatic structure analyzing/processing apparatus
US5504438A (en) * 1991-09-10 1996-04-02 Photon Dynamics, Inc. Testing method for imaging defects in a liquid crystal display substrate
WO1995016923A1 (fr) * 1993-12-16 1995-06-22 Philips Electronics N.V. Controle separe des courants de repos du trajet de signal et du trajet de polarisation dans un circuit integre
JPH07270335A (ja) * 1994-03-29 1995-10-20 Sekisui Chem Co Ltd 撮像式検査方法および装置
JPH08137093A (ja) * 1994-09-16 1996-05-31 Toshiba Corp 欠陥検査装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DERWENT ABSTRACT, AN 96-037385; & JP 07307371 A (HITACHI) 21 November 1995. *
DERWENT ABSTRACT, AN 97-122393; & JP 09005380 A (TOSHIBA) 10 January 1997. *

Also Published As

Publication number Publication date
JP2001518631A (ja) 2001-10-16
EP1029348A1 (fr) 2000-08-23
KR20010015630A (ko) 2001-02-26
AU4975397A (en) 1999-04-23

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