WO1998059369A1 - Boitier de semi-conducteur et son procede de fabrication - Google Patents
Boitier de semi-conducteur et son procede de fabrication Download PDFInfo
- Publication number
- WO1998059369A1 WO1998059369A1 PCT/JP1998/002757 JP9802757W WO9859369A1 WO 1998059369 A1 WO1998059369 A1 WO 1998059369A1 JP 9802757 W JP9802757 W JP 9802757W WO 9859369 A1 WO9859369 A1 WO 9859369A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor package
- circuit board
- chip
- mentioned
- resin
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 238000000034 method Methods 0.000 title claims description 29
- 239000011347 resin Substances 0.000 claims abstract description 39
- 229920005989 resin Polymers 0.000 claims abstract description 39
- 238000007789 sealing Methods 0.000 claims abstract description 29
- 229910000679 solder Inorganic materials 0.000 claims description 63
- 238000007747 plating Methods 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 11
- 239000000919 ceramic Substances 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 4
- 239000004744 fabric Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 23
- 229910052802 copper Inorganic materials 0.000 description 22
- 239000010949 copper Substances 0.000 description 22
- 230000004907 flux Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 241000287828 Gallus gallus Species 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000881 depressing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Definitions
- the present invention relates to a small-sized semiconductor package and a method for manufacturing the same, and more particularly, to an IC chip-sized semiconductor package in which a circuit board is mounted on an IC chip by flip-chip connection, and a method for manufacturing the same.
- a through hole 2 is formed in a circuit board 1 in which a copper foil 6 is formed on both sides of a resin base 1a.
- a copper plating layer (not shown) is formed on both surfaces of the circuit board 1 by electroless copper plating and electrolytic copper plating.
- the copper plating layer is also formed on the inner wall surface of the through hole.
- the copper plating layers on both sides of the circuit board 1 are laminated with a plating resist (not shown). Further, this mask resist is sequentially exposed and developed to form a pattern mask (not shown). After that, copper plating through this pattern mask The layer is subjected to pattern etching using an etching liquid. By this pattern etching, a plurality of bonding patterns 3 as IC connection electrodes are formed on the upper surface side of the circuit board 1. In addition, the pad electrodes 4 arranged in a matrix are formed on the bottom side of the circuit board 1 by this pattern etching.
- a solder resist process is performed to form a resist film (not shown) on the bottom surface side of the collective circuit board 100.
- This resist film has an opening for exposing the pad electrode 4 which is a solderable region.
- the bottom surface of the circuit board 1 becomes flat. In this way, the circuit board 1 in which a large number of solderable regions of the same shape are arranged in a matrix on the bottom surface is completed (FIG. 4 (a)).
- solder ball 9 is fixed on the pad electrode of the circuit board 1.
- a flux 12 is applied to the solder balls 9 as shown in FIG.
- the solder balls 9 to which the flux 12 has been applied are temporarily fixed on the pad electrodes with the flux 12 ((c) in FIG. 4).
- composition of the solder ball is 60% lead (Pb) and 40% tin (Sn) in terms of% by weight.
- solder having this composition is referred to as “6Z4 solder”.
- solder bumps 7 for flip chip connection are formed on the IC chip 5. Further, a flux 12 is applied to the solder bumps 7 ((d) in FIG. 4).
- the IC chip 5 to which the solder balls 9 are temporarily fixed is mounted on the circuit board 1.
- the solder bumps 7 of the IC chip 5 are positioned on the bonding pads 3 of the circuit board 1.
- the IC chip 5 is temporarily fixed to the circuit board 1 by the flux 12 applied to the solder bumps 7 ((e) in FIG. 4).
- the circuit board 1 and the IC chip 5 are heated in a heating furnace at a temperature of 210 ° C. to 230 ° C. to perform a riff opening.
- the flux 12 applied to the solder ball 9 is melted with the solder ball 9 to form the solder ball electrode 10.
- the solder bump 7 The flux 12 melts with the solder bump 7.
- the IC chip 5 is flip-chip connected to the circuit board 1 via the solder bumps 7 and the bonding pads 3 ((f) in FIG. 4).
- the IC chip 5 is side-molded to protect the IC chip 5 mounted on the circuit board 1.
- the IC chip 5 by exposing the upper surface of the IC chip 5, to allow for proper heat dissipation from the IC chip 5 (of FIG. 4 (g)) c
- the area occupied by the circuit board is made equal to the area occupied by the IC chip, there is a problem that the manufacturing cost for mounting the IC chip on the circuit board is eliminated. Furthermore, if the area occupied by the circuit board is made equal to the area occupied by the IC chip, there is almost no space between the IC chips mounted on the circuit board. As a result, there is a problem that it becomes difficult to inject the sealing resin between the IC chip and the circuit board from a gap between the IC chips.
- a semiconductor package and a method of manufacturing the same according to the present invention are directed to an inexpensive and small-sized semiconductor package excellent in reliability and productivity, and a method of manufacturing the same, in view of the above problems. Disclosure of the invention
- the area occupied by the circuit board is made smaller than the area occupied by the IC chip.
- the size of the semiconductor package is determined by the size of the IC chip.
- the size of the semiconductor package was determined by the size of the circuit board larger than the IC chip. Therefore, according to the present invention, the semiconductor The package can be reduced in size.
- each of the I formed on the wafer As described above, according to the method of manufacturing a semiconductor package according to the present invention, each of the I formed on the wafer. A flip-chip connection is made to each circuit board smaller than the IC chip. At the time of flip-chip connection, the edge of the wafer can be used as a manufacturing margin. Therefore, there is no need to provide a manufacturing allowance on the circuit board side for flip-chip connection.
- the circuit board is smaller than the IC chip, a gap can be provided between the circuit boards mounted on each IC chip of the wafer. As a result, it is possible to easily inject the sealing resin from between the circuit boards to between the Ic chip and the circuit board.
- the yield can be improved. As a result, it is possible to suppress the manufacturing cost of the semiconductor package and contribute to reducing the price.
- the size of the circuit board is smaller than that of the IC chip, the number of circuit boards per unit area that can be obtained from the integrated circuit board can be increased as compared with the conventional case. The result As a result, the manufacturing cost of the semiconductor package can be reduced. As a result, the price of the semiconductor package can be reduced.
- FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor package according to a first embodiment of the present invention.
- FIG. 2 is a fragmentary cross-sectional view for explaining the structure of a circuit board constituting the semiconductor package according to the first embodiment of the present invention.
- FIGS. 3A to 3E are views for explaining a method of manufacturing a semiconductor package according to a second embodiment of the present invention, and FIG. It is a figure for explaining, (b) is a figure for explaining a bonding process, (c) is a figure for explaining a resin sealing process, and (d) is a diagram for explaining.
- FIG. 7 is a diagram for explaining a dicing process, and FIG. 7E is a diagram for explaining a manufactured semiconductor package.
- FIG. 5A is a cross-sectional view for explaining the structure of a semiconductor package according to the third embodiment of the present invention
- FIG. 5B and FIG. FIG. 13 is a cross-sectional view of a principal part for describing a structure of a circuit board configuring a semiconductor package according to a third embodiment of the present invention.
- FIG. 6 is a fragmentary cross-sectional view for explaining the structure of a semiconductor package according to a third embodiment of the present invention.
- FIG. 1 is a cross-sectional view for explaining the structure of the semiconductor package according to the first embodiment.
- a semiconductor package 20 includes an IC chip 5 and a circuit board 1.
- the IC chip 5 and the circuit board 1 are flip-chip connected to each other via solder bumps 7.
- the area occupied by the circuit board 1 is smaller than the area occupied by the IC chip 5.
- FIG. 1 the illustration of the internal structure of the IC chip 5 is partially omitted.
- the size of the semiconductor package because the c determined by the size of connexion of the IC chip 5, greater than the IC chip
- the size of the semiconductor package can be reduced compared to a conventional semiconductor package in which an IC chip is mounted on a circuit board.
- the space between the IC chip 5 and the circuit board 1 is sealed with a sealing resin 8. Further, the outer peripheral side surface of the circuit board 1 is also covered with the sealing resin 8.
- the outer peripheral side of the IC chip smaller than the circuit board was covered with the sealing resin.
- FIG. 2 is a cross-sectional view of a main part of the circuit board 1.
- the circuit board 1 is configured using a resin substrate containing a glass cloth as a base material. Then, by containing the glass cloth, the line width of the circuit pattern of the circuit of the circuit board 1 can be reduced. As a result, the density of the rooster pattern can be increased. In addition, workability can be improved by containing glass cloth.
- the circuit board 1 has a bonding pad 3 for flip-chip connection on one surface. On this bonding pad 3, a solder bump 7 is connected.
- the circuit board 1 has an external connection electrode 10 on the other surface.
- the external connection electrode 10 includes a pad electrode 4 and a solder ball 9 formed thereon as a protruding electrode.
- the semiconductor package is electrically connected to, for example, a mother board (not shown) via the external connection electrode 10.
- the bonding pad 3 and the pad electrode 4 are each formed of a Ni (nickel) + Au (gold) plating layer 2e.
- the circuit board 1 includes a through hole 2 for electrically connecting the bonding pad 3 and the external connection electrode 10.
- a copper plating layer 2a is formed on the inner wall surface of the through hole 2.
- the through hole 2 is filled with a resin 2b. Both ends of the through hole filled with resin 2b are covered with copper plating layer 2c.
- the copper plating layer 2c is electrically connected to the copper plating layer 2a.
- the bonding pad 3 and the pad electrode 4 are formed on the copper plating layer 2c on their respective surfaces. Therefore, the bonding pad 3 and the protruding electrode 10 including the pad electrode 4 and the solder ball 9 are electrically connected.
- filling the through hole 2 with the resin 2b can prevent the solder from flowing into the through hole 2.
- a wiring pattern can be formed on the surface of the circuit board 1 at the position where the through hole 2 is formed. Therefore, the surface of the circuit board 1 can be effectively used.
- the bonding pad 3 and the protruding electrode 10 are connected one to one. Then, as shown in FIG. 1, each protruding electrode 10 is provided on the position where the through hole 2 is formed. In this case, since the through-hole 2 is filled with the resin 2b, it is possible to prevent the protruding electrode 10 from depressing into the through-hole 2. Therefore, the height accuracy of the protruding electrode 10 can be ensured.
- FIG. 3 shows an example in which four semiconductor packages 20 are taken from one wafer for convenience.
- a semiconductor package including an IC chip and a circuit board, which are flip-chip connected to each other, is manufactured through a solder bump forming step, a bonding step, a resin sealing step, and a dicing step sequentially. I do.
- solder bumps 7 are formed on the plurality of IC chips 5 formed on the wafer 11 (FIG. 3 (a)).
- the solder bump 7 is made of 6/4 solder. Further, the solder bumps 7 are formed on pad electrodes (not shown) formed on the surface of the IC chip 5.
- solder bumps 7 for example, a method such as a stud bump method, a ball bump method, and a plating bump method may be used.
- the plated bump method allows the bumps to be formed in a narrow array between the pad electrodes. For this reason, the bump method is particularly effective for miniaturizing IC chips.
- each of the IC chips 5 formed on the wafer 11 is provided with a circuit board 1 occupying a smaller area than the occupied area of the individual IC chip 5, one by one via a solder bump 7.
- flip-chip connection ((b) in Fig. 3).
- the circuit board 1 is mounted on the IC chip 5.
- the solder bumps 7 are positioned on the bonding pads (not shown in FIG. 3) of the circuit board 1 to which the flatness is applied.
- the circuit board 1 is melted by solder reflow and the flux is melted and integrated with the solder pads.
- the non-formed area 5a of the IC chip 5 of the wafer 11 can be used as a manufacturing margin.
- NC number control
- a copper plating layer 2a is formed on both surfaces of the substrate 1a by electroless copper plating and electrolytic copper plating.
- the copper plating layer 2 a is also formed on the inner wall surface of the through hole 2.
- the through holes 2 are filled with the resin 2b.
- a copper plating layer 2c is formed on both ends of the through hole 2 filled with the resin 2b by electroless copper plating and electrolytic copper plating.
- the copper plating layer 2c is electrically connected to the copper plating layer 2a.
- the copper plating layer 2c is laminated with a plating resist (not shown).
- the mask resist is exposed and developed to form a pattern mask (not shown).
- pattern etching using an etchant is performed on the copper plating layer via the pattern mask.
- a plurality of bonding patterns 3 as IC connection electrodes arranged on the upper surface side of the circuit board 1 are patterned.
- the pad electrodes 4 arranged in a matrix shape are patterned on the bottom surface side of the circuit board 1 by this pattern etching.
- a solder resist process is performed to form a resist film 2 d having openings in the regions of the bonding pattern 3 and the pad electrode 4. These openings are arranged in a matrix.
- a bonding pattern 3 and a pad electrode 4 are formed by forming a Ni + Au plating layer 2e in each opening of the resist film 2d. Then, the solder balls 9 are temporarily fixed on the pad electrodes 4 by means of flattening.
- the solder ball 9 is made of 6/4 solder. Therefore, when the flux is melted and the solder bump 7 is fixed in the reflow process, the solder ball 9 is also fixed to the pad electrode 4 to form the protruding electrode 10.
- thermosetting resin is injected from between circuit boards 1 so that IC chips 5 formed on wafer 11 and circuit
- the space between the substrate and the substrate 1 is sealed with a resin. Further, sealing between the adjacent circuit boards 1 is sealed.
- each circuit board 1 is fixed to the wafer 11.
- the wafer 11 is cut into individual IC chips 5 by dicing ((d) in FIG. 3).
- the wafer 11 is fixed to a jig (not shown) by a fixing means such as an adhesive or a double-sided tape.
- cutting is performed along dicing lines (street lines) 17 in the X direction and the Y direction orthogonal to each other by a cutting means such as a dicing saw.
- the sealing resin 8 sealed between the circuit boards 1 is also cut together with the wafer 11. Therefore, the dicing, the cut surface of the sealing resin 8 is formed ⁇
- each IC chip 5 is peeled from the jig using a dissolving solution or the like. In this way, a semiconductor package 20 is obtained ((e) of FIG. 3).
- the semiconductor package 20a of this embodiment is composed of an IC chip 5 and a circuit board 1.
- the IC chip 5 and the circuit board 1 are flip-chip connected to each other via solder bumps 7.
- the occupied area of the circuit board 1 is smaller than the occupied area of the IC chip 5.
- the semiconductor package 20a having such a structure is formed by mounting a circuit board (interposer substrate) 1 on an IC chip 5 on which solder bumps 7 are formed.
- a pad electrode 18 is formed on the surface of the IC chip 5.
- the pad electrodes 18 are formed at a pitch of 1 mm or less and arranged in a grid of 5 rows and 5 columns.
- a solder bump 7 is formed on each pad electrode 18.
- through holes (device holes) 2 are formed in the base material 1a constituting the circuit board 1, as shown in FIG. 5 (b). Through hole 2 is used for laser processing.
- the base material 1a is formed by punching by press working. These through holes 2 are formed at a pitch of 1 mm or less and arranged in a grid of 5 rows and 5 columns, similarly to the pad electrodes 18 on the IC chip 5.
- a bonding pad 3 is formed so as to cover the opening of each through hole 2 on one surface of the substrate 1a.
- the bonding pad 3 is exposed on the bottom surface of the through hole 2.
- a resist film 2d is formed on one surface of the substrate 1a on which the bonding pads 3 are formed.
- the resist film 2 d has an opening on the bonding pad 3. Therefore, when this state is viewed from one surface side of the base material 1a, the bonding pad 3 is exposed at the opening of the resist film 2d.
- a solder paste is printed and melted from the other surface side of the base material 1a to fill the through hole 2 with the solder 19.
- the solder balls 9 are melted and bonded to the solders 19 filled in the through holes 2 to form the external connection electrodes 10.
- the IC chip 5 is flip-chip connected to the circuit board 1 on which the external connection electrodes 10 are formed. In connecting the flip chip, each solder bump 7 of the IC chip 5 is connected to each bonding pad 3 of the circuit board 1. Further, the space between the IC chip 5 and the circuit board 1 is resin-sealed with a sealing schedule 8. Through these steps, the semiconductor package 20a is obtained.
- the semiconductor package 2 0 a, through the external connection electrodes 1 0, are example, mounted on motherboard one board (not shown) c
- the external connection electrode 10 and the bonding pad 3 are connected via the through hole 2 on the circuit board 20a. For this reason, it is not necessary to provide a wire pattern other than the bonding pad 3 on one surface of the circuit board 20a. As a result, the pitch of the bonding pads 3 can be shorter than in the case where a circuit board provided with a wiring pattern is used. As a result, The body package can be reduced in size.
- the pitch of the external connection electrodes 10 can be reduced as compared with the case where a circuit board provided with a dashed line pattern is used.
- the number of the external connection electrodes 10 can be increased while the pitch of the external connection electrodes 10 is set to 1 mm or less. In this regard, if there is a rugged pattern, increasing the number of external connection electrodes increases the area occupied by the wiring patterns, making it difficult to set the pitch of the external connection electrodes to 1 mm or less.
- FIG. 6 is a sectional view of a principal part of a semiconductor package 20b according to the fourth embodiment.
- the same components as those in the fifth embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
- the semiconductor package 20b of this embodiment has a bonding pad on one surface of the substrate la of the circuit board 1 (ie, the surface on the side where the IC chip 5 is flip-chip connected).
- the bad electrode 4 is provided on the other surface of the base material la.
- the pad electrode 4 is provided so as to close the opening of the through hole 2 on the other surface side of the substrate 1a.
- the solder balls 9 are connected to the pad electrodes 4. Therefore, the external connection electrode 10 is constituted by the pad electrode 4 and the solder hole 9.
- the through hole 2 is filled with solder 19 from one surface side of the base material 1a.
- solder 19 and the solder bumps 7 of the IC chip 5 are connected and integrated.
- the semiconductor package and the method of manufacturing the same according to the present invention are suitable as a semiconductor package having excellent reliability and productivity and a method of manufacturing the semiconductor package, which are mounted on a camera-integrated VTR or a small portable device. is there.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98928599A EP0923128B1 (en) | 1997-06-23 | 1998-06-22 | Method of manufacturing a semiconductor package |
DE69840473T DE69840473D1 (de) | 1997-06-23 | 1998-06-22 | Herstellungsverfahren für eine Halbleiterpackung |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9/165847 | 1997-06-23 | ||
JP16584797A JP4159631B2 (ja) | 1997-06-23 | 1997-06-23 | 半導体パッケージの製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998059369A1 true WO1998059369A1 (fr) | 1998-12-30 |
Family
ID=15820138
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1998/002757 WO1998059369A1 (fr) | 1997-06-23 | 1998-06-22 | Boitier de semi-conducteur et son procede de fabrication |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0923128B1 (ja) |
JP (1) | JP4159631B2 (ja) |
KR (1) | KR20000068303A (ja) |
CN (1) | CN1154177C (ja) |
DE (1) | DE69840473D1 (ja) |
WO (1) | WO1998059369A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6507118B1 (en) | 2000-07-14 | 2003-01-14 | 3M Innovative Properties Company | Multi-metal layer circuit |
JP5372346B2 (ja) | 2007-07-18 | 2013-12-18 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法 |
JP5966653B2 (ja) * | 2012-06-20 | 2016-08-10 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
US9219031B2 (en) * | 2013-05-13 | 2015-12-22 | Infineon Technologies Ag | Chip arrangement, and method for forming a chip arrangement |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2725305A1 (fr) | 1994-09-12 | 1996-04-05 | Nec Corp | Ensemble de connexion d'un dispositif electronique avec un substrat |
JPH08306743A (ja) * | 1995-04-27 | 1996-11-22 | Nec Corp | 半導体パッケージ及び半導体装置 |
JPH09260533A (ja) * | 1996-03-19 | 1997-10-03 | Hitachi Ltd | 半導体装置及びその実装構造 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01286430A (ja) * | 1988-05-13 | 1989-11-17 | Matsushita Electric Ind Co Ltd | 半導体チップの実装方法 |
JPH04233749A (ja) * | 1990-08-06 | 1992-08-21 | Motorola Inc | 電気アセンブリ用たわみチップ・キャリア |
KR960015869A (ko) * | 1994-10-03 | 1996-05-22 | 반도체 칩과 일체화된 반도체 패키지 및 그 제조방법 |
-
1997
- 1997-06-23 JP JP16584797A patent/JP4159631B2/ja not_active Expired - Lifetime
-
1998
- 1998-06-22 WO PCT/JP1998/002757 patent/WO1998059369A1/ja not_active Application Discontinuation
- 1998-06-22 EP EP98928599A patent/EP0923128B1/en not_active Expired - Lifetime
- 1998-06-22 DE DE69840473T patent/DE69840473D1/de not_active Expired - Lifetime
- 1998-06-22 CN CNB988007932A patent/CN1154177C/zh not_active Expired - Fee Related
- 1998-06-22 KR KR1019997001453A patent/KR20000068303A/ko not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2725305A1 (fr) | 1994-09-12 | 1996-04-05 | Nec Corp | Ensemble de connexion d'un dispositif electronique avec un substrat |
JPH08306743A (ja) * | 1995-04-27 | 1996-11-22 | Nec Corp | 半導体パッケージ及び半導体装置 |
JPH09260533A (ja) * | 1996-03-19 | 1997-10-03 | Hitachi Ltd | 半導体装置及びその実装構造 |
Non-Patent Citations (2)
Title |
---|
"Proceedings of the surface mount international conference", CHIP SIZE SOLUTIONS: A COMPARISON, 29 August 1995 (1995-08-29), pages 36 - 42 |
See also references of EP0923128A4 * |
Also Published As
Publication number | Publication date |
---|---|
CN1154177C (zh) | 2004-06-16 |
DE69840473D1 (de) | 2009-03-05 |
EP0923128B1 (en) | 2009-01-14 |
JPH1116947A (ja) | 1999-01-22 |
KR20000068303A (ko) | 2000-11-25 |
EP0923128A1 (en) | 1999-06-16 |
JP4159631B2 (ja) | 2008-10-01 |
CN1229525A (zh) | 1999-09-22 |
EP0923128A4 (en) | 2004-07-21 |
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