WO1998015011A1 - Leistungs-mos-bauelement - Google Patents
Leistungs-mos-bauelement Download PDFInfo
- Publication number
- WO1998015011A1 WO1998015011A1 PCT/DE1997/001910 DE9701910W WO9815011A1 WO 1998015011 A1 WO1998015011 A1 WO 1998015011A1 DE 9701910 W DE9701910 W DE 9701910W WO 9815011 A1 WO9815011 A1 WO 9815011A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- columns
- gate
- component according
- doped
- polysilicon
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 239000002800 charge carrier Substances 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 10
- 239000002019 doping agent Substances 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000001020 plasma etching Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Definitions
- the invention relates to a power MOS component having a source, drain, gate and a channel controlled by the gate. Furthermore, the invention relates to a method for producing such a component.
- Such semiconductor components which are used to switch large electrical powers, must insulate high voltages in the open state and, in the closed state, allow the greatest possible current density with a small voltage drop. Furthermore, the control performance should be as small as possible.
- Bipolar transistors are often used to implement such power semiconductors if a high current density and a low series resistance are required.
- Field effect transistors are used in particular when a small control power is required. Field effect transistors are used in a number of different forms as power semiconductors.
- VMOS power semiconductors for example, V-shaped trenches with (111) oriented crystal surfaces are exposed by anisotropic etching with KOH. A gate oxide is grown on this and a control gate is applied.
- DMOS transistors a current from the source is laterally under a control gate and then vertical to the drain, which is from
- Substrate is formed, led.
- the control gate is therefore implemented on the semiconductor surface of an n-doped wafer.
- the local p-well of the MOS transistor is formed by deep boron doping at the source.
- the invention is based on the objective of creating a component of the type mentioned at the outset which has a high insulation strength, in particular due to the avoidance of field peaks. Furthermore, the invention has for its object to provide a method for producing such a component.
- the columns and the entire component are preferably manufactured using silicon technology, the cross section of the columns being approximately 0.2 ⁇ m in one direction in order to achieve complete depletion.
- the columns are essentially square in cross section.
- a wall-shaped formation is also possible, as long as the "wall thickness" is so thin is that complete depletion is reached.
- the columns can be arranged periodically on a surface, so that a true symmetrical three-dimensional structure is made possible. This also enables a full-surface, self-positioned and therefore low-impedance source contact.
- the columns are preferably about one micron high.
- the columns are advantageously arranged very close to one another so that a very high current density can be achieved.
- the distance between the columns can be reduced to the distance that can be achieved in terms of process technology. This is usually the fineness of structure F.
- the width of the columns is also approximately 1F, but can be further reduced using additional spacer techniques.
- the gate consists of polysilicon arranged between the columns, as a result of which a low gate resistance is achieved.
- the polysilicon of the gate is preferably doped in a p-conducting manner, so that the work function of the gate electrode ensures a sufficiently high threshold voltage even with completely depleted columns.
- a p-doped layer is produced on a heavily n-doped semiconductor substrate, which forms a drain, and a hard mask is applied to the p-doped layer and structured, an isotropic etching for production performed by columns in the p-doped layer, which oxidizes the columns and a structure produced in the area of the etching to produce a gate oxide, the structure formed by the etching is filled with polysilicon and etched back isotropically, so that the columns are exposed in an upper area the upper area is covered by a nitride spacer, the polysilicon is oxidized or a planarizing oxide is applied, the nitride is removed and in the upper area Region of the column produces an n-doped source region by the ⁇ plantation.
- FIG. 1 to 7 different stages of the manufacturing process according to the invention
- FIG. 8 shows a two-dimensional dopant distribution along the axis of symmetry through the silicon column
- FIG. 9 shows a dopant profile along the axis of symmetry through the silicon column
- FIG. 10 shows a potential distribution at a 10 V drain voltage
- FIG. 11 shows an enlarged section from FIG. 10
- Figure 12 shows a potential distribution at 50V drain voltage
- Figure 13 is a reverse current characteristic.
- a lightly n-doped layer 2 of a few ⁇ m thickness is epitaxially grown on a heavily n-doped semiconductor wafer, which is referred to below as substrate 1.
- the epitaxial layer is then redoped in the area of the vertical MOS transistors to be formed later by implantation.
- the epitaxial layer can also be doped accordingly. This state of the process is shown in FIG. represents, the arrows 3 in the upper region indicate the channel implantation.
- Nitride is applied to the epitaxial layer 2 using a CVD (Chemical Vapor Deposition) process to form a hard mask and structured using a photo technique or spacer technique.
- CVD Chemical Vapor Deposition
- a mask is first applied and the nitride outside the mask is removed using a RIE (reactive ion etching) technique.
- the mask material is then removed, so that only the nitride mask designated by 4 in FIG. 2 remains.
- the nitride mask 4 is used to produce columns in the epitaxial layer 2.
- the lateral dimensions of this nitride mask 4 are so small in at least one direction that the silicon columns 5 structured with them are completely depleted.
- FIG. 3 with this nitride mask 4 the exposed epitaxial layer is etched approximately one ⁇ m by an isotropic RIE etching.
- a gate oxide 6 is now produced on the entire structure, with the exception of the top surfaces of the silicon columns 5.
- Polysilicon is deposited thereon to form a gate 7, so that the spaces between the silicon columns 5 are completely filled.
- the thickness of the gate oxide 6 must be matched to the maximum control voltage at the gate 7.
- the polysilicon is deposited using a CVD technique and doped with p-type boron.
- the polysilicon is etched back isotropically by reactive ion etching (RIE) to such an extent that the upper region of the silicon column 5 is exposed. This process state is shown in FIG. 4.
- nitride spacer 8 which is produced by chemical deposition from the vacuum (Chemical Vapor Deposition) nitride is deposited and the nitride spacers 8 are generated by reactive ion etching. These nitride spacers 8 are shown in FIG. 5.
- the polysilicon which forms the gate 7 is oxidized to such an extent that sufficient insulation for the source metallization is ensured.
- This oxide layer is designated 9.
- a planarizing oxide e.g. BPSG, i.e. boron phosphor silicate glass
- boron phosphor silicate glass can be applied and etched back.
- the nitride on the tips of the silicon columns 5 is removed and these areas are either n-conductively doped with arsenic with sufficiently high energy or laterally at an oblique angle.
- the tips of the silicon columns 5 thus form a source region.
- a metal layer 10 is then applied, which is designed over the entire surface and thus ensures a low-ohmic connection and good heat dissipation.
- the substrate 1 forms the drain
- the gate 7 is formed by the polysilicon, which is arranged around the silicon columns 5, which represent the channel
- the source regions are formed by the tips of the silicon column and the metal layer 10.
- FIG. 8 shows a section of the three-dimensional column MOS transistor. A distance in ⁇ m is indicated on the y-axis, with the 0 point placed at the top of the column and the total height corresponding to a distance of 4 ⁇ m. The x-axis also shows a distance in ⁇ m on the same scale. The distance from 0 to 4 ⁇ is plotted on the x-axis in FIG. 9, the O point being at the tip of the silicon columns in the source region. The dopant concentration per cm 3 is plotted logarithmically on the y axis.
- the column tip which on the one hand has been doped by implantation, again has a dopant concentration that is an order of magnitude smaller. Due to the small lateral dimensions, this area is also completely impoverished. Due to the arsenic implantation in the tip of the column, a high dopant concentration is present in the uppermost column area, whereby the source area is formed.
- FIG. 10 and 11 potential distributions are plotted at a substrate voltage of 10V.
- FIG. 11 shows an enlargement of the upper area of FIG. 10.
- the depletion zone marked 11 is located in the lower column area.
- the p + doped gate meets the p-well / channel area.
- Within the silicon column 5 and at the bottom edge of the gate only voltages occur that are less than approximately IV. As a result, no field peaks occur, which creates problems in other power MOS technologies.
- FIG. 12 Similar to FIG. 10, a potential distribution is plotted in FIG. 12, but with a substrate voltage of 50V.
- a blocking characteristic curve is shown in FIG. 13, the substrate voltage in volts being plotted on the x axis and the substrate current is plotted logarithmically in ⁇ A on the y-axis. This means that up to 50V problem-free locking behavior can be achieved.
- the extent of the potential lines into the highly doped substrate can be seen from FIGS. 10 and 12.
- the maximum reverse voltage depends on the thickness of the n-doped epitaxial layer 2 and must be adapted to the requirements.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10516099A JP2001501372A (ja) | 1996-09-30 | 1997-09-01 | パワーmos―デバイス |
EP97941862A EP0931354A1 (de) | 1996-09-30 | 1997-09-01 | Leistungs-mos-bauelement |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19640308A DE19640308A1 (de) | 1996-09-30 | 1996-09-30 | Leistungs-MOS-Bauelement |
DE19640308.1 | 1996-09-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998015011A1 true WO1998015011A1 (de) | 1998-04-09 |
Family
ID=7807451
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1997/001910 WO1998015011A1 (de) | 1996-09-30 | 1997-09-01 | Leistungs-mos-bauelement |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0931354A1 (de) |
JP (1) | JP2001501372A (de) |
KR (1) | KR20000048749A (de) |
DE (1) | DE19640308A1 (de) |
WO (1) | WO1998015011A1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3744513B2 (ja) * | 2003-05-30 | 2006-02-15 | トヨタ自動車株式会社 | ダイオード |
GB0324313D0 (en) * | 2003-10-17 | 2003-11-19 | Koninkl Philips Electronics Nv | Trench insulated gate field effect transistor |
JP2007043123A (ja) * | 2005-07-01 | 2007-02-15 | Toshiba Corp | 半導体装置 |
JP2008066708A (ja) * | 2006-08-09 | 2008-03-21 | Toshiba Corp | 半導体装置 |
KR101480077B1 (ko) * | 2013-06-26 | 2015-01-09 | 경북대학교 산학협력단 | 반도체 소자 및 그의 제조방법 |
GB2572442A (en) * | 2018-03-29 | 2019-10-02 | Cambridge Entpr Ltd | Power semiconductor device with a double gate structure |
JP2020126932A (ja) * | 2019-02-05 | 2020-08-20 | トヨタ自動車株式会社 | トレンチゲート型半導体装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0339963A2 (de) * | 1988-04-27 | 1989-11-02 | General Electric Company | Synchroner Gleichrichter |
JPH05198817A (ja) * | 1991-08-28 | 1993-08-06 | Sharp Corp | 半導体装置の構造および製造方法 |
US5323040A (en) * | 1993-09-27 | 1994-06-21 | North Carolina State University At Raleigh | Silicon carbide field effect device |
US5430315A (en) * | 1993-07-22 | 1995-07-04 | Rumennik; Vladimir | Bi-directional power trench MOS field effect transistor having low on-state resistance and low leakage current |
-
1996
- 1996-09-30 DE DE19640308A patent/DE19640308A1/de not_active Withdrawn
-
1997
- 1997-09-01 JP JP10516099A patent/JP2001501372A/ja active Pending
- 1997-09-01 WO PCT/DE1997/001910 patent/WO1998015011A1/de not_active Application Discontinuation
- 1997-09-01 KR KR1019990702734A patent/KR20000048749A/ko not_active Application Discontinuation
- 1997-09-01 EP EP97941862A patent/EP0931354A1/de not_active Ceased
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0339963A2 (de) * | 1988-04-27 | 1989-11-02 | General Electric Company | Synchroner Gleichrichter |
JPH05198817A (ja) * | 1991-08-28 | 1993-08-06 | Sharp Corp | 半導体装置の構造および製造方法 |
US5430315A (en) * | 1993-07-22 | 1995-07-04 | Rumennik; Vladimir | Bi-directional power trench MOS field effect transistor having low on-state resistance and low leakage current |
US5323040A (en) * | 1993-09-27 | 1994-06-21 | North Carolina State University At Raleigh | Silicon carbide field effect device |
Non-Patent Citations (2)
Title |
---|
BOARD K ET AL: "NEW LATCH-UP-FREE IGBT WITH LOW IN-RESISTANCE", 2 September 1993, ELECTRONICS LETTERS, VOL. 29, NR. 18, PAGE(S) 1664 - 1666, XP000395219 * |
PATENT ABSTRACTS OF JAPAN vol. 017, no. 629 (E - 1462) 19 November 1993 (1993-11-19) * |
Also Published As
Publication number | Publication date |
---|---|
EP0931354A1 (de) | 1999-07-28 |
JP2001501372A (ja) | 2001-01-30 |
KR20000048749A (ko) | 2000-07-25 |
DE19640308A1 (de) | 1998-04-02 |
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