WO1997010602A1 - Refresh strategy for drams - Google Patents
Refresh strategy for drams Download PDFInfo
- Publication number
- WO1997010602A1 WO1997010602A1 PCT/US1996/010855 US9610855W WO9710602A1 WO 1997010602 A1 WO1997010602 A1 WO 1997010602A1 US 9610855 W US9610855 W US 9610855W WO 9710602 A1 WO9710602 A1 WO 9710602A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- refresh
- memory
- memory bank
- banks
- initiating
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 37
- 238000001914 filtration Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 27
- 230000015654 memory Effects 0.000 claims description 82
- 230000000977 initiatory effect Effects 0.000 claims description 18
- 238000011084 recovery Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 101100247316 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) ras-1 gene Proteins 0.000 description 1
- 101100247323 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) ras-2 gene Proteins 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Definitions
- the present invention relates to a method of refreshing memory cells within a dynamic random access memory (DRAM), and in particular, to a method which reduces the refresh noise on the drain voltage of a DRAM using CMOS.
- DRAM dynamic random access memory
- dynamic random access memories require periodic refreshing of the memory cells within the DRAM so that the data stored within each memory cell does not corrupt or decay over time.
- refreshing is an essential element of memory storage for volatile memories.
- a refresh may be a CAS (column address select) before RAS (row address select) refresh, or a RAS-only refresh.
- a CAS before RAS refresh involves asserting the CAS signal before the RAS signal is asserted to indicate that the next cycle is a refresh cycle.
- an internal address counter in the memory supplies the row address of the next row to be refreshed.
- a RAS-only refresh operates in a similar manner to refresh selected rows of memory; however, the address of the row to be refreshed is instead supplied by an external refresh circuit.
- DRAM or other DRAMs supplied by the same voltage. This is particularly true in DRAMs which employ CMOS technology, since the internal circuitry of such DRAMS is particularly susceptible to sudden voltage drops or noise.
- a method for refreshing volatile memory banks which share a common filtering capacitor used to filter out voltage drops on a voltage supply line comprises the steps of: initiating a refresh of a first memory bank which shares the filtering capacitor in common with a second memory bank; initiating a refresh of a third memory bank which does not share the capacitor with the first and second memory banks after initiating the refresh of the first memory bank; and refreshing the second memory bank after initiating the refresh of the third memory bank.
- the first, second and third memory banks are CMOS memory banks.
- the method includes the step of initiating a refresh of a fourth memory bank subsequent to initiating the refresh of the second memory bank, wherein the fourth memory bank and the third memory bank share another filtering capacitance.
- the present invention is a method of reducing supply voltage drops which occur during refreshes to memory banks sharing a common capacitor, wherein a supply voltage drop is observed at the memory banks each time a refresh occurs.
- the time between refresh cycles is such that immediately successive refreshes to the first and second memory banks would result in a larger supply voltage drop at the first and second memory banks than would a single refresh to either one or the other of the first and second memory banks.
- the method comprises the steps of: initiating a refresh to a first memory bank which shares the capacitor in common with a second memory bank; and initiating a refresh to the second memory bank after a sufficient number of refresh cycles so that the refresh to the second memory bank does not result in a larger supply voltage drop at the first and second memory banks than would a solitary refresh to either one or the other of the first and second memory banks.
- Figure 1 is schematic block diagram which illustrates two pair of memory banks which each share a filtering capacitor.
- Figure 2 is a timing diagram which illustrates the order of refresh accesses to each of the memory banks as performed in accordance with the method of the prior art.
- Figure 3 is a timing diagram which illustrates the order of refresh accesses to the memory banks of Figure 1 in accordance with the method of the present invention.
- Figures 4A through 4C are signal diagrams which illustrate the voltage drop which occurs during a refresh for the case where (A) a staggered method of the prior art is used to access adjacent memory banks where no filtering capacitor is used; (B) the method of the prior art is used to refresh adjacent memory banks sharing the same filtering capacitors; and (C) the method of the present invention is used to access adjacent memory banks at spaced intervals where the filtering capacitor is shared between the memory banks.
- FIG. 1 is a simplified schematic block diagram which illustrates a plurality of dynamic random accessory memory (DRAM) banks 100 in connection with a voltage supply line 110.
- DRAM dynamic random accessory memory
- a first DRAM bank 120 and a second DRAM bank 130 share a filtering capacitor bank 140.
- DIMM dual in-line memory module
- the capacitor bank 140 may comprise a plurality of capacitors shared by each of the DRAM elements within the DRAM banks 120, 130.
- a third DRAM bank 150 and a fourth DRAM bank 160 share a capacitor bank 170.
- refreshes of the memory cells within each of the DRAM banks 120, 130, 150 and 160 are performed in a predetermined order so as to reduce the instantaneous current drain via the line 110.
- the voltage supply line 110 includes some impedance so that when a sudden current draw occurs at some point along the line 110, it is possible that a significant voltage drop will be observed at that location of the line 110.
- the filtering capacitors 140, 170 are included at a number of locations along the voltage source line 110 to alleviate the effects of such a voltage draw.
- the refresh accesses which are often responsible for sudden current draws on the line 110 are staggered to reduce the total current draw at any given place along the line 110.
- Figure 4A shows the voltage drop which would be observed along the line 10 at the DRAM banks 120, 130 if the RAS 2 signal is asserted immediately after the RAS 1 signal (as shown in Figure 2), while no filtering capacitor 140 is present.
- Figure 4A illustrates the close proximity of the voltage drops observed at the voltage inputs to the memory banks 120, 130 when these adjacent memory banks are refreshed in consecutive clock cycles.
- the voltage drop observed is represented as shown in Figure 4B.
- the voltage drop observed at the voltage supply inputs to the DRAM banks 120, 130 is not as severe as the voltage drop which would be observed if the capacitor 140 were not present at the first voltage drop, when the second voltage drop occurs while the voltage on the line 1 10 near the DRAM banks 120, 130 has not yet recovered to its original value, a large drop is observed upon the assertion of the second row address strobe signal.
- the method of the prior art results in a significant voltage drop to the voltage supply inputs of adjacent DRAM banks if the refreshes occur in rapid succession so that the filtering capacitor 140 does not have time to recover from the original voltage drop.
- This problem is further exacerbated if the DRAM banks 120, 130 employ CMOS technology, because CMOS technology is particularly susceptible to noise in the presence of such voltage drops.
- FIG. 3 an improved method of accessing DRAM banks during refreshes is illustrated in Figure 3.
- the sequence of DRAM refreshes is altered so that DRAM banks sharing the same filtering capacitors are not accessed in consecutive clock cycles. That is, as shown in Figure 3, the row address strobe used to refresh the second DRAM bank 130 is asserted, followed by the row address strobe signal used to refresh the fourth DRAM bank 160, followed by the row address strobe signal used to refresh the first DRAM bank 120, and, finally, the row address strobe signal used to refresh the third DRAM bank 150 is asserted.
- the row address strobe signal used to refresh the third DRAM bank 150 is asserted.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51068697A JP4166274B2 (ja) | 1995-09-14 | 1996-06-27 | Dramリフレッシュ方法 |
AU63934/96A AU6393496A (en) | 1995-09-14 | 1996-06-27 | Refresh strategy for drams |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/527,950 US5654929A (en) | 1995-09-14 | 1995-09-14 | Refresh strategy for DRAMs |
US08/527,950 | 1995-09-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997010602A1 true WO1997010602A1 (en) | 1997-03-20 |
Family
ID=24103635
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/010855 WO1997010602A1 (en) | 1995-09-14 | 1996-06-27 | Refresh strategy for drams |
PCT/US1996/010854 WO1997010601A1 (en) | 1995-09-14 | 1996-06-27 | Refresh strategy for drams |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/010854 WO1997010601A1 (en) | 1995-09-14 | 1996-06-27 | Refresh strategy for drams |
Country Status (12)
Country | Link |
---|---|
US (1) | US5654929A (forum.php) |
EP (1) | EP0792506B1 (forum.php) |
JP (1) | JP4166274B2 (forum.php) |
KR (1) | KR100248259B1 (forum.php) |
CN (1) | CN1130730C (forum.php) |
AU (1) | AU6393496A (forum.php) |
DE (1) | DE69621419T2 (forum.php) |
FI (1) | FI113572B (forum.php) |
IN (1) | IN192635B (forum.php) |
RU (1) | RU2163035C2 (forum.php) |
TW (1) | TW303469B (forum.php) |
WO (2) | WO1997010602A1 (forum.php) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6610493B1 (en) | 1993-06-17 | 2003-08-26 | Brigham And Women's Hospital | Screening compounds for the ability to alter the production of amyloid-β peptide |
US5841686A (en) * | 1996-11-22 | 1998-11-24 | Ma Laboratories, Inc. | Dual-bank memory module with shared capacitors and R-C elements integrated into the module substrate |
KR100243335B1 (ko) * | 1996-12-31 | 2000-02-01 | 김영환 | 독립적인 리프레쉬 수단을 가지는 데이지 체인 구조의 반도체 장치 |
DE19855445C1 (de) * | 1998-12-01 | 2000-02-24 | Siemens Ag | Vorrichtung zur Verringerung der elektromagnetischen Emission bei integrierten Schaltungen mit Treiberstufen |
JP4270707B2 (ja) * | 1999-04-09 | 2009-06-03 | 株式会社東芝 | ダイナミック型半導体記憶装置 |
US7124285B2 (en) * | 2001-03-29 | 2006-10-17 | Intel Corporation | Peak power reduction when updating future file |
US6532175B1 (en) * | 2002-01-16 | 2003-03-11 | Advanced Micro Devices, In. | Method and apparatus for soft program verification in a memory device |
CN101042933B (zh) * | 2007-04-12 | 2010-05-19 | 复旦大学 | 非挥发sram单元、阵列及其操作方法和应用 |
CN101504865B (zh) * | 2009-03-06 | 2011-06-22 | 成都市华为赛门铁克科技有限公司 | 存储系统的数据处理方法及存储设备 |
JP6314673B2 (ja) * | 2014-06-11 | 2018-04-25 | 富士電機株式会社 | 半導体装置 |
KR20160013624A (ko) * | 2014-07-28 | 2016-02-05 | 에스케이하이닉스 주식회사 | 리프레쉬 회로 |
US10490251B2 (en) | 2017-01-30 | 2019-11-26 | Micron Technology, Inc. | Apparatuses and methods for distributing row hammer refresh events across a memory device |
US11200944B2 (en) | 2017-12-21 | 2021-12-14 | SK Hynix Inc. | Semiconductor memory apparatus operating in a refresh mode and method for performing the same |
KR20190075341A (ko) | 2017-12-21 | 2019-07-01 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
CN112106138B (zh) | 2018-05-24 | 2024-02-27 | 美光科技公司 | 用于行锤击刷新采样的纯时间自适应采样的设备和方法 |
US10573370B2 (en) | 2018-07-02 | 2020-02-25 | Micron Technology, Inc. | Apparatus and methods for triggering row hammer address sampling |
US10685696B2 (en) | 2018-10-31 | 2020-06-16 | Micron Technology, Inc. | Apparatuses and methods for access based refresh timing |
WO2020117686A1 (en) | 2018-12-03 | 2020-06-11 | Micron Technology, Inc. | Semiconductor device performing row hammer refresh operation |
CN117198356A (zh) | 2018-12-21 | 2023-12-08 | 美光科技公司 | 用于目标刷新操作的时序交错的设备和方法 |
US10957377B2 (en) | 2018-12-26 | 2021-03-23 | Micron Technology, Inc. | Apparatuses and methods for distributed targeted refresh operations |
US11615831B2 (en) * | 2019-02-26 | 2023-03-28 | Micron Technology, Inc. | Apparatuses and methods for memory mat refresh sequencing |
US11227649B2 (en) | 2019-04-04 | 2022-01-18 | Micron Technology, Inc. | Apparatuses and methods for staggered timing of targeted refresh operations |
US11069393B2 (en) | 2019-06-04 | 2021-07-20 | Micron Technology, Inc. | Apparatuses and methods for controlling steal rates |
US10978132B2 (en) | 2019-06-05 | 2021-04-13 | Micron Technology, Inc. | Apparatuses and methods for staggered timing of skipped refresh operations |
US11302374B2 (en) | 2019-08-23 | 2022-04-12 | Micron Technology, Inc. | Apparatuses and methods for dynamic refresh allocation |
US11302377B2 (en) | 2019-10-16 | 2022-04-12 | Micron Technology, Inc. | Apparatuses and methods for dynamic targeted refresh steals |
US11309010B2 (en) | 2020-08-14 | 2022-04-19 | Micron Technology, Inc. | Apparatuses, systems, and methods for memory directed access pause |
US11380382B2 (en) | 2020-08-19 | 2022-07-05 | Micron Technology, Inc. | Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit |
US11348631B2 (en) | 2020-08-19 | 2022-05-31 | Micron Technology, Inc. | Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed |
US11557331B2 (en) | 2020-09-23 | 2023-01-17 | Micron Technology, Inc. | Apparatuses and methods for controlling refresh operations |
US11222686B1 (en) | 2020-11-12 | 2022-01-11 | Micron Technology, Inc. | Apparatuses and methods for controlling refresh timing |
US11264079B1 (en) | 2020-12-18 | 2022-03-01 | Micron Technology, Inc. | Apparatuses and methods for row hammer based cache lockdown |
US12112787B2 (en) | 2022-04-28 | 2024-10-08 | Micron Technology, Inc. | Apparatuses and methods for access based targeted refresh operations |
US12125514B2 (en) | 2022-04-28 | 2024-10-22 | Micron Technology, Inc. | Apparatuses and methods for access based refresh operations |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5500831A (en) * | 1994-12-01 | 1996-03-19 | Advanced Peripherals Labs, Inc. | RAS encoded generator for a memory bank |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US4887240A (en) * | 1987-12-15 | 1989-12-12 | National Semiconductor Corporation | Staggered refresh for dram array |
US5113372A (en) * | 1990-06-06 | 1992-05-12 | Micron Technology, Inc. | Actively controlled transient reducing current supply and regulation circuits for random access memory integrated circuits |
JPH06338187A (ja) * | 1993-05-27 | 1994-12-06 | Melco:Kk | Dramを用いたメモリ装置 |
-
1995
- 1995-09-14 US US08/527,950 patent/US5654929A/en not_active Expired - Lifetime
-
1996
- 1996-06-27 DE DE69621419T patent/DE69621419T2/de not_active Expired - Lifetime
- 1996-06-27 WO PCT/US1996/010855 patent/WO1997010602A1/en active IP Right Grant
- 1996-06-27 RU RU97110100/09A patent/RU2163035C2/ru not_active IP Right Cessation
- 1996-06-27 AU AU63934/96A patent/AU6393496A/en not_active Abandoned
- 1996-06-27 WO PCT/US1996/010854 patent/WO1997010601A1/en active IP Right Grant
- 1996-06-27 EP EP96922577A patent/EP0792506B1/en not_active Expired - Lifetime
- 1996-06-27 KR KR1019970703236A patent/KR100248259B1/ko not_active Expired - Fee Related
- 1996-06-27 JP JP51068697A patent/JP4166274B2/ja not_active Expired - Fee Related
- 1996-06-27 CN CN96191400A patent/CN1130730C/zh not_active Expired - Lifetime
- 1996-07-03 IN IN1173MA1996 patent/IN192635B/en unknown
- 1996-07-20 TW TW085108858A patent/TW303469B/zh not_active IP Right Cessation
-
1997
- 1997-05-14 FI FI972050A patent/FI113572B/fi not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5500831A (en) * | 1994-12-01 | 1996-03-19 | Advanced Peripherals Labs, Inc. | RAS encoded generator for a memory bank |
Also Published As
Publication number | Publication date |
---|---|
WO1997010601A1 (en) | 1997-03-20 |
KR970707554A (ko) | 1997-12-01 |
FI113572B (fi) | 2004-05-14 |
KR100248259B1 (ko) | 2000-03-15 |
EP0792506A1 (en) | 1997-09-03 |
EP0792506A4 (en) | 1998-08-19 |
FI972050L (fi) | 1997-05-14 |
AU6393496A (en) | 1997-04-01 |
IN192635B (forum.php) | 2004-05-08 |
US5654929A (en) | 1997-08-05 |
TW303469B (forum.php) | 1997-04-21 |
JP4166274B2 (ja) | 2008-10-15 |
CN1130730C (zh) | 2003-12-10 |
DE69621419D1 (de) | 2002-07-04 |
RU2163035C2 (ru) | 2001-02-10 |
JPH10509269A (ja) | 1998-09-08 |
EP0792506B1 (en) | 2002-05-29 |
CN1169205A (zh) | 1997-12-31 |
FI972050A0 (fi) | 1997-05-14 |
DE69621419T2 (de) | 2003-01-16 |
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