Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

• EEPROM electrically writable and electrically erasable read-only memory cells in silicon technology
• these memory cells are usually implemented by a MOS transistor, which has a first dielectric, a floating gate, a second dielectric and a control gate on the channel region. If a charge is stored on the floating gate, this influences the threshold voltage of the MOS transistor.
• the state “charge on the floating gate” is assigned a first logic value
• the state “no charge on the floating gate” is assigned a second logic value.
• the information is written into the memory cells via a Fowler-Nordheim tunnel current or by "hot electron” current, through which electrons are injected onto the floating gate.
• the information is deleted by a
• Tunnel current through the first dielectric At least eight EEPROM transistors are connected in series in a NAND arrangement.
• the MOS transistors are designed as planar MOS transistors and are arranged in a planar cell architecture.
• the minimum area requirement of a memory cell is 4F 2 , where F is the smallest structure size that can be produced in the respective technology.
• Such EEPROM arrangements are currently available for data volumes of up to 32 Mbit.
• JP-OS 3-1574 an electrically writable and erasable read-only memory cell arrangement has been proposed which comprises vertical MOS transistors with a floating gate and control gate as memory cells for a main area of a semiconductor substrate. Strip-shaped trenches which run essentially parallel are provided in the substrate. The vertical MOS transistors are arranged on the flanks of the trenches.
• the memory cells are each arranged on opposite flanks of the trenches.
• Strip-shaped, doped regions which encompass the source and drain regions of the MOS transistors, run on the trench bottom and on the main surface between adjacent trenches. After the trenches have been formed, these stripe-shaped doped regions are produced by masked implantations. Because of the unavoidable 'Justtechnikenautechnik the use of steps Masken ⁇ the achievable packing density in this Spei ⁇ cherzellenan let limited.
• DRAM dynamic memory cell arrangements
• magnetic data carriers are based on mechanical systems with rotating storage media.
• the invention is based on the problem of specifying a method for producing a read-only memory cell arrangement, which can be produced with a smaller space requirement per memory cell.
• the electrically writable and erasable read-only memory cell arrangement produced by the method according to the invention is implemented in a semiconductor substrate, preferably made of monocrystalline silicon or in a silicon layer of an SOI substrate.
• a cell array with memory cells is provided on a main surface of the semiconductor substrate.
• Each memory cell comprises a MOS transistor which is vertical to the main surface and which, in addition to the source / drain region and a channel region arranged between them, comprises a first dielectric, a floating gate, a second dielectric and a control gate.
• a plurality of strip-shaped trenches running essentially parallel are provided in the cell array.
• the vertical MOS transistors are arranged on the flanks of the trenches.
• the memory cells are arranged on opposite flanks of the trenches.
• Strip-shaped, doped areas run on the trench floor and on the main area between adjacent trenches.
• the strip-shaped, doped regions adjoining the respective flank form the source / drain regions of the MOS transistors arranged on the flank.
• the first dielectric, floating gate, second dielectric and control gate are each arranged along the flank between the corresponding source / drain regions.
• a large number of memory cells are arranged along an edge.
• the floating gate and the control gate of memory cells adjacent along an edge are isolated from one another.
• Word lines run across the trenches, each of which is connected to control gates of vertical MOS transistors which are arranged below the respective word line.
• the floating gates preferably have a greater extent in the direction perpendicular to the main surface than corresponds to the depth of the trenches. As a result, the floating gates protrude beyond the main surface. In this way, the coupling capacitance between the floating gate and the control gate is increased.
• the read-only memory cell arrangement according to the invention can be produced in the self-adjusting manufacturing process with a space requirement of 2F 2 per memory cell, F being the minimum structure size in the respective technology .
• F being the minimum structure size in the respective technology .
• For the self-adjusting manufacture of the read-only memory cell arrangement only two masks produced photolithographically are required: a mask for trench etching, a further mask for structuring the word lines running transverse to the trenches.
• the floating gates are self-aligned to the flanks of the trenches by means of a spacer etching.
• the floating gates and the second dielectric are structured parallel to the course of the trenches using the word line mask.
• the spacer etching to form the floating gates is preferably carried out before the trench mask is removed.
• the extent of the floating gates perpendicular to the main surface can then be adjusted via the thickness of the trench mask.
• the trench mask is removed prior to the deposition of a second dielectric layer to form the second dielectric.
• the trench mask is removed before the deposition of the first doped polysilicon layer to form the floating gates.
• FIG. 1 shows a substrate with a doped region in the cell field.
• FIG. 2 shows the substrate with a trench mask after the etching of trenches.
• FIG. 3 shows the substrate after the formation of stripe-shaped, doped regions at the bottom of the trenches.
• FIG. 4 shows the substrate after formation of a first dielectric and doped polysilicon spacer on the flanks of the trenches.
• FIG. 5 shows the substrate after deposition of a second dielectric layer and a second doped polysilicon layer.
• FIG. 6 shows a plan view of the finished, electrically writable and erasable read value memory cell arrangement.
• a substrate 1 made of, for example, p-doped monocrystalline silicon with a dopant concentration of 5 ⁇ IO 15 cm “3 is provided on a main surface 2 with a scattering oxide in a thickness of, for example, 50 nm (not shown).
• a scattering oxide in a thickness of, for example, 50 nm (not shown).
• boron 160 keV, 6 x IO 13 cm “2
• a p-doped trough 3 with a dopant concentration of 3 x IO 17 cm “ 3 is produced (see FIG. 1).
• the scattering oxide is then passed through Etching removed.
• An insulation structure (not shown) is subsequently formed at the edge of the p-doped well 3, for example in a LOCOS process.
• the isolation structure defines the area for a cell field.
• an n + -doped region 4 is produced by implantation with arsenic, 50 keV, 5 x IO 15 cm “2.
• the n + -doped region 4 has a dopant concentration of 1 x IO 21 cm “3 on. It extends on the main surface 2 over the area for the cell field.
• the depth of the n + -doped region 4 is, for example, 200 nm.
• a layer of SiO 2 in a thickness of, for example, 50 nm is formed on the main surface 2 by thermal oxidation at, for example, 800 ° C. and a nitride layer in a thickness of 50 nm by CVD deposition.
• the layer made of SiO 2 and the nitride layer form an auxiliary layer 5 (see FIG. 2).
• a grave mask 6 in a TEOS process a 300 nm thick Si0 2 layer is then pick ⁇ chieden and patterned with the aid photolithographi ⁇ cher method by ani ⁇ otro- pe ⁇ dry etching, for example, CHF 3, 0 2 to form.
• the auxiliary layer 5 is structured according to the trench mask 6 by anisotropic dry etching.
• the etching of the auxiliary layer 5 takes place, for example, with CHF 3, 0 second
• a trench etching is carried out.
• the trench etching is carried out in an anisotropic dry etching process using, for example, HBr, He, 0 2 , NF 3 .
• trenches 7 are produced which have a depth of, for example, 0.6 ⁇ m.
• the trenches 8 extend over a block of the NAND cell field. They have a length of, for example, 8 ⁇ m and a width of, for example, 0.4 ⁇ m. In the cell adjacent trenches 7 are arranged at a distance of 0.4 ⁇ m.
• the trenches 7 run essentially parallel.
• a 20 nm thick TEOS layer (not shown) and then an Si 3 N 4 layer with a thickness of 80 nm, for example, are produced by conformal deposition.
• Si 3 N 4 layer with a thickness of 80 nm, for example, are produced by conformal deposition.
• ani ⁇ sotropes dry etching with CHF 3 0 2 are ge on vertical sides of the trenches 7 and the grave mask 6 Si 3 N 4 spacers 8 forms (see Figure 3).
• a scatter oxide layer 9 with a thickness of 20 nm is then deposited over the entire surface in a TEOS process.
• An ion implantation with As (5 ⁇ IO 15 cm “ 2.50 keV) is carried out, in which 7 n + -doped, strip-shaped regions 14a are formed on the bottom of the trenches.
• the doped regions 14a are activated by a tempering step strip-shaped, doped regions 14a, a doping substance concentration of, for example, 1 x IO 21 cm “3 is set.
• the Si 3 N 4 spacers 8 mask the flanks of the trenches 7 during the ion implantation. This avoids a shift in the operating voltage of the vertical MOS transistors formed on the flanks of the trenches 7.
• doped regions 14b On the main surface 2 of the semiconductor substrate 1, in the case of trench etching by structuring the n + -doped region 4 between adjacent trenches 7, strip-shaped, doped regions 14b have formed.
• the scatter oxide 9 is then removed, for example in an HF dip.
• wet etching for example with H 3 P0 4, the Si 3 N 4 spacers are removed JB.
• the thin oxide base is then removed wet-chemically with HF.
• Silicon surfaces are now exposed in the trenches 7 on the flanks and on the bottom.
• thermal oxidation for example at 800 ° C., a first dielectric layer 10 made of SiO 2 is formed at least on the exposed silicon surfaces.
• the first dielectric layer 10 is formed on the flanks with a thickness of 10 nm, for example. Because of the increased doping of the strip-shaped, doped regions 14a at the bottom of the trenches 7, the first dielectric layer is formed there in a thickness of 50 nm.
• doped polysilicon spacers 11 are produced on the flanks of the trenches (see FIG. 4).
• an undoped polysilicon layer can also be deposited, which is then doped by covering.
• the trench mask 6 is subsequently removed by wet etching, for example using HF steam. During this etching, deposited Si0 2 is selectively removed to thermal Si0 2 in a TEOS process. The auxiliary layer 5 and the first dielectric layer 10 on the surface of the strip-shaped doped regions 14a, b are not attacked during this etching (see FIG. 5). This etching is also selective with respect to polysilicon. The doped polysilicon spacers 11 protrude beyond the main surface 3 after the trench mask 6 has been removed. The expansion of the polysilicon spacers 11 in the direction vertical to the main surface 2 is given by the thickness of the trench mask 6.
• a second dielectric layer 12 is then produced over the entire surface.
• the second dielectric layer 12 is formed as a multiple layer from a first Si0 2 layer, an Si 3 N 4 layer and a second Si0 2 layer.
• the Si 3 N 4 layer is deposited in a CVD process, the first and second SiO 2 layers are dation formed.
• the second dielectric layer 12 is formed in a thickness of 8 nm.
• a second doped polysilicon layer 13 is then deposited.
• the second doped polysilicon layer 13 is deposited in situ doped. It is deposited in a thickness of, for example, 500 nm.
• the second doped polysilicon layer 13 completely fills the trenches 7. It also fills the space between adjacent polysilicon spacers 11 on the main surface 2.
• a word line mask is subsequently formed by deposition of a TEOS-Si0 2 layer in a thickness of, for example, 100 nm and structuring of the TEOS-Si0 2 layer with the aid of photolithographic process steps (not shown).
• the word line mask defines word lines extending transversely to the trenches 7.
• the second polysilicon layer 13 is structured in an anisotropic dry etching process, for example with HBr, Cl 2 , He. This results in word lines 13a running transversely to the trenches 7 (see top view in FIG. 6) and in the region of the trenches 7 control gates.
• the etching is interrupted as soon as the surface of the second dielectric layer 12 is exposed.
• the second dielectric layer 12 is etched in the ONO bei ⁇ piel ⁇ weise with CHF 3, 0. 2
• the polysilicon (HBr, Cl 2 , He) is etched again with high selectivity to (oxide / nitride).
• the floating gate and the control gate are now etched down to the bottom of the trench. During this etching, floating gates are formed from the doped polysilicon spacer 11.
• the second dielectric layer 12 is then removed by wet etching, for example using HF, H 3 PO 4 .
• wet etching for example using HF, H 3 PO 4 .
• the first dielectric layer 10 is exposed in the trenches 7 between adjacent word lines 13a. That means that between adjacent word lines 13a, the trenches 7 are opened except for the first dielectric layer 10.
• This space is then filled by depositing a TEOS-Si0 2 layer in a layer thickness of, for example, 800 nm and etching back the TEOS-Si0 2 layer until the surface of the word lines 13a is exposed (not shown).
• a planarizing intermediate is schenoxid ⁇ chicht whole area, for Bei ⁇ piel au ⁇ Borpho ⁇ phorsilikatglas> deposited, be open in the contact holes.
• Contact holes become, inter alia, the word lines 13a, the strip-shaped doped regions 14a which are arranged at the bottom of the trenches 7 and the strip-shaped, doped regions 14b which are arranged on the main surface 2 between adjacent trenches 7 are opened.
• the contact holes are filled with aluminum, for example.
• a metallization level for example by depositing and structuring an aluminum layer.
• a passivation layer is applied.
• the individual memory cells are evaluated according to the “virtual ground” principle.
• Each of the strip-shaped, doped regions 14a, 14b is assigned to two rows of memory cells.
• a pair of the strip-shaped doped regions 14a, 14b, which is composed of adjacent doped areas on the main surface 14a and on the bottom 14b, is clearly assigned to a row of memory cells.
• the current is therefore selected via the word line 13a.
• the strip-shaped, doped regions 14a, 14b on the bottom of the trenches 7 and on the main surface 2 act, depending on the circuitry, as a reference line or as a bit line.
• the information is written into the memory cells, as is usual with EEPROM arrangements, by "hot electron” injection.
• the memory cells are erased in a Fowler-Nordheim process.
• the doped, strip-shaped regions 14a, b are placed on the left of a selection transistor on a first supply voltage, for example V d d, and the doped, strip-shaped regions 14a, b on the right of the selection transistor are placed on a second supply voltage, for example V ⁇ s .
• a high gate voltage of, for example, 7 volts is applied to the part of the word line 13a arranged in the trench 7, which acts as a control gate. This injects electrons into the associated floating gate.
• the floating gates are discharged to the substrate by a Fowler-Nordheim process.
• FIG. 6 shows a plan view of the cell field of the fixed value memory cell arrangement according to the invention.
• the cell size of the memory cells is entered as a dash-dotted line.
• the width of the memory cells is composed of half the width of the trench 7 and half the distance between adjacent trenches.
• the length of a memory cell is composed of the width of the word line 13a and twice half the distance between adjacent word lines 13a. If the trenches 7 are formed with a width of F and at a distance from F and the word lines 13a are formed with a width of F and a distance from F, wherein F is the minimum structure size in the respective technology, this results in a memory cell area of 2F 2 .

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• 1995
  • 1995-07-05 DE DE19524478A patent/DE19524478C2/de not_active Expired - Fee Related
• 1996
  • 1996-06-25 JP JP50470097A patent/JP3615765B2/ja not_active Expired - Fee Related
  • 1996-06-25 KR KR1019970709885A patent/KR100417451B1/ko not_active Expired - Fee Related
  • 1996-06-25 DE DE59607727T patent/DE59607727D1/de not_active Expired - Lifetime
  • 1996-06-25 WO PCT/DE1996/001117 patent/WO1997002599A1/de active IP Right Grant
  • 1996-06-25 US US08/973,701 patent/US5998261A/en not_active Expired - Lifetime
  • 1996-06-25 EP EP96918610A patent/EP0836747B1/de not_active Expired - Lifetime
  • 1996-06-28 IN IN1203CA1996 patent/IN189218B/en unknown

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