TW583755B - Method for fabricating a vertical nitride read-only memory (NROM) cell - Google Patents
Method for fabricating a vertical nitride read-only memory (NROM) cell Download PDFInfo
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- TW583755B TW583755B TW091133597A TW91133597A TW583755B TW 583755 B TW583755 B TW 583755B TW 091133597 A TW091133597 A TW 091133597A TW 91133597 A TW91133597 A TW 91133597A TW 583755 B TW583755 B TW 583755B
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- 150000004767 nitrides Chemical class 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 238000009413 insulation Methods 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- -1 nitride nitride Chemical class 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 238000005192 partition Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 97
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
- 229910052814 silicon oxide Inorganic materials 0.000 description 17
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- 238000005530 etching Methods 0.000 description 11
- 238000003860 storage Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052778 Plutonium Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- OYEHPCDNVJXUIW-UHFFFAOYSA-N plutonium atom Chemical compound [Pu] OYEHPCDNVJXUIW-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000001397 quillaja saponaria molina bark Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229930182490 saponin Natural products 0.000 description 1
- 150000007949 saponins Chemical class 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
583755 五、發明說明（l) 發明所屬之領域： ,:明係有關於一種非揮發記憶單元極其製造方法， 甘制=士關於一種垂直式氮化物唯讀記憶單元（NROM )及 其1地方法，以提高記憶單元之效能。 先前技術： f 揮發記憶體工業中，氮化物唯讀記憶單元（nr〇m W用4 ^源，西d Μ6年。此新式的非揮發記憶體技術 ' 氮化—氧化（oxide-nitride-〇xide，ΟΝΟ ) 層=閘極介電層並藉由習知之程式化及抹除之機制而建 f出母：'己憶皁元擁有兩分離之位元線。目此，氮化物唯 讀記憶單元隻位元線大小約為整個記憶單元面積之一半。 由=晶粒之尺寸大小為成本架構中的主要要素，顯然這 就疋亂化物唯讀記憶單元技術為何能具有經濟上的競 之原因。 第1圖係繪示出傳統氮化物唯讀記憶單元之結構剖面 示意圖。&記憶單元包含-秒基底丨⑽，其具有兩分離的 位元線（源極及汲極）102 ,兩位元線絕緣層1〇4係各設置 於兩位元線102之上方，且一0N0層112係設置於兩位元線 102之間的基底100上方。此〇N〇層丨12係由一底層氧化矽声 106、一氮化矽層108、及一上層氧化矽層丨1〇依序堆疊而" 成。一閘極導電層（字元線）1丨4係設置於位元線絕緣層 104及0Ν0層112上方。 在0Ν0層112中的氮化矽層Η2具有兩電荷儲存區 1 0 7, 1 09，其鄰近於位元線1〇2。兩電荷儲存區1〇7, 1〇9係 0548-8786TWF(Nl) ； 91132 ； Spin.ptd 第6頁 583755 五、發明說明（2) 在程式化記憶單元期間用以儲存電荷。當利用電荷儲存區 1 0 7私一式化左邊的位元時，左邊的位元線1〇2作為汲極並接 收一咼程式化電壓。同時，右邊的位元線1〇2係作為源極 並接地。同理:當利用電荷儲存區1〇9程式化右邊的位元 時右邊的位元線1 〇 2作為沒極並接收一高程式化電壓。 一同時，左邊的位元線1 〇 2係作為源極並接地。再者， 當讀取左邊的位元（電荷儲存區1〇7)時，左邊的位元線 102作為源極且右邊的位元線1〇2係作為汲極。同理，當讀 取右邊的位兀（電荷儲存區丨〇 9 )時，右邊的位元線1 〇 2作 ^源極且左邊的位元線丨02係作為汲極。另外，進行抹除 時，其源汲極的相對位置與進行程式化時相同。 / —為了增加A憶單元密度以提升積體電路之積集度，必 須縮小位兀線之面積或縮小〇N〇層之寬度（兩字元線之間 距）。不幸地，當縮小位元線之面積時，會提高位元線之 電阻而造成記憶裝置的操作速度降低。另一方面，若縮小 0^10層之見度，則會在程式化、抹除或讀取期間發生記憶 早兀中兩電荷儲存區相互干擾（cell disturbance)的情 形。，別是當0N0層之寬度小於1〇奈米（nm)時。亦即， =:單兀密度會文限於上述原目而無法增加積冑電路之積 集度。 發明内容： =此’本發明之目的在於提供一種新穎的垂直式 唯讀記憶單元及其製造方法，其利用溝槽側壁的基 底作為亂化物唯讀記憶單元之通道1以降低位元線之電583755 V. Description of the invention (l) Field of the invention: The Ming system relates to a non-volatile memory unit and extremely manufacturing method, and the system is related to a vertical nitride read-only memory unit (NROM) and its method. To improve the performance of the memory unit. Previous technologies: f In the volatile memory industry, nitride read-only memory cells (nr0m W use 4 ^ source, West dM6 years. This new non-volatile memory technology 'oxide-nitride-〇 xide, ΟΝΟ) layer = gate dielectric layer and built through the familiar mechanism of stylization and erasure: 'Jiyi saponin has two separate bit lines. For this reason, nitride read-only memory The bit line size of a cell is about one-half of the entire memory cell area. Since the size of the die is the main factor in the cost structure, obviously this is why the read-only memory cell technology can be economically competitive. Figure 1 is a schematic cross-sectional view showing the structure of a conventional nitride read-only memory cell. &Amp; The memory cell includes a -second substrate, which has two separate bit lines (source and drain) 102, two bits. The element wire insulation layers 104 are each disposed above the two-bit element lines 102, and a 0N0 layer 112 is disposed above the base 100 between the two-bit element lines 102. The 0N0 layer 12 is composed of a bottom layer Silicon oxide sound 106, a silicon nitride layer 108, and an upper silicon oxide layer A gate conductive layer (word line) 1-4 is disposed above the bit line insulation layer 104 and the ON0 layer 112. The silicon nitride layer Η2 in the ON0 layer 112 has two charge storages. Region 1 0 7, 1 09, which is adjacent to the bit line 102. The two charge storage regions 107, 109 are 0548-8786TWF (Nl); 91132; Spin.ptd Page 6 583755 5. Description of the invention (2) Used to store the charge during the programmed memory cell. When the left bit is privately formatted using the charge storage area 107, the left bit line 102 is used as the drain and receives a programmed voltage. At the same time, the bit line 102 on the right is used as the source and grounded. The same applies: when the right bit is programmed using the charge storage area 10, the bit line 102 on the right is used as the no pole and receives a high Program the voltage. At the same time, the left bit line 102 is used as the source and grounded. Furthermore, when the left bit line (charge storage area 107) is read, the left bit line 102 is used as the source. The bit line 102 on the right and the right is used as the drain. Similarly, when the bit on the right (charge storage area 丨 〇9) is read, the bit on the right is Line 1 〇2 is the source and the bit line on the left is the drain. In addition, the relative position of the source and drain when erasing is the same as when programming. /-In order to increase the density of the A memory cell In order to increase the integration degree of the integrated circuit, it is necessary to reduce the area of the bit line or the width of the OO layer (the distance between the two word lines). Unfortunately, when the area of the bit line is reduced, the bit is increased. The resistance of the wire reduces the operating speed of the memory device. On the other hand, if the visibility of the 0 ^ 10 layer is reduced, the two charge storage areas in the memory may interfere with each other during programming, erasing or reading ( cell disturbance). , Especially when the width of the 0N0 layer is less than 10 nanometers (nm). That is to say, =: simple density is limited to the above-mentioned original purpose and cannot increase the integration degree of the accumulation circuit. Summary of the invention: = This ’The purpose of the present invention is to provide a novel vertical read-only memory cell and a manufacturing method thereof, which uses the substrate of the sidewall of the trench as the channel 1 of the random read-only memory cell to reduce the bit line electricity.
583755 五、發明說明（3) P且。 本發，之另一目的在於提供—種新穎的垂直式氮化物 唯讀記憶單元及其製造方法，其藉由形成垂直式的通道以 取代傳統水平式之通道’藉以防止在進行程式化、抹除或 讀取期間發生記憶單元干擾（cell disturbance)。 根據上述之目的，本發明提供一種垂直式氮化物唯讀 記憶=之製造方法。t先，提供具有至少一溝槽之基底 ，且/ a之側壁形成有一間隙壁。隨後，以間隙壁作為罩 幕以對，底f施離子植A，而|鄰近基底纟面及溝槽底部 之基底中形成作為位元線之摻雜區。接下|，在位元線上 方形成位兀線絕緣層並接著去除間隙壁。之後，順應性形 成一絕緣層於位元線絕緣層表面及溝槽側壁以作為^極 電層。最後，纟絕緣層上形成—導電層並填人溝槽以作為 字元線。 ” =據上…的’本發明提供一種垂直式氮 憶單^括：—具有至少—溝槽之基底 、複數位几線、複數位元線絕緣層、一閘極介電層及一丰 ::。：”元線係形成於鄰近基底表面及溝槽底部之基 底中，且母一位兀線上方設置有位元線絕緣層。 層係順應性地設置於溝槽側壁及位元線絕緣層表面。^ 線係3又置於閘極介電層上方並填入溝槽。 其中，為元線係藉由磷離子植入所形成且 層係藉由熱氧化法所形成。再者，閉極介電層係緣 虱化-乳化（ΟΝΟ)層’而字元線係由複晶矽所構成。583755 V. Description of the invention (3) P and. Another purpose of the present invention is to provide a novel vertical nitride read-only memory cell and a method for manufacturing the same, by forming a vertical channel instead of a traditional horizontal channel to prevent programming and erasing. Cell disturbance occurs during division or reading. According to the above object, the present invention provides a method for manufacturing a vertical nitride read-only memory. First, a substrate having at least one trench is provided, and a sidewall is formed on a sidewall of / a. Subsequently, the spacer wall is used as a mask to face, and the bottom f is implanted with ion implantation A, and a doped region serving as a bit line is formed in the substrate near the base surface of the substrate and the bottom of the trench. Connect | to form a bit line insulation layer above the bit line and then remove the spacer. Afterwards, an compliance layer is formed on the surface of the bit line insulation layer and the sidewalls of the trenches to serve as the anode layer. Finally, a conductive layer is formed on the plutonium insulating layer and fills the trench as a word line. According to the above, the present invention provides a vertical nitrogen memory unit including:-a substrate having at least-a trench, a plurality of bit lines, a plurality of bit line insulation layers, a gate dielectric layer, and a ferrite: :.: "The element line is formed in the substrate adjacent to the substrate surface and the bottom of the trench, and a bit line insulation layer is disposed above the female bit line. The layer system is compliantly disposed on the sidewall of the trench and the surface of the bit line insulation layer. ^ Line 3 is placed above the gate dielectric and fills the trench. Among them, the element line is formed by phosphorus ion implantation and the layer is formed by a thermal oxidation method. In addition, the closed-dielectric layer is a lice-emulsified (ONO) layer 'and the character lines are composed of polycrystalline silicon.
0548-8786TWF(Nl) ； 91132 ： Spin.ptd 第8頁 5837550548-8786TWF (Nl); 91132: Spin.ptd page 8 583755
為讓本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如 下： 實施方式： 以下配合第2a到2 f圖說明本發明實施例之垂直氮化 唯讀記憶單元製造方法。首先，參照第2a圖，提供一基 底2 0 0，例如一矽晶圓。在基底2 〇 〇表面上形成一罩幕層 2〇5，其可為單層結構或數層的堆疊結構。如圖中所示， 罩幕層205較佳是由一層墊氧化矽層2〇2與一層較厚的氮化 石夕層204所組成。其中，墊氧化矽層2〇2的厚度約1〇〇埃 (A )左右，且其形成方法可為熱氧化法或是以習知的常 壓（atmospheric)或低壓化學氣相沉積法（1〇w pressure chemical vap〇r dep〇sUi〇n，LpcVD)沉積而 成在墊氧化矽層20 2之上的氮化矽層204的厚度約在1〇〇〇 到2000埃的範圍，且可利用低壓化學氣相沉積法，以二氣 f烷（SiCl^)與氨氣（㈣3)為反應原料沉積而成。接 ，，在罩幕層205表面上形成一層光阻層2〇β。之後，藉由 習知微影製程於光阻層206中形成複數開口2〇7。 曰 接下來，請參照第2b圖，藉由具有開口 207之光阻層 206作為蝕刻罩幕，對罩幕層2〇5進行非等向性蝕刻製程， 例如反應離子蝕刻（reactive i〇n etching，RIE)，以 將光阻層20 6的開口 207圖案轉移至罩幕層205中。接著， 以適當蝕刻溶液或灰化處理來去除光阻層2 〇 6之後，藉由 罩幕層205作為蝕刻罩幕，進行非等向性蝕刻製程，例如In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following exemplifies preferred embodiments in combination with the accompanying drawings to describe them in detail as follows: Embodiments: The following describes the present invention in conjunction with Figures 2a to 2f. The manufacturing method of the vertical nitrided read-only memory cell of the embodiment of the invention. First, referring to Figure 2a, a substrate 200 is provided, such as a silicon wafer. A cover layer 205 is formed on the surface of the substrate 2000, which may be a single-layer structure or a stacked structure of several layers. As shown in the figure, the cover layer 205 is preferably composed of a silicon oxide layer 202 and a thicker nitride layer 204. The thickness of the pad silicon oxide layer 200 is about 100 angstroms (A), and the formation method may be a thermal oxidation method or a conventional atmospheric or low-pressure chemical vapor deposition method (1 〇w pressure chemical vap〇r dep〇sUnion (LpcVD) is deposited on the pad silicon oxide layer 20 2 to a thickness of the silicon nitride layer 204 in the range of about 1000 to 2000 angstroms, and can be used A low-pressure chemical vapor deposition method is formed by using digas falkane (SiCl ^) and ammonia gas (㈣3) as reaction raw materials. Then, a photoresist layer 20β is formed on the surface of the mask layer 205. After that, a plurality of openings 207 are formed in the photoresist layer 206 by a conventional lithography process. Next, referring to FIG. 2b, by using the photoresist layer 206 with the opening 207 as an etching mask, the mask layer 20 is subjected to an anisotropic etching process, such as reactive ion etching (reactive ion etching). (RIE) to transfer the pattern of the openings 207 of the photoresist layer 206 into the mask layer 205. Next, after removing the photoresist layer 2 with an appropriate etching solution or ashing treatment, the mask layer 205 is used as an etching mask to perform an anisotropic etching process, such as
0548-8786WF(Nl) ； 91132 ； Spin.ptd 第9頁 583755 五、發明說明（5) 反^離子蝕刻，以將罩幕層2〇5之開口下方之基底2〇〇蝕刻 至一預定深度而形成深度約為14〇〇〜160〇人之複數溝槽 2 0 8 ° ，下來，請參照第2c圖，將罩幕層2〇5剝除。其中， 剝除氮化石夕層204的方法為濕式蝕刻法，例如是以熱磷酸 (ΙΡ〇4 )為蝕刻液來浸泡而將其去除，剝除墊氧化矽層 2 〇 2的方法為濕式蝕刻法，其例如是以氫氟酸（叮）為蝕 刻液來浸泡。之後，藉由CVD法在基底2〇〇上方及溝槽2〇8 表，順應性形成一氧化矽層210 ,其厚度約1〇()埃左右。此 薄氧化矽層210係用以修補在蝕刻溝槽2〇8期間形成於基底 2〇〇中的缺陷（未繪示）。接著，在氧化矽層21〇上方順應 性沉積一氮化矽層2 11。同樣地，氮化矽層2丨j可利用低壓 化學氣相沉積法，以二氣矽烷（Sicl2H2 )與氨氣（NH3 ) 為反應原料沉積而成。 接下來，請參照第2d圖，非等向性蝕刻氮化矽層2 i i ，例如RIE，以在每一溝槽208的側壁上形成一間隙^212 。之後，利用間隙壁212作為罩幕而在溝槽2〇8的底$及基 底2 0 0表面實施一離子植入，例如使用磷離子，藉以在溝 槽208底部及鄰近基底2〇〇表面處之基底2〇〇中各形雜 區214，以作為位元線。 乡雜 接下來，請參照第2e圖，藉由熱氧化法或其他沉積技 術在每一摻雜區2 1 4上方形成位元線絕緣層2 1 6，例如氧化 矽層。位元線絕緣層2 1 6通常非常厚，用以降低位元線與 字兀線間所形成的電容值。在本實施例中，位元線絕緣層0548-8786WF (Nl); 91132; Spin.ptd page 9 583755 V. Description of the invention (5) Reverse ion etching to etch the substrate 200 under the opening of the mask layer 200 to a predetermined depth and A plurality of grooves 208 ° with a depth of about 1400 to 160 are formed. Then, referring to FIG. 2c, peel off the mask layer 205. The method for stripping the nitride nitride layer 204 is a wet etching method. For example, the method is immersed with hot phosphoric acid (IP04) as an etching solution to remove it, and the method for stripping the silicon oxide layer 002 is wet. The etching method is, for example, immersion with hydrofluoric acid (ding) as an etching solution. After that, a silicon oxide layer 210 is conformably formed on the substrate 200 and the trench 208 table by a CVD method, and has a thickness of about 10 angstroms. The thin silicon oxide layer 210 is used to repair defects (not shown) formed in the substrate 200 during the etching of the trenches 208. Next, a silicon nitride layer 21 is compliantly deposited on the silicon oxide layer 21o. Similarly, the silicon nitride layer 2j can be deposited by using a low-pressure chemical vapor deposition method using two gas silanes (Sicl2H2) and ammonia gas (NH3) as reaction materials. Next, referring to FIG. 2d, the silicon nitride layer 2 i i is anisotropically etched, such as RIE, to form a gap ^ 212 on the sidewall of each trench 208. After that, the spacer 212 is used as a mask to perform an ion implantation on the bottom of the trench 208 and the surface of the substrate 2000. For example, phosphorus ions are used at the bottom of the trench 208 and at the surface of the substrate 200 adjacent to the substrate. Various shaped miscellaneous regions 214 in the base 200 are used as bit lines. Rural Miscellaneous Next, referring to FIG. 2e, a bit line insulating layer 2 1 6 such as a silicon oxide layer is formed over each doped region 2 1 4 by thermal oxidation or other deposition techniques. The bit line insulation layer 2 1 6 is usually very thick to reduce the capacitance value formed between the bit line and the word line. In this embodiment, the bit line insulation layer
583755 五、發明說明（6) 2 W厚度約在50 0到700埃的範圍。之後，藉由濕蝕刻依 序去除間隙壁212及氧化石夕層21〇。 蚀幻依 -維ί :…在溝槽2〇8側壁及位元線絕緣層21 6表面順應性 =:223,例如一氧化一氮化_氧化（_)層，以： 為閘極” '層。在本實施例中，此〇Ν〇層223係由一氧化 層218一氮化矽層22〇、及一氧化矽層222依序堆疊而 成，且氮化矽層220及兩氧化矽層218，222的厚度分 30〜10J)埃的範圍。再者，氧化矽層218可藉由熱氧化法形 成。氮化矽層220及氧化矽層222則可藉由CVD法形成。如 先前所述，此ΟΝΟ層223係在記憶單元進行程式化期間作為 儲存電荷之用，而電荷儲存區（未繪示）係位於溝槽2〇8 側壁上的氮化矽層220中並鄰近於溝槽208上方及底部之摻 雜區214。而不同於習之技術之處在於本發明係以溝槽2〇& 側壁之基底2 0 0作為記憶單元之通道。亦即，根據本發明 之氮化物唯讀記憶單元之製造方法，可形成一垂直式通 道，而不同於習之技術中的水平式通道。 最後’请參照第2 f圖，一導電層2 2 4，例如複晶石夕， 係形成於閘極介電層223上方並完全填入溝槽208。在本實 施例中，導電層224的厚度約在15〇〇到200 0埃的範圍且可 藉由CVD法形成。之後，可藉由化學機械研磨法 (chemical mechanic polishing，CMP)對導電層 224 進 行平坦化。接著，在導電層224上塗覆一光阻層（未繪示 )。隨後藉由習知微影及蝕刻程序，藉以定義出由導電層 2 2 4所構成之位元線’如此便完成垂直式氮化物唯讀記憶583755 5. Description of the invention (6) The thickness of 2 W is in the range of 50 0 to 700 Angstroms. After that, the spacer 212 and the oxide scale layer 21 are sequentially removed by wet etching. Etching Ei-Wei: ... compliance on the sidewall of the trench 20 and the surface of the bit line insulation layer 21 6 = 223, such as a nitric oxide-nitride (_) layer, as: "Gate" In this embodiment, the ONO layer 223 is formed by sequentially stacking an oxide layer 218, a silicon nitride layer 22, and a silicon oxide layer 222, and the silicon nitride layer 220 and silicon dioxide The thicknesses of the layers 218 and 222 are in the range of 30 to 10 J). Furthermore, the silicon oxide layer 218 can be formed by a thermal oxidation method. The silicon nitride layer 220 and the silicon oxide layer 222 can be formed by a CVD method. It is mentioned that the ONO layer 223 is used for storing charges during the programming of the memory cell, and the charge storage area (not shown) is located in the silicon nitride layer 220 on the sidewall of the trench 208 and is adjacent to the trench. The doped region 214 above and at the bottom of the trench 208. What is different from Xi's technique is that the present invention uses the trench 20 & sidewall substrate 200 as the channel of the memory cell. That is, the nitrogen according to the present invention The manufacturing method of the material-only memory unit can form a vertical channel, which is different from the horizontal channel in Xi's technology. Finally ' Referring to FIG. 2f, a conductive layer 2 2 4 such as polycrystalline spar is formed above the gate dielectric layer 223 and completely fills the trench 208. In this embodiment, the thickness of the conductive layer 224 is about The range is from 150 to 200 angstroms and can be formed by a CVD method. Thereafter, the conductive layer 224 can be planarized by chemical mechanic polishing (CMP). Then, a conductive layer 224 is coated on the conductive layer 224 Photoresist layer (not shown). Then, through the conventional lithography and etching procedures, the bit line formed by the conductive layer 2 2 4 is defined, thus completing the vertical nitride read-only memory.
583755 五、發明說明（7) 單元之製造，如第3圖所示，其繪示出第2f圖中垂直式氮 化物唯讀記憶單元之平面圖。 同樣地’請參照第2 f圖，其會釋出根據本發明實施例 之垂直式氮化物唯讀記憶單元之結構剖面示意圖。此記憶 單元包含一具有複數溝槽2〇8之基底2〇〇，及形成於鄰近基 底20 0表面及溝槽2〇8底部之基底2〇〇中的複數位元線21 4。 在本實施例中，溝槽208的深度約在1 400到1 60 0埃的範 圍。再者’位元線2 1 4係藉由林離子植入所形成。複數位 兀線絕緣層2 1 6係設置於每一位元線2丨4上方，其厚度約在 50 0到700埃的範圍。一閘極介電層223，例如由一氧化矽 層218、一氮化矽層220、及一氧化矽層222依序堆疊而成 之ΟΝΟ結構，順應性地設置於溝槽2 〇 8側壁及位元線絕緣層 2 1 6表面上。一子元線2 2 4，例如由複晶矽所構成，係設置 於閘極介電層223上並填入溝槽2〇8中。 相較於習知技術，本發明之氮化物唯讀記憶單元具有 一垂直式通道，其可調整出適當的通道長度來防止發生記 憶單元干擾，如先前所述。亦即，通道的長度係取^於溝 槽之深度。只要溝槽的深度夠深，就可避免記憶單元干擾 的情形。再者，由於氮化物唯讀記憶單元的通道位於溝槽 側壁之基底中，因此整個基底平面可供離子植入來形成位 元線之用。亦即，可增加位元線的面積而減少其電阻，藉 以增加氮化物唯讀記憶單元之操作速度。因此，根據本發 明之垂直式氮化物唯讀記憶單元及其製造方法，可提其之 效能。583755 5. Description of the invention (7) As shown in Fig. 3, the manufacturing of the unit shows the plan view of the vertical nitride read-only memory cell in Fig. 2f. Similarly, please refer to FIG. 2f, which will release a schematic cross-sectional view of a structure of a vertical nitride read-only memory cell according to an embodiment of the present invention. The memory cell includes a substrate 2000 having a plurality of grooves 208 and a plurality of bit lines 21 4 formed in the substrate 2000 adjacent to the surface of the substrate 200 and the bottom of the grooves 208. In the present embodiment, the depth of the trench 208 is in the range of about 1,400 to 1,600 Angstroms. Furthermore, the 'bit line 2 1 4' is formed by the ion implantation. The plurality of bit-line insulation layers 2 1 6 are disposed above each bit line 2 丨 4, and have a thickness in the range of 50 to 700 angstroms. A gate dielectric layer 223, for example, a NOO structure formed by sequentially stacking a silicon oxide layer 218, a silicon nitride layer 220, and a silicon oxide layer 222, is compliantly disposed on a side wall of the trench 208 and Bit line insulation layer 2 1 6 on the surface. A sub-element line 2 2 4 is composed of, for example, polycrystalline silicon, and is disposed on the gate dielectric layer 223 and filled in the trench 208. Compared with the conventional technology, the nitride read-only memory cell of the present invention has a vertical channel, which can be adjusted to an appropriate channel length to prevent memory cell interference from occurring, as previously described. That is, the length of the channel is taken from the depth of the groove. As long as the depth of the grooves is deep enough, memory cell interference can be avoided. Furthermore, since the channel of the nitride read-only memory cell is located in the substrate on the sidewall of the trench, the entire substrate plane can be used for ion implantation to form bit lines. That is, the area of a bit line can be increased to reduce its resistance, thereby increasing the operating speed of a nitride read-only memory cell. Therefore, according to the vertical nitride read-only memory cell of the present invention and the manufacturing method thereof, its efficiency can be improved.
0548-8786TWF(Nl); 91132 ； Spin.ptd 第12頁 583755 五、發明說明（8) 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。0548-8786TWF (Nl); 91132; Spin.ptd Page 12 583755 V. Description of the invention (8) Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art Changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.
0548-8786TWF(Nl) ； 91132 ； Spin.ptd 第13頁 583755 圖式簡單說明 第1圖係繪示出傳統氮化物唯讀記憶單元之結構剖面 示意圖。 第2a到2 f圖係繪示出根據本發明實施例之垂直氮化物 唯讀記憶單元製造方法之剖面示意圖。 第3圖係繪示出第2 f圖中垂直式氮化物唯讀記憶單元 之平面圖。 [符號說明] 100、200〜基底； 1 0 2、2 1 4〜位元線； 1 0 4、2 1 6〜位元線絕緣層； 106、 110、210、218、222〜氧化矽層； 107、 109〜電荷儲存區； 108、 204、211、220 〜氮化矽層； 112 、 223〜ΟΝΟ 層； 114、224〜字元線； 2 0 2〜墊氧化矽層； 205〜罩幕層； 2 0 6〜光阻層； 207〜開口； 208〜溝槽； 2 1 2〜間隙壁。0548-8786TWF (Nl); 91132; Spin.ptd Page 13 583755 Brief Description of Drawings Figure 1 is a schematic cross-sectional view showing the structure of a conventional nitride read-only memory cell. Figures 2a to 2f are schematic cross-sectional views illustrating a method for manufacturing a vertical nitride read-only memory cell according to an embodiment of the present invention. Figure 3 is a plan view showing the vertical nitride read-only memory cell in Figure 2f. [Symbol description] 100, 200 ~ substrate; 10, 2 1 4 ~ bit line; 104, 2 1 6 ~ bit line insulation layer; 106, 110, 210, 218, 222 ~ silicon oxide layer; 107, 109 ~ charge storage area; 108, 204, 211, 220 ~ silicon nitride layer; 112, 223 ~ 〇ΝΟ layer; 114, 224 ~ word line; 2 0 2 ~ pad silicon oxide layer; 205 ~ mask layer 206 ~ photoresist layer; 207 ~ opening; 208 ~ groove; 2 1 ~ 2 spacer wall.
0548-8786TWF(Nl) ； 91132 ； Spin.ptd 第14頁0548-8786TWF (Nl); 91132; Spin.ptd page 14
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| TWI288473B (en) * | 2005-10-05 | 2007-10-11 | Promos Technologies Inc | Flash memory structure and method for fabricating the same |
| US7592224B2 (en) | 2006-03-30 | 2009-09-22 | Freescale Semiconductor, Inc | Method of fabricating a storage device including decontinuous storage elements within and between trenches |
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| US7572699B2 (en) * | 2007-01-24 | 2009-08-11 | Freescale Semiconductor, Inc | Process of forming an electronic device including fins and discontinuous storage elements |
| US7651916B2 (en) * | 2007-01-24 | 2010-01-26 | Freescale Semiconductor, Inc | Electronic device including trenches and discontinuous storage elements and processes of forming and using the same |
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| US8409952B2 (en) * | 2008-04-14 | 2013-04-02 | Spansion Llc | Method of forming an electronic device including forming a charge storage element in a trench of a workpiece |
| KR101096164B1 (en) * | 2009-11-30 | 2011-12-22 | 주식회사 하이닉스반도체 | Method for manufacturing side contact in semiconductor device using double trench process |
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| JPH0567791A (en) * | 1991-06-20 | 1993-03-19 | Mitsubishi Electric Corp | Electrically writable and erasable semiconductor memory device and its manufacture |
| US5429977A (en) * | 1994-03-11 | 1995-07-04 | Industrial Technology Research Institute | Method for forming a vertical transistor with a stacked capacitor DRAM cell |
| US5460988A (en) * | 1994-04-25 | 1995-10-24 | United Microelectronics Corporation | Process for high density flash EPROM cell |
| US5703387A (en) * | 1994-09-30 | 1997-12-30 | United Microelectronics Corp. | Split gate memory cell with vertical floating gate |
| US5595927A (en) * | 1995-03-17 | 1997-01-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for making self-aligned source/drain mask ROM memory cell using trench etched channel |
| DE19524478C2 (en) * | 1995-07-05 | 2002-03-14 | Infineon Technologies Ag | Method for producing a read-only memory cell arrangement |
| DE19600423C2 (en) * | 1996-01-08 | 2001-07-05 | Siemens Ag | Electrically programmable memory cell arrangement and method for its production |
| DE19609678C2 (en) * | 1996-03-12 | 2003-04-17 | Infineon Technologies Ag | Memory cell arrangement with stripe-shaped, parallel trenches and vertical MOS transistors and method for their production |
| DE19720193C2 (en) * | 1997-05-14 | 2002-10-17 | Infineon Technologies Ag | Integrated circuit arrangement with at least two vertical MOS transistors and method for their production |
| KR19980084469A (en) | 1997-05-23 | 1998-12-05 | 문정환 | Mask ROM and Manufacturing Method |
| US6008079A (en) * | 1998-03-25 | 1999-12-28 | Texas Instruments-Acer Incorporated | Method for forming a high density shallow trench contactless nonvolatile memory |
| US6555870B1 (en) * | 1999-06-29 | 2003-04-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method for producing same |
| TW508590B (en) * | 2001-05-09 | 2002-11-01 | Macronix Int Co Ltd | Operating method of flash memory with symmetrical dual channel |
| US6486028B1 (en) * | 2001-11-20 | 2002-11-26 | Macronix International Co., Ltd. | Method of fabricating a nitride read-only-memory cell vertical structure |
| TW575945B (en) * | 2002-12-17 | 2004-02-11 | Nanya Technology Corp | Method for fabricating a vertical NROM cell |
-
2002
- 2002-11-18 TW TW091133597A patent/TW583755B/en not_active IP Right Cessation
- 2002-12-13 US US10/318,551 patent/US7005701B2/en not_active Expired - Lifetime
-
2003
- 2003-10-27 US US10/694,155 patent/US6916715B2/en not_active Expired - Lifetime
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| US7005701B2 (en) | 2006-02-28 |
| US20040097036A1 (en) | 2004-05-20 |
| US6916715B2 (en) | 2005-07-12 |
| TW200409298A (en) | 2004-06-01 |
| US20040094781A1 (en) | 2004-05-20 |
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