WO1996017381A1 - Dispositif a semi-conducteur et son procede de production - Google Patents

Dispositif a semi-conducteur et son procede de production Download PDF

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Publication number
WO1996017381A1
WO1996017381A1 PCT/JP1995/001821 JP9501821W WO9617381A1 WO 1996017381 A1 WO1996017381 A1 WO 1996017381A1 JP 9501821 W JP9501821 W JP 9501821W WO 9617381 A1 WO9617381 A1 WO 9617381A1
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WO
WIPO (PCT)
Prior art keywords
film
semiconductor device
oxygen
lower electrode
oxidized
Prior art date
Application number
PCT/JP1995/001821
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English (en)
Japanese (ja)
Inventor
Masayuki Suzuki
Hiroshi Miki
Shinji Nishihara
Shin-Ichi Ishida
Masashi Sahara
Hiromi Abe
Hideaki Tsugane
Original Assignee
Hitachi, Ltd.
Hitachi Ulsi Engineering Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Ulsi Engineering Corp. filed Critical Hitachi, Ltd.
Publication of WO1996017381A1 publication Critical patent/WO1996017381A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Definitions

  • the present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device using a perovskite dielectric film as an insulating film for a capacitor.
  • Perovskite dielectrics represented by P ZT (P b Z r, T i, 0 3 : 0 ⁇ X ⁇ 1) are capable of polarization reversal, and in principle, the time for reading and writing information is reduced. Because it can be made equal and shorter, it is promising as a next-generation non-volatile memory that replaces EEPROM (Electrically Erasable and Programmable Read Only Memory). In addition, since the dielectric constant can be expected to be 100 times or more that of silicon dioxide, it is also expected to be used as a material for insulating capacitors of DRAM.
  • Perovskite dielectrics include several film forming methods such as sputtering, vapor deposition, sol-gel, and CVD. In any case, oxygen deficiency is likely to occur. If oxygen deficiency occurs, the leakage current increases. To prevent this, it is necessary to perform an oxidation treatment after the film formation, specifically, a heat treatment in an oxygen atmosphere. As such a heat treatment, as disclosed in Japanese Patent Application Laid-Open No. 6-135655, after forming a PZT film on a Pt film, a one-time annealing comprising an ozone atmosphere anneal and an oxygen atmosphere anneal is performed. Supply oxygen into the PZT crystal to prevent oxygen deficiency and loss of Pb A way is being considered.
  • a silicon diffusion preventing film such as TiN is used.
  • a Pt / TiN laminated film provided between a substrate and a lower electrode has been widely studied as an electrode material. Disclosure of the invention
  • the present inventor has found the following problems as a result of studying the prior art.
  • Pt and Pd are characterized by being hardly oxidized.
  • the temperature is at least 500, preferably from 600 ° C to 6550. It is desirable to perform heat treatment in a C oxygen atmosphere. Under such conditions, Pt easily permeates oxygen, and this permeation causes a problem that TiN of the PtZTiN laminated film is oxidized.
  • Pt is poorly reactive and there is no compound stable in the gas phase. Therefore, considering the application of semiconductor device manufacturing, patterning must be performed by ion milling rather than by chemical dry etching. In such ion milling, the removed Pt may adhere as foreign matter to the Si wafer, which is a dry-etched chamber processed product. Adhesion of foreign matter to the wafer reduces the reliability of the product, and adhesion of foreign matter to the chamber reduces the reproductive efficiency that requires frequent cleaning. As described above, when the thickness of the Pt film is increased, a new problem arises in that the adhesion of foreign substances due to such Pt is increased.
  • An object of the present invention is to provide a technology capable of preventing oxidation of a Si diffusion preventing film in the above-described step of heat-treating a perovskite dielectric film in an oxygen atmosphere, and reducing the thickness of a lower electrode film as much as possible. Is to provide.
  • the Berobusu chi Bok dielectric film having a composition of AB 0 3 represented by PZT or the like as the absolute ⁇ , a metal film as a lower electrode, S i on a substrate, electrically conductive typified T i N S i A diffusion barrier film, a lower electrode film typified by Pt and Pd, and a perovskite dielectric, which are sequentially laminated, and an oxidation process for adding oxygen to oxygen-deficient portions of the perovskite dielectric.
  • an electrically conductive oxygen diffusion preventing film is formed between an electrically conductive Si diffusion preventing film typified by TiN and a lower electrode film typified by Pt and Pd.
  • the electrically conductive oxygen diffusion prevention film is made of two or more solid elements, At least one of them is a component that is oxidized by the heat treatment in the oxidizing atmosphere, and at least one is a component that maintains the electrical conductivity without being oxidized by the heat treatment in the oxidizing atmosphere.
  • At least one kind of element in the electrically conductive oxygen diffusion preventing film is oxidized by the heat treatment in an oxygen atmosphere itself to capture oxygen, so that it is transferred to the Si diffusion preventing film. Diffusion of oxygen can be prevented. Therefore, even if the metal electrode film is thinned, the Si diffusion preventing film is not oxidized and becomes non-conductive. On the other hand, elements that do not oxidize maintain electrical conductivity as a simple metal.
  • the effect (3) has an effect that dirt in the dry etching chamber can be reduced.
  • the effect (3) has an effect that the production efficiency can be improved.
  • the lower electrode can be processed by another method such as jet etching or plating instead of ion milling.
  • FIG. 1 is a longitudinal sectional view showing a memory cell portion of a semiconductor device according to one embodiment of the present invention.
  • FIG. 2 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to one embodiment of the present invention.
  • FIG. 3 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to one embodiment of the present invention.
  • FIG. 4 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to one embodiment of the present invention.
  • FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.
  • FIG. 7 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.
  • FIG. 8 is a longitudinal sectional view showing a memory cell portion of a semiconductor device according to another embodiment of the present invention.
  • FIG. 1 is a longitudinal sectional view showing a memory cell portion of a semiconductor device according to an embodiment of the present invention.
  • the memory cell of the present embodiment is composed of a series circuit of an n-channel MIS transistor formed on the main surface of the semiconductor substrate and a capacitor for information sharing formed on the transistor via an insulating film.
  • 1 is a semiconductor substrate of Si single crystal
  • 2 is a p-well layer
  • 3 is a field insulating film defining an element formation region
  • a channel stopper region 4 is formed below the field insulating film 3.
  • An n-channel MIS transistor is formed in the element formation region, and the MIS transistor is composed of an n-type diffusion layer 5, which diffuses As, a gate insulating film 6, and a gate electrode 7, and one of the n-type diffusion layers 5 is a capacitor.
  • the other of the n-type diffusion layers 5 is connected to a visitor line, and the gate electrode 7 is formed integrally with the word line.
  • One side and the top of the gate electrode are covered with side walls 8.
  • Reference numeral 9 denotes an S insulating film on the main surface of the semiconductor substrate 1, a first opening 10 is formed in the insulating film 9 on the n-type diffusion layer 5, and a first layer wiring 1 formed on the insulating film 9 is formed. 1 and the n-type diffusion layer 5 are conducted through the opening 10.
  • the first layer wiring 11 is composed of a Ti film 12 for obtaining a low contact resistance, an electric conductivity Si diffusion preventing film 13 for the TiN, and a W film 14 for lowering the wiring resistance.
  • the configuration is such that the layers are sequentially stacked.
  • a second opening 16 is formed in the interlayer insulating film 15, and the electrically conductive oxygen diffuses inside the second opening 16.
  • a protection film 17 is provided. Electrically conductive oxygen diffusion preventing film 1 7 Although during formation is P t S i, by heat treatment of perovskite ⁇ body, the P t and S i 0 2.
  • Reference numeral 20 denotes a metal film lower electrode of a capacitor made of Pt
  • reference numeral 21 denotes a capacitor insulating film 21 of a PZT film which is a perovskite film.
  • the PZT film formed here has oxygen vacancies in the crystal.
  • a heat treatment was performed in an oxygen atmosphere of 600 "C10 minutes, and then the upper portion of the capacitor consisting of a stacked film of a Pt film and a TiN film was formed.
  • An electrode film 22 is formed, and 23 is a TiN film used as a mask.
  • a P-type layer 2 is formed on the main surface of the semiconductor substrate 1 by ion implantation and indentation diffusion of a p-type impurity such as B into the semiconductor substrate 1 of single crystal Si, and a field insulating film formed by selective oxidation by LOCOS method. 3 defines the element formation region.
  • the n-type impurity implanted in the region for forming the field insulating film 3 prior to the selective oxidation is diffused to form the n-type channel stopper region 4.
  • an n-channel MIS transistor is formed in this element formation region.
  • a thin oxide film serving as a gate insulating film 6 is formed on the main surface of the semiconductor substrate 1 in the element formation region by thermal oxidation, and a polycrystalline Si film or a polycrystalline Si film is formed on this oxide film.
  • a stacked film with point metal silicide is formed by CVD and patterned by photolithography to form a gate electrode.
  • the gate electrode 7 as a mask, As is ion-implanted and diffused to form the n-type diffusion layer 5.
  • Side walls 8 of SiO 2 are formed on the side and top surfaces of the gate electrode 7 by the CVD method. Figure 2 shows this exhaustion.
  • an insulating film 9 is formed by a CVD method, a first opening 10 is formed on the n-type diffusion layer 5, and a first-layer wiring 11 is formed.
  • the first layer wiring 11 is sequentially formed by sputtering the Ti film 12 with a thickness of 30 nm and the TiN electrically conductive Si diffusion preventing film 13 with a 100 nm sputtering method. Then, a 250 nm W film 14 was laminated and formed by the CVD method.
  • an interlayer insulating film 15 is formed as an interlayer insulating film 15 on the first layer wiring 11 by plasma CVD, and a second opening 16 is opened by dry etching.
  • An i film was formed and processed by dry etching, leaving a polycrystalline Si film 18 only inside the second opening 16.
  • the interlayer insulating film 15 may be planarized using an etch-back method or the like.
  • a Pt film 19 was formed on the polycrystalline Si film 18 by a sputtering method. This state is shown in FIG.
  • P t film was formed in a thickness of l O nm sputtering as the metal film lower electrode 20 of the capacitor, by dry etching using a mask S i 0 sigma film by A r and C 1 plasma, a metal lower electrode film 20 Is patterned. Since the Pt film is as thin as 10 nm in this embodiment, this etching can also be performed by jet etching. Thereafter, the Si mask was removed, and a perovskite dielectric PZT film was formed as a capacitor insulating film 21 by a 50 nm spatter method. The PZT film formed here has some oxygen vacancies in the crystal. Then, in order to replenish oxygen to the oxygen-deficient portion, a heat treatment was performed for 10 minutes in a 600 atmosphere of oxygen atmosphere.
  • a Pt film to be the upper electrode film 22 is formed by 50 ⁇ m, and a TiN film 23 to be a mask of the Pt film is formed by 100 ⁇ m sequentially by sputtering. This state is shown in FIG. Thereafter, by photolithography, the TiN film 23 is first patterned, the upper electrode film 22 is patterned using the patterned TiN film 23 as a mask, and the capacitor is patterned using the patterned upper electrode film 22 as a mask. Pattern the insulating film 21.
  • a Si film is formed as the second interlayer insulating film 24 by the CVD method.
  • the TiN film is 100 nm
  • the Ti film is 20 nm
  • Cu a first film containing 600 nm and a 60 nm-thick iN film are sequentially formed to form a second-layer metal wiring 25, and as a final protective film 26, tetraethyloxysilane (TE) is used as a source gas living body.
  • TE tetraethyloxysilane
  • OS A Si film was formed by plasma CVD using gas (organic silane), and finally the semiconductor device shown in Fig. 1 was fabricated.
  • the Pt film as the lower electrode film 20 is as thin as 10 nm, oxygen diffuses to the electrically conductive oxygen diffusion preventing film 17 during the oxidation heat treatment of the PZT film.
  • oxygen in PtSi constituting the electrically conductive oxygen diffusion preventing film 17 is oxidized to capture oxygen, diffusion of oxygen to the electrically conductive Si diffusion preventing film 13 is prevented. Can be prevented.
  • the Si diffusion prevention film 13 is oxidized. It does not become non-conductive.
  • Pt in PtSi constituting the electrically conductive oxygen diffusion preventing film 17 does not oxidize and maintains electrical conductivity as a single metal.
  • the air conductive Si diffusion preventing film 13 of the TiN film of the first layer wiring 11 can prevent the mutual diffusion of Pt and Si during the oxidation heat treatment. No degradation occurs.
  • the Pt film serving as the lower electrode film 20 is thin, the Pt residue when the lower electrode film 20 is applied is reduced, the contamination in the dry etching chamber is reduced, and the production efficiency is improved.
  • the step formed by the lower electrode film 20 is reduced, thereby facilitating the subsequent film forming process and improving the accuracy.
  • the PZT film of the perovskite dielectric film is formed by the sputtering method.
  • the present invention can be applied to other forming methods such as an evaporation method, a CVD method, and a sol-gel method. It is also effective when using another perovskite dielectric film such as another perovskite dielectric film such as BST or PTO.
  • the polycrystalline Si film 18 was reacted with the Pt film 19, but the polycrystalline Si film 18 may be left without reacting. In this case, the remaining polycrystalline Si film 18 may be made conductive by, for example, doping P (phosphorus).
  • Example 2
  • FIG. 8 is a longitudinal sectional view showing a memory cell portion of a semiconductor device according to another embodiment of the present invention.
  • the electrically conductive oxygen diffusion preventing film is formed by plating.
  • FIG. 8 The manufacturing process of the semiconductor device shown in FIG. 8 will be described with reference to FIG. 2, FIG. 6, and FIG.
  • a p-type impurity such as B is ion-injected into a semiconductor substrate 1 of single-crystal Si, and p- ⁇ 2 is formed on the main surface of the semiconductor substrate 1 by indentation diffusion.
  • An element formation region is defined by the field insulating film 3.
  • an n-channel MIS transistor is formed in this element formation region.
  • a thin oxide film serving as a gate insulating film 6 is formed on the main surface of the semiconductor substrate 1 in the element formation region by thermal oxidation, and a polycrystalline Si film or polycrystalline Si is formed on this oxide film with a high melting point.
  • a laminated film with a metal silicide is formed by a CVD method, and is patterned by photolithography to form a gate electrode 7.
  • As is ion-implanted and diffused using the gate electrode 7 as a mask to form an n-type diffusion layer 5.
  • the side and top surfaces of the gate electrode 7 is Sai Doworu 8 S i 0 sigma by CVD covers. This state is shown in FIG.
  • an insulating film 9 is formed by a CVD method, a first opening 10 is formed on the n-type diffusion layer 5, and a first-layer wiring 11 is formed.
  • the first layer wiring 11 has a Ti film 12 with a thickness of 30 nm and a TiN electrically conductive Si diffusion preventing film 13 with a lOO nm sputtering method sequentially. Ridge layer Furthermore, a W film 14 of 250 nm was formed by CVD and formed.
  • the unreacted Pt film 29 is removed with aqua regia.
  • An electrically conductive oxygen diffusion preventing film 27 was formed.
  • the P t S i is P t and S i 0 2 next by a heat treatment carried out after, but maintains the O connection electrical conductivity to the P t, as the electrode of the capacitor, there is a rough like surface It is desirable to perform some surface treatment.
  • the lower electrode film 30 is formed by plating.
  • a PZT film of a perovskite dielectric was formed as a capacitor insulating film 21 by a 50 nm sputtering method.
  • the PZT film formed here has some oxygen vacancies in the crystal. Therefore, oxygen is The heat treatment in an oxygen atmosphere of 600 was performed for 10 minutes in order to replenish.
  • a Pt film serving as the upper electrode film 22 is formed at 50 ⁇ m, and a TiN film 23 serving as a mask for the Pt film is formed successively by sputtering to a thickness of 100 nm. This state is shown in FIG. Thereafter, the TiN film 23 is first patterned by photolithography, the upper electrode film 22 is patterned using the patterned TiN film 23 as a mask, and the capacitor insulation is performed using the patterned upper electrode film 22 as a mask. Pattern the membrane 21.
  • a SiO 2 film is formed as a second interlayer insulating film 24 by a CVD method.
  • a TiN film is 100 nm
  • a Ti film is 20 nm
  • Cu S
  • the second layer metal wiring 25 is formed by sequentially laminating an A1 film containing i at 600 nm and a TiN film at 60 nm.
  • a final protective film 26 tetraethoxysilane (TE) is mainly used as a source gas.
  • TE tetraethoxysilane
  • OS A SiO 2 film was formed by plasma CVD using gas (organic silane), and finally the semiconductor device shown in FIG. 8 was fabricated.
  • the Pt film serving as the lower electrode film 30 since the Pt film serving as the lower electrode film 30 is formed thin by the technique, oxygen diffuses to the electrically conductive oxygen diffusion preventing film 27 during the oxidation heat treatment of the PZT film. However, oxygen is trapped by oxidizing Si in the PtSi constituting the electrically conductive oxygen diffusion preventing film 27, so that diffusion of oxygen to the electrically conductive Si diffusion preventing film 13 is prevented. it can. Therefore, even if the lower electrode film 30 is formed thin, the Si diffusion preventing film 13 is not oxidized and becomes non-conductive. In addition, Pt in PtSi constituting the electrically conductive oxygen diffusion preventing film 27 does not oxidize and maintains electrical conductivity as a single metal.
  • the electrical conductivity of the TiN film of the first layer wiring 11 Si diffusion preventing film 13 Accordingly, during the oxidation heat treatment, the interdiffusion of Pt and Si can be prevented, so that the element does not deteriorate.
  • the Pt film serving as the lower electrode film 30 is thin, the Pt residual method at the time of applying the lower electrode film 30 is reduced, contamination in the dry etching chamber is reduced, and production efficiency is improved.
  • the step formed by the lower electrode film 30 is reduced, so that the subsequent film forming process is facilitated and the accuracy is improved.
  • the PZT film of the perovskite dielectric film is formed by the sputtering method.
  • the present invention can be applied to other forming methods such as an evaporation method, a CVD method, and a sol-gel method.
  • the present invention is also effective when other perovskite dielectric films such as BST and PTO are used.
  • ⁇ ⁇ is used as the perovskite dielectric
  • Pt or Pd is used as the lower electrode material
  • PtSi is used as the oxygen diffusion preventing film
  • W / TiN is used as the Si diffusion preventing film.
  • the necessary condition of the present invention is to pass through the oxidation condition, the lower electrode material and the oxygen diffusion preventing film as described below.
  • materials that are the least oxidizable among the elements A, A ', B, B', etc., which constitute the perovskite dielectric of AB O a composition in other words, the element with the smallest oxide generation energy is A,
  • C is the element that forms the oxygen diffusion prevention film, and the element that has the lowest oxide generation energy is D, and the element that forms the largest oxygen diffusion energy is E.
  • a and E of each constituent element are oxidized, and C and D are not oxidized.
  • the material and oxidation conditions are selected as in these conditions.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé amélioré de production, à efficacité augmentée, d'un dispositif à semi-conducteur, au moyen d'une couche diélectrique perovskite. Une couche barrière de diffusion de Si, telle que du TiN, une couche électrode inférieure, telle que du Pt, et une couche isolante constituée d'un diélectrique perovskite sont déposées l'une après l'autre sur un substrate de Si. Entre la couche barrière de diffusion de Si et la couche électrode inférieure, est formée une barrière de diffusion d'oxygène, laquelle contient un composant oxydable par application d'oxygène sur des parties déficientes en oxygène du diélectrique perovskite et un composant non oxydable qui maintient la conductivité électrique. Dans la barrière de diffusion d'oxygène, le composant non oxydable est un métal simple conducteur qui maintient la conductivité électrique, tandis que le composant oxydable est oxydé par traitement thermique dans une atmosphère d'oxydation, c'est-à-dire qu'il capte l'oxygène et empêche ainsi la diffusion de celui-ci dans la couche barrière de diffusion de Si, et donc qu'il empêche l'oxydation de celle-ci. En conséquence, étant donnée que l'épaisseur de la couche électrode inférieure peut être réduite, il est possible d'améliorer la marge d'usinage ainsi que la fiabilité et la productivité d'un condensateur.
PCT/JP1995/001821 1994-11-28 1995-09-13 Dispositif a semi-conducteur et son procede de production WO1996017381A1 (fr)

Applications Claiming Priority (2)

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JP29273494 1994-11-28
JP6/292734 1994-11-28

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0847083A2 (fr) * 1996-12-04 1998-06-10 Samsung Electronics Co., Ltd. Méthode de fabrication d'un condensateur pour un dispositif à semi-conducteur
US6001660A (en) * 1997-04-17 1999-12-14 Samsung Electronics Co., Ltd. Methods of forming integrated circuit capacitors using metal reflow techniques
US6075264A (en) * 1999-01-25 2000-06-13 Samsung Electronics Co., Ltd. Structure of a ferroelectric memory cell and method of fabricating it
US6130124A (en) * 1996-12-04 2000-10-10 Samsung Electronics Co., Ltd. Methods of forming capacitor electrodes having reduced susceptibility to oxidation
WO2008075641A1 (fr) * 2006-12-20 2008-06-26 Ulvac, Inc. Procédé de formation d'un film multicouche et appareil de formation d'un film multicouche

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05299601A (ja) * 1992-02-20 1993-11-12 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH06140570A (ja) * 1992-10-26 1994-05-20 Fujitsu Ltd 高誘電率誘電体薄膜を有する電子部品とその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05299601A (ja) * 1992-02-20 1993-11-12 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH06140570A (ja) * 1992-10-26 1994-05-20 Fujitsu Ltd 高誘電率誘電体薄膜を有する電子部品とその製造方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0847083A2 (fr) * 1996-12-04 1998-06-10 Samsung Electronics Co., Ltd. Méthode de fabrication d'un condensateur pour un dispositif à semi-conducteur
EP0847083A3 (fr) * 1996-12-04 1998-12-23 Samsung Electronics Co., Ltd. Méthode de fabrication d'un condensateur pour un dispositif à semi-conducteur
US6130124A (en) * 1996-12-04 2000-10-10 Samsung Electronics Co., Ltd. Methods of forming capacitor electrodes having reduced susceptibility to oxidation
US6001660A (en) * 1997-04-17 1999-12-14 Samsung Electronics Co., Ltd. Methods of forming integrated circuit capacitors using metal reflow techniques
US6075264A (en) * 1999-01-25 2000-06-13 Samsung Electronics Co., Ltd. Structure of a ferroelectric memory cell and method of fabricating it
US6337216B1 (en) 1999-01-25 2002-01-08 Samsung Electronics Co., Ltd. Methods of forming ferroelectric memory cells
WO2008075641A1 (fr) * 2006-12-20 2008-06-26 Ulvac, Inc. Procédé de formation d'un film multicouche et appareil de formation d'un film multicouche
JPWO2008075641A1 (ja) * 2006-12-20 2010-04-08 株式会社アルバック 多層膜形成方法及び多層膜形成装置

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