Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/06—Synchronising arrangements
  • H04J3/0635—Clock or time synchronisation in a network
  • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
  • G06F1/10—Distribution of clock signals, e.g. skew
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/06—Synchronising arrangements
  • H04J3/0635—Clock or time synchronisation in a network
  • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging

Definitions

• the present invention relates to a method and system for automatic compensation of line delay in a clock distribution system in which a clock generator distributes a master clock signal on clock path to a group of decentralized clock signal buffers.
• a digital switching exchange there are a number of decentralized computer units which communicate with one another on a synchronous data transmission bus.
• computer units connected to it must be synchronized with regard to one another by timing signals.
• the aim is to distribute timing signals so that the clock signals arrive at each computer unit with substantially the same phase, or so that the clock signals have a desired phase difference.
• a centralized clock signal generator produces a so-called master clock signal which is distributed via one or more cabling routes to clock signal buffers which handle the distribution of clock signals to one or more decentralized computer units.
• Clock signal buffers on the same clock distribution path are located at different line lengths from the clock signal generator that distributes the clock signal.
• the phase of the output clock pulse must be adjusted in each buffer so that it compensates the delay between the buffer and the clock signal generator which distributes a master clock signal to the buffer, which delay is caused by a specific cable length between them.
• the clock signals received by different computers are with the same phase, or a desired time difference has been set between them.
• the line delay does not have to be compensated in the clock signal distribution, if lines of fixed length are used between the clock signal buffers and the clock signal generator.
• a manual method represents one way for compensating the clock phase.
• a phase preset is manually set for each clock signal buffer, the value of which depends on the length of the line section between the generator transmitting the master clock signal, and the buffer.
• the buffer is informed of the required buffer-specific phase preset value by, for example, back end terminals or bridge connections.
• a manual setting of a phase preset value like this is trying, and a high possibility exists for erroneous settings that are difficult to notice, especially if the number of required phase preset values is large for reasons of accuracy.
• Another known method for carrying out compensation is to carry it out at the master clock end of the clock path. Such a system is described in the U.S. Patent 5 298 866.
• a separate return path is connected to the clock distribution path just prior to the buffer.
• the clock distribution circuit includes a loop comprising a delay element, which loop is also fed with a clock signal, and thus the delayed clock signal acts as a reference signal.
• the logic compares the phase of return signals from the various clock distribution paths to the phase of the reference signal, and dynamically adjusts the phase of each outward clock signal so that it matches the phase of the reference signal. This method is restricted to be utilized in a star-like clock distribution system in which clock paths are of different lengths.
• each module comprises a PLL clock signal generator which is locked onto the same, common time reference.
• the arrangement goes as follows : the master clock at the other end of the path transmits clock pulses to the down signal path. Parallel to the path, there is a return signal path. The path ends that are far from the master clock are connected to each other, and the end of the return path at the master clock end is so terminated that no reflections take place.
• Each module is connected to the down path and the return path at the- same point .
• the module detects the edge of the pulse upon its arrival at the module.
• the pulse proceeds to the end of the down path, and returns on the return path towards the master clock.
• the module detects the edge of the pulse upon its arrival at the module.
• the module knows the exact time interval between the outward and return signals. One half of this time corresponds to the distance in time at which the module is located from the end of the paths.
• each module knows the distance in time at which it is located from the end of the paths.
• the modules As a new clock pulse passes each module, the modules, as a response to the passing, generate a synchronizing pulse to their respective clock distribution circuits after exactly one half of the time measured by said module.
• each module generates a synchronizing pulse at exactly the same moment of time. This way, the clock of each module is locked onto the same time reference, i.e. the moment at which the clock pulse from the master clock has proceeded to the end of the down path.
• the module measures the time interval between the down and return pulses, and as the next clock pulse has bypassed the module after one half of said time, generates yet another synchronizing pulse.
• the aforementioned is repeated continuously, and the synchronizing pulse of the module clock circuit is always updated when the pulse from the master clock reaches the end of the down path.
• each module measures the propagation delay of the master clock pulse between the module and the end of the clock path.
• the delay between the master clock and the module is not established, and thus the phase of the master clock pulse is not found out, i.e. the moment at which the master clock transmits the clock pulse is not detected.
• the time of the module is exactly the same as that of the master clock without the delay, or the time of the master clock added by an arbitrary delay. If the time of the module is the same as that of the master clock, the module clock should anticipate the arrival of the pulse from the master clock by the delay caused by the distance between the module and the master clock. This is not possible by the method of said patent .
• the object of the present invention is to provide a method by which the actual delay caused to the clock signal by the line between the master clock generator and the buffer can be measured in a decentralized clock distribution system, and automatically compensate the delay in each clock signal buffer accordingly, so that all buffers transmit a clock signal with the same phase or of a desired phase relationship with respect to the other buffers.
• each buffer is connected to a line which is at least the length of a clock path, the beginning of which line is close to the master clock generator of the clock path, - each buffer independently measures a variable which is proportional to the length of the line section between it and the beginning of the line, and on the basis of that determines the propagation • time of the signal on that section of the line, and - each buffer sets a phase preset value for the phase of the outward clock signal, which preset value corresponds to said propagation time.
• the variable to be measured may be the impedance of the line section, on the basis of which impedance the buffer measures the propagation time of the signal, or the variable is the phase difference on the cable between the measuring signal travelling from the buffer to the direction of the master clock generator and a measuring signal returning back from there.
• the line can therefore be a single line, in which case the returning measuring signal is a reflected signal, or the line can be a loop.
• clock signal buffer In the method of the invention, all clock signal buffer set their respective phase preset values which depend on the line length. Thus, the phase preset value does not have to be manually set, and the lengths of the lines to be used can be freely chosen.
• the expression clock signal buffer derives from the method of producing a clock pulse from an incoming clock signal by buffering, but the invention is applicable to all techniques that generate an output clock signal from an incoming clock signal by way of, for example, a phase- locked loop.
• the term buffer is here used in an exemplary sense without being restricted in any way to the buffering technology of this invention.
• the present invention makes it possible to set the phase preset value very accurately, because the setting is based on a (system-specific) measurement result. What is later set forth in the attached claims is characteristic to the system of the invention and other preferred embodiments.
• a system embodying the method of the invention for an automatic compensation of line delay in a clock signal distribution is shown in the attached figure which is an exemplary illustration of a clock signal generator and a number of clock buffers PI ...PN of a Nokia DX 200 digital switching exchange, and a clock path cabling C between the generator and buffers.
• the clock path cabling begins at a clock signal generator 1 and ends at the last buffer PN on the path.
• the clock signal generator 1 distributes, for example, master clock signals of 16,384 MHz and 8 kHz to clock signal buffers P1...PN on one or more clock paths 2.
• the clock signal buffer receives the master clock signals of 16,384 MHz and 8 kHz transmitted by the clock signal generator 1, and, by means of them, produces 8,192 MHz and 8 kHz output clock signals of its own for buffers using the exchange clocks.
• the buffers produce their output clock signals from the incoming clock signal by means of buffering or by re-generating the clock signal by a phase-locked loop.
• the object is to transmit the clock signals from all the buffers PI ...PN to the buffers using the exchange clocks with as much the same phase as possible regardless of the propagation delay caused by the clock path cabling, the delay being usually in the region of 5-6 ns/m in the signal received by the clock signal buffer.
• a desired phase difference can be achieved between some or all of the outward clock signals from the buffers.
• the clock signal buffer compensates the line delay by setting a suitable phase preset value for its output clock signal.
• the value of the necessary phase preset is determined, according to the primary embodiment of the invention, by measuring the propagation time of a separate measuring signal in the clock path cabling. Alternatively, the value of the phase preset can be determined by, for example, measurements of the cable resistance, or by another suitable method.
• the clock signal buffers comprise a clock transmitter 8 for carrying out measurements.
• the clock transmitter 8 of the buffer PN at the end of the clock path is advantageously connected to a measuring loop 3 on the clock path cabling, to which measuring loop 3 it transmits an 8 kHz measuring signal.
• Another, existing cable in the system, a clock path cable, for example, can serve as a measuring loop.
• a single measuring cable can be employed, so that instead of the returning signal from the other loop branch, a reflected echo signal is monitored.
• Each buffer PI ...PN receives the signal that travels to the end B of the measuring loop as well as the measuring signal returning from it. The signal on the measuring cable is thus fed through all the buffers P1...PN to the end B of the measuring loop, which end B is at the clock signal generator 1, from which it is re-connected to the beginning (A) of the measuring loop through all the buffers (P1...PN) .
• a signal travelling to the end B of the measuring loop causes at gate 5 of each buffer an MSTART pulse which is fed to a counter 4.
• a signal returning to the beginning A of the measuring loop causes at gate 6 an MSTOP pulse which is also fed to the counter 4.
• the counter 4 determines the phase difference between the signals MSTART and MSTOP as seconds by counting, during the time interval between the rising edges of the measuring signals MSTART and MSTOP, the 65,536 MHz clock signal pulses C K produced at each buffer.
• the measured phase difference corresponds to the propagation time of the measuring signal from the measuring buffer to the end of the measuring loop and back from there to the measuring buffer.
• Each unit sets the phase preset value of the outward clock signal to one half of the measured propagation time of the measuring signal . This corresponds to the time that elapses as the output signal from the clock signal generator travels from the beginning of the clock path to the clock buffer.
• the computer 7 in the clock signal buffer reads the result of the phase difference measurement from the counter 4, and sets a phase preset value corresponding to said result for the divider chain that produces output clock signals from the buffer.
• the phase preset value can be set within the accuracy of 15 ns for each buffer. Accuracy can be increased by increasing the clock signal frequency used in the counter.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Electric Clocks (AREA)

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• 1994
  • 1994-07-13 FI FI943341A patent/FI101833B1/fi active
• 1995
  • 1995-07-10 US US08/782,925 patent/US5812835A/en not_active Expired - Fee Related
  • 1995-07-10 EP EP95924346A patent/EP0770237B1/en not_active Expired - Lifetime
  • 1995-07-10 JP JP8504734A patent/JP2889701B2/ja not_active Expired - Fee Related
  • 1995-07-10 AT AT95924346T patent/ATE214170T1/de not_active IP Right Cessation
  • 1995-07-10 AU AU28892/95A patent/AU693231B2/en not_active Ceased
  • 1995-07-10 DE DE69525749T patent/DE69525749T2/de not_active Expired - Fee Related
  • 1995-07-10 CN CN95194603.XA patent/CN1095109C/zh not_active Expired - Fee Related
  • 1995-07-10 WO PCT/FI1995/000400 patent/WO1996002877A2/en active IP Right Grant

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