WO1993006620A1 - Solder bump fabrication method and solder bumps formed thereby - Google Patents

Solder bump fabrication method and solder bumps formed thereby Download PDF

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Publication number
WO1993006620A1
WO1993006620A1 PCT/US1992/007722 US9207722W WO9306620A1 WO 1993006620 A1 WO1993006620 A1 WO 1993006620A1 US 9207722 W US9207722 W US 9207722W WO 9306620 A1 WO9306620 A1 WO 9306620A1
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WO
WIPO (PCT)
Prior art keywords
solder
contact pads
bump
under
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1992/007722
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English (en)
French (fr)
Inventor
Edward K. Yung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MCNC
Original Assignee
MCNC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MCNC filed Critical MCNC
Priority to EP92919808A priority Critical patent/EP0603296B1/en
Priority to CA002116766A priority patent/CA2116766C/en
Priority to KR1019940700820A priority patent/KR0186061B1/ko
Priority to DE69221627T priority patent/DE69221627T2/de
Publication of WO1993006620A1 publication Critical patent/WO1993006620A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465—Application of solder
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01257—Changing the shapes of bumps by reflowing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01261—Chemical or physical modification, e.g. by sintering or anodisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H10W72/01953—Changing the shapes of bond pads by etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/234—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing

Definitions

  • This invention relates to microelectronic device manufacturing methods and more particularly to methods of forming electrical and mechanical connections for a microelectronic substrate, and the connections so formed.
  • VLSI very large scale integration
  • solder bumps solder balls or solder bumps for electrical interconnection to other microelectronic devices.
  • VLSI very large scale integration
  • This connection technology is also referred to as "Controlled Collapse Chip Connection - C4" or “flip-chip” technology, and will be referred to herein as "solder bumps”.
  • solder bumps are formed by evaporation through openings in a shadow mask which is clamped to an integrated circuit wafer.
  • Solder bump technology based on an electroplating process has also been actively pursued, particularly for larger substrates and smaller bumps.
  • an "under-bump metallurgy" (UBM) is deposited on a microelectronic substrate having contact pads thereon, typically by evaporation or sputtering.
  • a continuous under-bump metallurgy film is typically provided on the pads and on the substrate between the pads, in order to allow current flow during solder plating.
  • the sites of the solder bumps are photolithographically patterned, by depositing a thick layer of photoresist on the under- bump metallurgy and patterning the photoresist to expose the under-bump metallurgy over the contact pads. Solder pads are then formed on the exposed areas of the under-bump metallurgy, over the contact pads, by pattern electroplating. The plated solder accumulates in the cavities of the photoresist, over the contact pads. Then, the under-bump metallurgy between the plated solder pads is etched, using the solder as an etch mask, to break the electrical connection between the solder bumps.
  • the photolithographic patterning and under-bump metallurgy etching steps define the geometry of the under-bump metallurgy at the base of the solder bump, between the solder bump and the contact pad.
  • Solder bump fabrication methods are described in U.S. Patents 4,950,623 to Dishon, assigned to the assignee of the present invention; 4,940,181 to Juskey, Jr. et al.; and 4,763,829 to Sherry.
  • the base may be reduced due to at least two steps in the above described process.
  • a dry thick film photoresist such as du Pont RISTON ® photoresist
  • multiple coatings of liquid photoresist is used, in order to accumulate sufficient volume of plated solder. Thicknesses on the order of tens of microns (for example 50 microns) are used.
  • the thick film photoresist must be accurately patterned over the contact pads, without misalignment or distortion.
  • the resultant solder bump often does not cover the entire contact pad.
  • the second major factor which may reduce the solder bump base is undercutting during chemical etching of the under-bump metallurgy.
  • the under-bump metallurgy is typically etched, between the solder bumps, in order to break the electrical connections therebetween.
  • overetching typically needs to be practiced, because etching frequently does not proceed uniformly across the substrate surface.
  • this overetching typically undercuts the under-bump metallurgy between the solder bump and the contact pad, which reduces the solder bump base.
  • solder bump connection is thereby degraded.
  • the under-bump metallurgy layer between the solder bump and contact pad is converted to an intermetallic of the solder and the under-bump metallurgy, prior to etching the under-bump metallurgy.
  • the under-bump metallurgy includes a top layer of copper, and lead-tin solder is used, substantially all of the top copper layer is converted to an intermetallic of copper and tin.
  • the intermetallic layer is resistant to etchants which are used to etch the under-bump metallurgy.
  • the under-bump metallurgy may therefore be removed between the contact pads, while preserving the intermetallic layer at the base of the solder bump.
  • the invention also reduces misalignment between the solder pads and its underlying contact pads, and tolerates distortion in patterning the solder accumulation layer.
  • a continuous under- bump metallurgy is formed on the contact pads and on the microelectronic substrate between the contact pads.
  • Solder dams are then formed on the under-bump metallurgy between the contact pads such that the solder dams expose the under-bump metallurgy over the contact pads.
  • the exposed under-bump metallurgy over the contact pads define the location of the solder bump base. During reflow, the solder will retract or spread to these areas.
  • solder dams also referred to as solder stops, are preferably formed from a thin film layer (on the order of 1 micron or less) such as a thin film of chromium (on the order of 1500A thick) , which adheres well to the under-bump metallurgy.
  • the solder dams are precisely aligned to the underlying contact pads using known integrated circuit photolithography.
  • the solder dams are preferably patterned using the lift-off technique. Other photolithographic techniques may be used to pattern the solder dams.
  • Solder accumulation regions are then formed on the solder dams. These regions, which may be thick film (on the order of 50 microns) photoresist regions, need only accumulate solder volume. They need not be used for alignment purposes, because the solder dams provide precise alignment. Accordingly, misalignment and distortion of the thick film solder accumulation regions will not reduce the base of the solder bump over the contact pads. Solder pads are then electroplated onto the substrate over the contact pads, on the areas of the under-bump metallurgy which are exposed by the solder dams and solder accumulation regions. The solder accumulation regions may then be removed.
  • the solder is reflowed (melted) to form a solder bump having an intermetallic layer of the solder and the under-bump metallurgy at the base of the solder bump adjacent the contact pad.
  • the solder dams prevent lateral spread and bridging of the solder, and control the size of the bump base.
  • solder dams and under-bump metallurgy are then etched to isolate the solder bumps, using at least one etchant which etches the intermetallic layer more slowly than the solder bumps and under-bump metallurgy. Since the intermetallic has been formed at the base of the solder bumps, the bumps are relatively unaffected by the etchant.
  • a mixture of ammonium hydroxide with trace amounts of hydrogen peroxide may be used to etch copper, and a hydrochloric acid based etchant may be used to etch chromium. Neither of these etchants is effective against the copper/tin intermetallic.
  • the base of the solder bumps formed according to the present invention is not reduced by under-bump metallurgy etching or solder pad misalignment/distortion. By preserving the base geometry, mechanical and electrical reliability is enhanced.
  • the intermetallic layer formed at the base of each solder bump extends beyond the bump to form a lip around the base of the solder bump.
  • This lip provides extra protection for the edge of the solder bump and the edge of the contact pad underneath the solder bump. Accordingly, the invention produces a new profile of solder bump, which improves mechanical and electrical reliability.
  • Figures 1-5 illustrate cross-sectional views of a microelectronic substrate during fabrication of solder bumps thereon according to the present invention.
  • Figure 6 is a scanning electron microscope photograph of a solder bump formed according to the present invention. Detailed Description of a Preferred Embodiment
  • microelectronic substrate 10 having a plurality of contact pads 12 thereon.
  • microelectronic substrate 10 may be an integrated circuit chip, a circuit board or microelectronic packaging substrate, or any other substrate which requires electrical and mechanical connection.
  • Contact pads 12 are formed on substrate 10 using well known techniques which need not be described herein.
  • the contact pads are typically aluminum for integrated circuit chips, although other metals and metal composites may also be used for integrated circuit chips and other substrates.
  • a passivating dielectric 14 is formed on the substrate 10 and patterned to expose the contact pads 12, using conventional plasma or reactive ion etching or other well known patterning techniques.
  • a continuous under- bump metallurgy 16 is then formed on the substrate over the contact pads 12 and between the contact pads 12.
  • the under-bump metallurgy 16 typically contains a (bottom) chromium layer (about lOOOA thick) adjacent substrate 10 and pads 12, which functions as an adhesion layer and diffusion barrier for the under-bump metallurgy.
  • a top copper layer (about 1 micron thick) is typically provided to act as a solderable metal, and a phased chromium/copper layer (about lOOOA thick) is formed between the chromium and copper layers.
  • the under-bump metallurgy may be formed by conventional thin film deposition techniques such as evaporation or sputtering, and need not be described further herein.
  • solder dam or solder stop layer 18 is formed on the under-bump metallurgy layer 16 between the contact pads 10, exposing the under-bump metallurgy layer over the pads 12.
  • Solder dam layer 18 is preferably a thin film, which does not wet with solder. Chromium or titanium solder dams on the order of 1500A thick, may be used. Solder dam layer 18 is preferably formed by depositing a continuous solder dam layer 18 and patterning using lift-off or etch techniques. The thin film may be patterned with reduced misalignment and distortion, compared to thick film photoresist, by using integrated circuit photolithography, because of reduced light scattering, better adhesion and more precise developing.
  • solder accumulation regions 28 are formed on solder dams 18. These regions may be thick film photoresist. Since solder accumulation regions are used to accumulate solder volume, and need not be used for alignment relative to contact pads 12, their imprecise alignment and distorted shape will not reduce the base of the solder bumps.
  • solder pads 20 are then formed on substrate 10, typically by electroplating. Volume is acquired by filling the spaces in solder accumulation regions 28 during plating. The solder pads 20 may be confined within the gaps in the solder dam layer 18 or may be allowed to extend over the solder dams, as is illustrated in Figure 3. The solder accumulation regions 28 may then be removed.
  • solder pads 20 are reflowed prior to removing the under-bump metallurgy layer 16 between the contact pads 12, to form an intermetallic layer 22 at the base of each solder bump 24.
  • the topmost component of the under-bump metallurgy layer is copper (about 1 micron thick) and conventional lead-tin solder (5 weight percent tin) is used, the intermetallic 22 which forms is Cu3Sn. It will be understood by those having skill in the art that a thin layer of the under-bump metallurgy 16, typically the bottom chromium layer and the phased chromium-copper layer (not shown in Figure 4) may remain on contact pad 12 between the intermetallic layer 22 and contact pad 12.
  • reflow preferably takes place for 1-2 minutes above the melting point of the solder.
  • the unconverted copper in the phased chromium-copper region prevents detachment of the solder bumps from the chromium adhesion layer, and thereby enhances structural integrity.
  • solder dams 18 prevent lateral spread and bridging of the solder and thereby control the size of the solder bump base.
  • Reflow may be performed in air or in an inert ambient such as nitrogen, typically with flux applied, or in a reducing ambient such as hydrogen, without flux.
  • flux residues if present, should be cleaned prior to etching the solder dam 18 and the under-bump metallurgy 16.
  • each bump includes a lip or ridge 26 which typically extends several microns from the bump.
  • This lip or ridge may be used to identify solder bumps formed according to the present invention, because lateral reaction with the under-bump metallurgy cannot take place if all under-bump metallurgy between the contact pads is removed prior to reflow.
  • This lip or ridge 26 also provides an added degree of protection for the base of the solder bump. An improved performance solder bump is thereby provided.
  • solder dam 18 and the under-bump metallurgy 16 between the contact pads 12 are removed, while preserving the base of the reflowed solder bumps 24. Since the top copper layer of the under-bump metallurgy between solder bump 24 and contact pad 12 has been converted into an intermetallic layer, the solder dams and the remaining under-bump metallurgy between contact pads 12 may be removed, without substantially removing the intermetallic.
  • An etchant or etchants are used which etch the intermetallic 22 much more slowly than solder dam 18 and under-bump metallurgy 16. Preferably, the etchants do not etch the intermetallic 22 while removing solder dams 18 and intermetallic 22.
  • a hydrochloric acid based etchant such as Transene CRE473 is an effective etchant, and a mixture of ammonium hydroxide and a trace amount of hydrogen peroxide is an effective copper etchant.
  • Contact to the metal surface in the substrate with a zinc rod may be required to initiate etching of chromium.
  • a mixture of ammonium hydroxide and hydrogen peroxide typically higher peroxide concentrations than in the copper etchant
  • Multiple etch cycles may be needed to remove the phased chromium copper layer and the bottom chromium layer.
  • etchants are effective against the copper/tin intermetallic and neither of these etchants attacks solder to a detectable extent. It will be understood by those having skill in the art that during copper etching, the device may be left in the etchant for as long as necessary to completely remove the copper between the bumps. It will also be understood by those having skill in the art that other etchants may be used, and other removal processes may be used.
  • solder bump fabrication process is provided. Imperfections in photolithographic processing of thick film photoresists also do not degrade alignment. Moreover, undercutting of the solder bump base during under-bump metallurgy etching is substantially reduced or eliminated. The base geometry of the solder bump is therefore preserved. In fact, the process preferably forms a lip at the base of the solder bump to further protect the solder bump, and enhance electrical and mechanical reliability.
  • Figure 6 is a scanning electron microscope photograph of a solder bump formed according to the present invention, illustrating solder bump 24, lip 26 and substrate 10.
  • reduced bump base undercutting may be obtained with the present invention, independent of misalignment/distortion reduction, by reflowing the solder prior to removing the under-bump metallurgy between the contact pads.
  • the designed bump base may be substantially larger than the contact pads, so that alignment of the solder bump to the contact pads is relatively unimportant. Misalignment or distortion of the solder bump relative to the contact pads may be tolerated.
  • the under-bump metallurgy may contain the same bottom chromium layer, phased chromium/copper layer and top copper layer described above. However, a second chromium layer is added on the top copper layer.
  • a solder accumulation layer for example thick film photoresist, is formed and patterned as described above. The patterned solder dam layer described above is not formed.
  • the second chromium layer is then removed in the cavities of the solder accumulation layer, and solder is plated as already described. After removing the solder accumulation layer, the solder is reflowed to form an intermetallic and protect the bump base as already described.
  • the second chromium layer between the contact pads prevents the reflowed solder from bridging.
  • the second chromium layer may be misaligned relative to the contact pads, but this misalignment may be relatively unimportant in view of the substrate design.
  • the base of the solder bump is still protected during etching of the under-bump metallurgy by reflowing prior to removing the under-bump metallurgy between the contact pads.

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Ceramic Products (AREA)
  • Arc Welding In General (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/US1992/007722 1991-09-13 1992-09-11 Solder bump fabrication method and solder bumps formed thereby Ceased WO1993006620A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP92919808A EP0603296B1 (en) 1991-09-13 1992-09-11 Solder bump fabrication method and solder bumps formed thereby
CA002116766A CA2116766C (en) 1991-09-13 1992-09-11 Solder bump fabrication method and solder bumps formed thereby
KR1019940700820A KR0186061B1 (ko) 1991-09-13 1992-09-11 땜납 돌출전극 제조방법과 상호연결시스템
DE69221627T DE69221627T2 (de) 1991-09-13 1992-09-11 Verfahren zum herstellen von löthöckern und löthöcker so hergestellt.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US759,450 1991-09-13
US07/759,450 US5162257A (en) 1991-09-13 1991-09-13 Solder bump fabrication method

Publications (1)

Publication Number Publication Date
WO1993006620A1 true WO1993006620A1 (en) 1993-04-01

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ID=25055684

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Application Number Title Priority Date Filing Date
PCT/US1992/007722 Ceased WO1993006620A1 (en) 1991-09-13 1992-09-11 Solder bump fabrication method and solder bumps formed thereby

Country Status (10)

Country Link
US (2) US5162257A (https=)
EP (1) EP0603296B1 (https=)
JP (1) JP2842692B2 (https=)
KR (1) KR0186061B1 (https=)
AT (1) ATE156935T1 (https=)
CA (1) CA2116766C (https=)
DE (1) DE69221627T2 (https=)
ES (1) ES2106194T3 (https=)
TW (1) TW200417B (https=)
WO (1) WO1993006620A1 (https=)

Families Citing this family (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950001962A (ko) * 1993-06-30 1995-01-04 김광호 반도체 칩 범프
US5366140A (en) * 1993-09-30 1994-11-22 Minnesota Mining And Manufacturing Company Patterned array of uniform metal microbeads
US5442852A (en) * 1993-10-26 1995-08-22 Pacific Microelectronics Corporation Method of fabricating solder ball array
US5396702A (en) * 1993-12-15 1995-03-14 At&T Corp. Method for forming solder bumps on a substrate using an electrodeposition technique
US5532550A (en) * 1993-12-30 1996-07-02 Adler; Robert Organic based led display matrix
US5665639A (en) * 1994-02-23 1997-09-09 Cypress Semiconductor Corp. Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal
US5470787A (en) * 1994-05-02 1995-11-28 Motorola, Inc. Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
US5539153A (en) * 1994-08-08 1996-07-23 Hewlett-Packard Company Method of bumping substrates by contained paste deposition
TW253856B (en) * 1994-12-13 1995-08-11 At & T Corp Method of solder bonding, and article produced by the method
ATE210895T1 (de) * 1995-03-20 2001-12-15 Unitive Int Ltd Löthöcker-herstellungsverfahren und strukturen mit einer titan-sperrschicht
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
EP0819318B1 (en) * 1995-04-05 2003-05-14 Unitive International Limited A solder bump structure for a microelectronic substrate
US5620131A (en) * 1995-06-15 1997-04-15 Lucent Technologies Inc. Method of solder bonding
US5874782A (en) * 1995-08-24 1999-02-23 International Business Machines Corporation Wafer with elevated contact structures
KR100438256B1 (ko) * 1995-12-18 2004-08-25 마츠시타 덴끼 산교 가부시키가이샤 반도체장치 및 그 제조방법
US5851911A (en) 1996-03-07 1998-12-22 Micron Technology, Inc. Mask repattern process
US5736456A (en) * 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US5793116A (en) * 1996-05-29 1998-08-11 Mcnc Microelectronic packaging using arched solder columns
US5903058A (en) * 1996-07-17 1999-05-11 Micron Technology, Inc. Conductive bumps on die for flip chip application
JP3413020B2 (ja) * 1996-07-17 2003-06-03 株式会社東芝 半導体装置の製造方法
US5902686A (en) * 1996-11-21 1999-05-11 Mcnc Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structures
JP3553300B2 (ja) * 1996-12-02 2004-08-11 富士通株式会社 半導体装置の製造方法及び半導体装置の実装方法
US6045030A (en) * 1997-03-13 2000-04-04 Raytheon Company Sealing electronic packages containing bumped hybrids
US6117299A (en) * 1997-05-09 2000-09-12 Mcnc Methods of electroplating solder bumps of uniform height on integrated circuit substrates
US5926731A (en) * 1997-07-02 1999-07-20 Delco Electronics Corp. Method for controlling solder bump shape and stand-off height
US5990472A (en) * 1997-09-29 1999-11-23 Mcnc Microelectronic radiation detectors for detecting and emitting radiation signals
US5962151A (en) * 1997-12-05 1999-10-05 Delco Electronics Corp. Method for controlling solderability of a conductor and conductor formed thereby
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
US6595408B1 (en) 1998-10-07 2003-07-22 Micron Technology, Inc. Method of attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux prior to placement
US6268275B1 (en) * 1998-10-08 2001-07-31 Micron Technology, Inc. Method of locating conductive spheres utilizing screen and hopper of solder balls
US6139972A (en) * 1998-10-26 2000-10-31 Agilent Technologies Inc. Solder paste containment device
JP3667184B2 (ja) * 1999-02-26 2005-07-06 住友ベークライト株式会社 半導体装置
JP3287328B2 (ja) * 1999-03-09 2002-06-04 日本電気株式会社 半導体装置及び半導体装置の製造方法
US6649533B1 (en) * 1999-05-05 2003-11-18 Advanced Micro Devices, Inc. Method and apparatus for forming an under bump metallurgy layer
US6332988B1 (en) 1999-06-02 2001-12-25 International Business Machines Corporation Rework process
US6544880B1 (en) * 1999-06-14 2003-04-08 Micron Technology, Inc. Method of improving copper interconnects of semiconductor devices for bonding
US6570251B1 (en) * 1999-09-02 2003-05-27 Micron Technology, Inc. Under bump metalization pad and solder bump connections
KR100319813B1 (ko) 2000-01-03 2002-01-09 윤종용 유비엠 언더컷을 개선한 솔더 범프의 형성 방법
US6387793B1 (en) * 2000-03-09 2002-05-14 Hrl Laboratories, Llc Method for manufacturing precision electroplated solder bumps
US6437669B1 (en) * 2000-09-29 2002-08-20 Applied Micro Circuits Corporation Microwave to millimeter wave frequency substrate interface
DE60108413T2 (de) 2000-11-10 2005-06-02 Unitive Electronics, Inc. Verfahren zum positionieren von komponenten mit hilfe flüssiger antriebsmittel und strukturen hierfür
US6863209B2 (en) 2000-12-15 2005-03-08 Unitivie International Limited Low temperature methods of bonding components
US6884313B2 (en) * 2001-01-08 2005-04-26 Fujitsu Limited Method and system for joining and an ultra-high density interconnect
US6793792B2 (en) * 2001-01-12 2004-09-21 Unitive International Limited Curaco Electroplating methods including maintaining a determined electroplating voltage and related systems
JP4656275B2 (ja) * 2001-01-15 2011-03-23 日本電気株式会社 半導体装置の製造方法
US6419148B1 (en) 2001-01-23 2002-07-16 Orbotech Ltd. System for forming bumps on wafers
US6762122B2 (en) * 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
TW536766B (en) * 2002-02-19 2003-06-11 Advanced Semiconductor Eng Bump process
TW521359B (en) * 2002-02-20 2003-02-21 Advanced Semiconductor Eng Bump fabrication process
TWI239578B (en) * 2002-02-21 2005-09-11 Advanced Semiconductor Eng Manufacturing process of bump
US7547623B2 (en) 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US7531898B2 (en) 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
AU2003256360A1 (en) 2002-06-25 2004-01-06 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US6987307B2 (en) * 2002-06-26 2006-01-17 Georgia Tech Research Corporation Stand-alone organic-based passive devices
US6900708B2 (en) * 2002-06-26 2005-05-31 Georgia Tech Research Corporation Integrated passive devices fabricated utilizing multi-layer, organic laminates
US7260890B2 (en) * 2002-06-26 2007-08-28 Georgia Tech Research Corporation Methods for fabricating three-dimensional all organic interconnect structures
US6780751B2 (en) 2002-10-09 2004-08-24 Freescale Semiconductor, Inc. Method for eliminating voiding in plated solder
AU2003301632A1 (en) 2002-10-22 2004-05-13 Unitive International Limited Stacked electronic structures including offset substrates
US6897141B2 (en) * 2002-10-23 2005-05-24 Ocube Digital Co., Ltd. Solder terminal and fabricating method thereof
US6796482B2 (en) * 2002-10-31 2004-09-28 Freescale Semiconductor, Inc. Phase separated system for fluxing
DE10301934A1 (de) * 2003-01-20 2004-07-29 Epcos Ag Elektrisches Bauelement mit verringerter Substratfläche
TWI225899B (en) 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
US7489914B2 (en) * 2003-03-28 2009-02-10 Georgia Tech Research Corporation Multi-band RF transceiver with passive reuse in organic substrates
TWI221334B (en) * 2003-06-30 2004-09-21 Advanced Semiconductor Eng Bumping process
TWI223882B (en) * 2003-06-30 2004-11-11 Advanced Semiconductor Eng Bumping process
US7244671B2 (en) * 2003-07-25 2007-07-17 Unitive International Limited Methods of forming conductive structures including titanium-tungsten base layers and related structures
US7049216B2 (en) 2003-10-14 2006-05-23 Unitive International Limited Methods of providing solder structures for out plane connections
US7427557B2 (en) * 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
US7410833B2 (en) * 2004-03-31 2008-08-12 International Business Machines Corporation Interconnections for flip-chip using lead-free solders and having reaction barrier layers
TW200603698A (en) 2004-04-13 2006-01-16 Unitive International Ltd Methods of forming solder bumps on exposed metal pads and related structures
US8345433B2 (en) * 2004-07-08 2013-01-01 Avx Corporation Heterogeneous organic laminate stack ups for high frequency applications
JP2006032851A (ja) * 2004-07-21 2006-02-02 Mitsui Mining & Smelting Co Ltd 被覆銅、ホイスカの発生抑制方法、プリント配線基板および半導体装置
US7252514B2 (en) * 2004-09-02 2007-08-07 International Business Machines Corporation High density space transformer and method of fabricating same
US20060205170A1 (en) * 2005-03-09 2006-09-14 Rinne Glenn A Methods of forming self-healing metal-insulator-metal (MIM) structures and related devices
US7932615B2 (en) 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7439840B2 (en) 2006-06-27 2008-10-21 Jacket Micro Devices, Inc. Methods and apparatuses for high-performing multi-layer inductors
US7808434B2 (en) * 2006-08-09 2010-10-05 Avx Corporation Systems and methods for integrated antennae structures in multilayer organic-based printed circuit devices
JP2010501116A (ja) * 2006-08-17 2010-01-14 エヌエックスピー ビー ヴィ エッチングステップ中の電極の適正なアンダーカットの試験方法
US7989895B2 (en) * 2006-11-15 2011-08-02 Avx Corporation Integration using package stacking with multi-layer organic substrates
US7569164B2 (en) * 2007-01-29 2009-08-04 Harima Chemicals, Inc. Solder precoating method
CN101234455B (zh) * 2007-01-30 2012-03-28 播磨化成株式会社 焊锡膏组合物及焊锡预涂法
EP1952935B1 (en) * 2007-02-01 2016-05-11 Harima Chemicals, Inc. Solder paste composition and solder precoating method
US7713860B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump on I/O pad
TWI446843B (zh) * 2007-12-11 2014-07-21 Unimicron Technology Corp 線路板及其製程
US7888259B2 (en) * 2008-08-19 2011-02-15 Ati Technologies Ulc Integrated circuit package employing predetermined three-dimensional solder pad surface and method for making same
KR101022942B1 (ko) 2008-11-12 2011-03-16 삼성전기주식회사 흐름 방지용 댐을 구비한 인쇄회로기판 및 그 제조방법
US9142520B2 (en) * 2011-08-30 2015-09-22 Ati Technologies Ulc Methods of fabricating semiconductor chip solder structures
KR101774938B1 (ko) 2011-08-31 2017-09-06 삼성전자 주식회사 지지대를 갖는 반도체 패키지 및 그 형성 방법
US8946891B1 (en) * 2012-09-04 2015-02-03 Amkor Technology, Inc. Mushroom shaped bump on repassivation
US20150195912A1 (en) 2014-01-08 2015-07-09 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Substrates With Ultra Fine Pitch Flip Chip Bumps
US9949378B2 (en) 2014-04-14 2018-04-17 Presidio Components, Inc. Electrical devices with solder dam
FR3050865B1 (fr) * 2016-05-02 2018-10-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation d'interconnexions conductrices sur un substrat et interconnexions ainsi obtenues
US11676932B2 (en) * 2019-12-31 2023-06-13 Micron Technology, Inc. Semiconductor interconnect structures with narrowed portions, and associated systems and methods
KR20250061993A (ko) 2023-10-30 2025-05-08 가톨릭대학교 산학협력단 재난 대응 하·폐수 처리시설의 자산관리방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0313082A2 (en) * 1987-10-21 1989-04-26 Kabushiki Kaisha Toshiba Semiconductor device with bump electrode and method of manufacturing the same
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3986255A (en) * 1974-11-29 1976-10-19 Itek Corporation Process for electrically interconnecting chips with substrates employing gold alloy bumps and magnetic materials therein
JPS54128669A (en) * 1978-03-29 1979-10-05 Nippon Denso Co Ltd Flip chip element
US4273859A (en) * 1979-12-31 1981-06-16 Honeywell Information Systems Inc. Method of forming solder bump terminals on semiconductor elements
DE3685647T2 (de) * 1985-07-16 1993-01-07 Nippon Telegraph & Telephone Verbindungskontakte zwischen substraten und verfahren zur herstellung derselben.
FR2588121B1 (fr) * 1985-10-02 1990-02-23 Bull Sa Procede et dispositif de soudage d'elements sur les plots correspondants d'une plaquette telle que notamment une plaquette de circuits integres de haute densite
US4878611A (en) * 1986-05-30 1989-11-07 American Telephone And Telegraph Company, At&T Bell Laboratories Process for controlling solder joint geometry when surface mounting a leadless integrated circuit package on a substrate
US4763829A (en) * 1986-06-04 1988-08-16 American Telephone And Telegraph Company, At&T Bell Laboratories Soldering of electronic components
EP0263222B1 (en) * 1986-10-08 1992-03-25 International Business Machines Corporation Method of forming solder terminals for a pinless ceramic module
US4752027A (en) * 1987-02-20 1988-06-21 Hewlett-Packard Company Method and apparatus for solder bumping of printed circuit boards
JP2544396B2 (ja) * 1987-08-25 1996-10-16 株式会社日立製作所 半導体集積回路装置の製造方法
US4817850A (en) * 1988-03-28 1989-04-04 Hughes Aircraft Company Repairable flip-chip bumping
US4893403A (en) * 1988-04-15 1990-01-16 Hewlett-Packard Company Chip alignment method
US4840302A (en) * 1988-04-15 1989-06-20 International Business Machines Corporation Chromium-titanium alloy
US5024372A (en) * 1989-01-03 1991-06-18 Motorola, Inc. Method of making high density solder bumps and a substrate socket for high density solder bumps
US4940181A (en) * 1989-04-06 1990-07-10 Motorola, Inc. Pad grid array for receiving a solder bumped chip carrier
US5154341A (en) * 1990-12-06 1992-10-13 Motorola Inc. Noncollapsing multisolder interconnection
US5152451A (en) * 1991-04-01 1992-10-06 Motorola, Inc. Controlled solder oxidation process

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0313082A2 (en) * 1987-10-21 1989-04-26 Kabushiki Kaisha Toshiba Semiconductor device with bump electrode and method of manufacturing the same
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE Transactions on Components, Hybrids, and Manu- facturing Technology, Vol 14, No 3, September 1991, Edward K Yung et al., "Electroplated Solder Joints for Flip-Chip Applications", pp. 549-559, see page 550 col. 1 line 7 - line 31, page 551 col. 1 line 11 - page 552 col. 1 line 39, page 555 col. 2 line 45 - page 556 col. 2 line 53; see fig 1 *

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ES2106194T3 (es) 1997-11-01
JP2842692B2 (ja) 1999-01-06
EP0603296A1 (en) 1994-06-29
JPH07502147A (ja) 1995-03-02
US5162257A (en) 1992-11-10
DE69221627D1 (de) 1997-09-18
CA2116766A1 (en) 1993-04-01
ATE156935T1 (de) 1997-08-15
KR0186061B1 (ko) 1999-04-15
KR940702644A (ko) 1994-08-20
US5293006A (en) 1994-03-08
CA2116766C (en) 1999-02-16

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