TW200417B - - Google Patents
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- Publication number
- TW200417B TW200417B TW081107808A TW81107808A TW200417B TW 200417 B TW200417 B TW 200417B TW 081107808 A TW081107808 A TW 081107808A TW 81107808 A TW81107808 A TW 81107808A TW 200417 B TW200417 B TW 200417B
- Authority
- TW
- Taiwan
- Prior art keywords
- solder
- layer
- pad
- block
- metallurgical
- Prior art date
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Classifications
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- Y10T29/49117—Conductor or circuit manufacturing
Description
200417 A 6 B6 五、發明説明i f ) f發明領域] , \: 本發明關於徹電子說置的製造法,持別是閟於形成供 微電子基片所用的電子及機滅聯结的方法,及利用此種方 法所製造的聯結。 「發明背景] „ • % 高性能微電子_置經常使甩焊接球或焊接塊進行與其 他微電子_置之間的電子聯結。舉例而言,吾人可能利用 V··':. 焊接球或焊接塊,而電子式地聯结一種弗番 -—l-a-r-g-e scale in t a-β ra ion 晶片至一電路板 或其iit :穴層包装基片。此聯结科技也被稱為”受控的崩裂 晶 Η 礙结-C 4 ι Controlled Coiiapse Chip C ο η n a ο ΐ i o a -C 4 )或”倒装法(f 1 i ρ - c h i ρ ) ” ,本文也將稱之為” 焊接塊”。 由I B H所發展的原始焊接塊科技中,首先夾一値陰影 掩樓到一積體電路片,然後利用蒸發焊料,透過陰影掩模 的孔,而形成焊接塊。也有人尋求以電鍍製程來製造焊接 塊,持別用來處理較大的基Η及較小的焊接塊。在此製程 中,一 ’’ j·旱接塊之下的冶金 ( u n d 3 r - b u a p m e ΐ a 1 1 u r g :/ 經濟部屮欠標';'1-局尚工消';?合作^卬?41 (請先聞讀背面之:;i意事項再填寫本頁) (UBM)) ”被用在一微電子基片(微電子基片有一些墊片 與之接镯),通常是利用蒸發或噴塗(濺射)。一片連續 的焊接塊之下的冶金層膜通常被舖在墊片之上及基片之上 而介於各墊片之間,以准許電流在鍍焊塊過程中流通。 為了界定焊塊在接觸墊片上成形的位置,利用攝影刻 表 +¾ Vt :4 »!中 S 句家埝 KC.NS > 〒·μ| 格(21 η X 297 公弩 ΐ 200417 A6 B6 五、洤叫説明f二) . 印35方式來描繪焊接塊3¾泣置,放置厚厚的一層宠 在該焊接塊之下的冶金1摸上及畫出該光致電阻的形狀以 暴露該垾接塊之下的冶金.1摸於該接镯墊Η之上Γ'外、,): 然後,利用形狀電鍍,焊接墊Η被形成在該焊接塊之下的 冶金層漠玻暴露於該接壤Β Μ之外的S域:.被鍍的焊接 塊堆積在光敏電阻的凹穴甲,透過接赛墊Η。然後,介於 :1被鍍的焊接墊Η之間的焊接塊之下的冶金層膜被蝕刻( 以焊接塊作為蝕刻掩模)μ攱壤介於焊接塊之間的電子聯 结:U_S. Patents 4,35 :3, 32:3 ta Dishon t 己被讓渡給本 !案的申請人、;4,9 4 0 . 1 3 1 ί : J u s k e y, J r . 9 t a I · ; a n d 4 , 7 S 3,3 2 d邰钶_ 了’ 一圣译接魂的袈造方 <去: 言: 不幸的是,在利用邁述專利所討論的製程來製造焊接 塊時,不容易保護焊接塊在接獨墊片上的基部。保護焊接 塊的莶部是重要的,s a焊接塊的基部是用來密封接觸墊 η:上述專利所討論的製程绖常降低焊接塊的基部,此舉 暴露了绱在下方接獨μ η且導致機械或電子失靈& 焊接塊的基部可能由於上述製程中至少兩画步驟而愛 >.·;十 」'」λ —, j .1印I a f的.1 ? 一譽的弋窀電阻層部有先 埤濟郎屮史標 fN 工-νί,'κιν合fift卬¾ (請先聞讀计面之注意事項再堪坏本頁) •訂丨· 天的扭曲菱形,光敏電阻1無:去對齊於接觸塾。通常,使 " '! t- 甩一乾式厚摸光敏電阻:如d~u n t R I S T Q N光敏電阻)或 塗上多層的液光敏電阻,以累積足夠的被鍍的焊接塊的證 積。通常使用的膜的厚度是數十激米(例如5 0微米)的 等级。厚膜光敏電阻必須在接觸墊的上方被精確地繪出形 3 200417 A6 B6 五、發明説明(3 ) 狀,而沒有任何不對齊或扭曲變形。不幸地,對乾式厚膜 光敏電阻而言,焊接塊位置形狀的扭曲變形可能肇因於光 敏電阻不良地附著於平滑的焊接塊下方冶金層。透過厚膜 光敏電阻器及封面層的光散射,及厚膜光敏電阻器發展過 程中不準確的持性,也造成在接觸墊上方的厚膜光敏電阻 器罩的扭曲變形。對多層的液態光敏電阻器而言,一些冽 如因為長時間的烘烤所造成的光敏電阻 > 的硬化及邊緣焊 珠成形的等等因素都可能造成在接镯墊上方的光敏電阻器 罩形狀的杻曲變形。依上所論,结果的焊接塊通常不覆蓋 (請先KI讀背面之注意事項再填寫本頁) 經濟部十处標爷局13;工消'>^合作|1印皙 塊待介確過表, II 形 的 SJ3C。 , 了 行片此 供所 塊 焊蝕刻為進基因 成法 接 是侵蝕 。要屆 η : 形方 焊 3 方被结需整部性 可種 成 原下是聯常在基靠 的此 形 的塊ft子通生的可 良用 在 要接通電,發塊的 改利 可 主焊 層的層 地接面 經及 種 III對金 間金勻 焊方 種, 一 二的冶之冶均小兩 一法 供 第 中方塊方法縮硪 供方 提 的程下接下無常锞 提的 於 部過塊焊塊常通¾於塊 在 基刻接各接經刻子 在接 的 的蝕焊壞焊刻蝕電述的焊 。目 塊學 ,破的蝕度的概目的塊脑 接化述以要為過结明個用接 一 焊的所 ,需因種鞴發一所焊另 「.小層上 間不是這塊 的結的的 ¾縮金如 之有這 ,接 明聯良明 觸能冶 ,塊所 ,而淳 發置改發 接一OJ的說接去刻然T本設經本 想方地焊除蝕 。泜 子的 整 下定於保度面洚 電成 •5t_ •打— 200417 A 6 B6 五、發明說明(4) 過程中深留焊接塊基部的方法:. (锜先閱請背面之注意事峭再填寫本頁) 不發明的又一値目的在於減少在形成焊接塊的過程中 對焊接塊下部的浸蝕: 本發明的又一値目的在於降低介於焊接塊及其下方的 接辑塾之間的不良對齊:, .訂· 根據本發明,利用軟焊或在独刻介於焊接墊之間的在 焊接塊下方冶金層之前先熔融焊接塾,達成上述目的。介 於焊接塊下方冶金層與焊接塊之間的夾層因此披形成在焊 接塊及接觸墊之間,在焊接塊的基部上,在蝕刻在焊接壤 下方冶金1之前,:,依上所論,至少介於焊接塊及接觸墊之 間的淳接J·鬼下万<&…五.層的部刀· ί皮磚爱為/「於澤接凉丨、方占 金層及焊接塊之間的夾層,在蝕刻在焊接塊下方冶金層之 前:最好,焊接塊下方冶金層包括铜製頂層及使用鉛一錫 焊钭時,所有銅製頂層被轉愛為銅及錫製的夾層。 •線. 金屬間的夾層可抵抗被用來蝕刻焊接塊下方冶金層的 蝕刻液3因此,焊接塊下方冶金層可以被移動於接鶚墊之 間,而同時保持冶金層在焊接塊的基部。依上所論,用本 1明的方:去來莖主焊接埤’1 t産主最量的澍涅凄魂荃部 的浸蝕,因此保持了焊接塊基部的尺寸,而接镯墊也不會 波暴露3焊接塊聯结的電子及機娀的可靠度也被強(匕。 本發明降低焊接墊及位於其下方接觸墊之間的不良對 齊,fc容忍在畫出塊接塊累積層的形狀中的杻曲變形。待 定地說,一連缥的焊接塊下方冶金層詖形成在接觸墊及徹 -7 - ^ 'xc;^ ν : n ·.> *ι 200417 A6 B6 五、發明説明(Jr ) 電子基片二者之上,介於接觸墊之間。焊料阻隔(d a π s) 形成在焊接塊下方冶金層上,介於接觸墊之間,焊料阻隔 暴露該焊接塊下方冶金層在接觸墊之上。被暴露的在接觸 墊上的該焊接塊下方冶金層界定焊接塊基部的位置。在軟 焊的過程中,焊接料會回收或擴散至這些區域, 焊料阻隔(d a m s或s t q p s )最好是從一薄膜層(约為 1微米或更小的等级),如一薄層的鉻(約為1 5 0 0徹 米),其有效地附著於焊接塊下方冶金層3應用習用的積 韹電路攝影刻印法,準確地對齊焊料阻隔到其下方的接觸 墊:最好利用1 i f t - a f f技術來形成焊料阻隔的形狀:當然 也可以用具他《ί影刻印技術來形成焊科®隔的形狀3 經濟部屮处櫺个局SC工消';'合作;1卬製 (請先閱讀背面之注意事項再填寫本頁) 焊接累積區域被形成在焊料阻隔上。這些區域(可以 是厚膜光敏電阻器,約為5 0徹米的等级)僅需累積焊接 體積。他們不需被用作對齊目的,因為焊料阻隔提供精確 對齊3依上所論,厚膜焊接累積區域的不良對齊及杻曲變 形不會縮小在接镯塾上方的焊接塊基部。焊接塾被電鍍到 在接觸墊上方的基片上,在焊接塊下方冶金層部分由焊接 S湯暴31的遙域及焊接累堊域二f上:然後.可以涂去焊 接累積區域。 然後,在移走介於接觸墊之間的焊接塊下方冶金層之 前,焊料被熔化以形成一焊接塊,這値焊接塊有一片介於 焊接塊及在接觸墊附近的焊接塊的基部的焊接塊下方冶金 層之間的金属間夾層。舉例而言,在該焊接塊下方冶金層 A6 B6 20041?
五、發明説《I (請先聞讀背面之注意事邛再填寫本頁) •襄· •訂…:
經濟部屮史標"勾W工^"合作沁印W 的最上方的成分是銅且使用 铜/錫金1間夾1 s在軟焊 的_向灌敎及焊科的未厍滿 焊料阻隔及焊接塊下方 庚用至少一種轴刻液,這種 及電子的可靠 圖式簡介 圖1至圖5是敗據本發
小於蝕 绖被形 液的影 成的混 來刻 \R 下方冶 «箸保 及電子 此 接墊及 玻形或 :¾ 、丨工: ν〇 -·;·^\ U〆 塊邊緣 論,本 形改善 刻焊接 成在焊 鎏。持 合物可 , 這 金.1的 存诨接 的可靠 外,吾 焊接塊 在每茴
π m 'M 及在焊 發明産 了機滅 塊及焊 接塊的 定地說 以波用 些独刻 明所得 独刻或 塊的基 性: 人fc發 下方;台 焊接塊 :旱接宽 接塊下 生一種 接塊上 基部, ,由氫 來蝕刻 液部不 到的焊 焊接墊 部的幾 現,在 金罾二 基部處 々Γ7 ‘·(- 方的接 新的焊 傳統鉛 過程中 ,及控 冶金層 註刻液 方冶金 焊接塊 氣化銨 銅,氫 會影謇 接魂的 不良對 何形狀 /錫焊 ,焊料 制焊接 被蝕刻 独刻金 層。即 便比較 及少量 氯馥基 铜/旻 基部不 齊/杻 ,本發 料時, 阻隔防 塊基部 以隔绝 =¾ 3B Ttr
* 13J 然金驀 不容易 的過氧 蝕刻液 金蜀間 羞a為 曲變形 明才能 本發明的軟焊步驟中,介於焊 者之間有側向活動。依前論, 的金1間夾層延伸過每画焊接 一 s部:渣蕕吾部提洪對淳m 獨墊的邊综二者的保護,ί衣前 接塊外形,這種新的焊接塊外 度, 明,在一徹電子基片上,形成 9- 便形成一 止焊接塊 的尺寸。 焊接塊, 層的速度 間夾層已 受到蝕刻 化氫所混 可以被甩 夾層d 對焊接魂 而變小3 強化機減 A6 B6 20041^ 五、發明説明(Ί) 焊接塊的過程中,該微電子基片的橫剖面視圖3 圖6是依據本發明所形成的一値焊接塊的描瞄電子顯 微鏡相片3 最佳實施例詳述 以下将配合所附圖式,更詳細地說明本發明,圖式所 示的是本發明的最佳實施例。然而,本發明可以許多不同 形式來實施,因此本發明不應該局限於圖式中的實施例, 實施例被用來使本發明所掲示的内容連貫及完整,且將充 分傳達本發明的範蹯给熟於此技S者。在所有的圖式中, 相同的參數指的是相同的元件。 請參考_ 1 ,如函所示,一礅電子基片1 ύ的上S有 一些接镯墊1 2。習於此技《者應該了解微電子基片1 ◦ 可以是一積體電@晶Η , —電子電路板或徹電子套装板, 或任何一種需要電子及機滅聯结的基片。本發明是利用習 知的技術來安装接觸Ml 2至基片10上面,因此,不持 別介紹二者之間的聯结關偽。接觸墊通常是鋁,因為鋁常 被用來製作積體電路晶片,雖然,其他金屬及金屬複合物 C可G波甩來製5積違電路及其也基片: 圖1也頴示一鈍化電介質1 4被安排在基片1 0上, 其鈍化電介質1 4的形狀正可以暴露接觸墊1 2 ,使用傳 統的等離子態或反應式鐵蝕刻或其他習知畫圖形的技術。 —tr ; 一連缥的在焊接塊下方冶金層1 6 •安基片1 0的上 方,焊接塊下冶金層1 6的部分覆蓋在接觸墊1 2上面, -1 0- ^ ;·5. ^ ^ ''ifCNS ' ^ ν?〇; Λ (請先閱讀计面之注素事項再填寫本頁) •装· .訂. 200417 A6 36 五、诠明説明(y ) 焊接塊T方冶金層L 3的其他部分則介於這些接獨墊1 2 之間,熟於此技藝者*該十分了解,該焊接塊下方冶金.層 1 6通常包含一(底部:;鉻層(约1 0 0 0埃厚)靠近基 Η 1 0及接镯墊1 2 ,其功能是作為該焊接塊下方冶金層 35黏合1及障礙,一頂銅層徽米厚)通常凌吊 經濟部屮失標苓局^:工^''合作^卬54: ο 用棟 在暴 ,上约最焊部的産因脱以這 ο 利接 排 -分 2.¥成的的¾來是 一 可在 ο 以焊 安間部 1 用 形缥要薄法這用 ,排 1 可該 被 之的墊利的連需 舆刻 ,利層安 ^明成 。8 2 方獨以 8 一不 .蝕形 。隔波 (, 發形绍 1 i 上接可 1 成去 Π- 影變 展阻將 層本來介層 M2在明層形除丨 攝曲發料塊 0 , 別止鐲 1 接發隔面來 1 路扭的焊接 \ 間塗待阻接墊直本阻上術 隔電及精的焊 络之噴此接於鐲的 。料的技沮護齊更方後 的層或在焊7>接 6 蓋焊 6 刻 抖 漬對 及 上以 相銅 發不或 ,在 1S,, 1 蝕 用良合 2 ί 定及蒸文隔面 6 層所隔層或 的 利不黏1溝 1 層如本阻Χ1 金 S 阻金雜 栗 -的 的墊的 及鉻諸 ,钭 6.1冶 1 钭;έ脫3下低佳 >觸8 , 該 ,此焊 i 金方隔焊方 HE 的之較較"、在 1 1於1因 一 € 冶下沮钛下利.1較有 ,位層 金介技 , -茧方塊v-參或塊再^相以射接隔 接而位 6 2(ο下接$鉻接後有器可散直阻 揮排定 la 万塊焊波的焊然 具阻案光走料 可安 膜層考 F 接該未 埃 該 ,生電 画 的移焊 1 被薄屬 ® 塊焊 ,分 ο 在 1 荖敏的低來於 為丨的金諳接該之部 ο 先隔而光膜較術介 作厚统方 焊出言的 5 是阻 ,膜薄有技到 來埃傳下 該露變方 1 好料分厚生 為離得 (锖先閱讀背面之注意事項再填寫木頁) •襄· •打:: " t :Λ ri ^ s ! r\·^
20041V A6 B6 五、诠明説明("/ ) 痼部位)之間的對齊,及其下方的接觸墊1 2。 請參考圖3,在焊料阻隔18上面形成焊料累積區域 2 8 3這些區域可以是厚膜光敏電阻器。即然焊料累積區 域披用來累積焊料體,且不需被用來與接觸墊1 2對齊, 它1_門之間不良的對齊及扭曲菱形不會縮小焊接塊的基部。 請繼缠參考圖3 ,在基片1 0上方形成焊料墊20, 通常是用電鍍的方式來實施。在電鍍的過程中,填滿焊料 累積區域中空間2 8需要體積。焊料墊2 0可以被容纳在 焊料阻隔1 8之間的溝中,或被允許延伸過焊料阻隔,如 圖3所示。然後,焊料累積區域2 8可被移走3 現圧請参考圖4 ,汪移走7「於接觸兹1 £之間的該焊 ϋ訂龍M20 —熳’』詩 痼焊接塊24的基部形成介於金屬中間的夾層2 2。焊接 塊下方冶金層1 6最頂部的成分是銅時(厚約1微米)且 使用傳統的鉛一錫焊料(錫所佔重量比約為百分之五), 則焊接塊下方冶金層1 6所形成的的介於金屬中間的夾層 2 2是三銅化錫3熟於此技藉者應該了解一薄層的焊接塊 下方冶金,116 :通常其底部是鉻層及定相的铭一铜1, 圖4未顯示)可保持在介於金屬間夾層2 2及接觸墊1 2 之間的接觸墊1 2上面。 為了確保在該焊接塊下方冶金層1 6頂層的銅能幾乎 轉變成金屬間夾層2 2 ,丨軚焊最好以高於焊料熔點的溫度 來進行1— 2分鐘。在定相的絡一銅區域的不轉變的銅防 -1 2- (請先閑讀计面之注意事項再填寫本頁) ,策· * J^:: 20041? A 6 B6 五、S'明說明>:!C ) 止淳科塊脫雞詻站合1,所以,tt強it 了结溝的整_性:. 在軟焊的過程干,焊接阻隔1 3防止焊料的刨向擴散及跨 越,所以,1£控制了诨接塊基部的尺可:钦焊可以在空氣 中進行或是在諸如氖氣的化學鈍氣流通的環境中來進行, 通常是有助熔液,&可以在諸如氫氣的降泜的流通環境中 來進行,通常不芾肋溶液:如熟於此技藝者所知一般,Μ 該在蝕刻該焊接塊下方冶金層1 6及焊料阻隔1 8之前, 清除肋熔液殘渣(如杲産生): 圖4也漂示,在軟焊的過程中,在焊料2 0及焊接塊 下方冶金層1 6之間存在一制向的相互作弔:依上所論, 菝形职圧每涸焊接魂F面的βi .¾中周的夾/¾ s :s —召 或脊2 6 ,每個唇或脊2 6通常浞焊接塊延伸數微米:,1 或脊2 6可能波用來指3拫據本發明所形成的焊接塊,因 為,若介於各画接蕷M L 2 2間的焊接塊下方冶金層1 6 在軟焊的過程之前已绖波移走,則焊料20與焊接塊下方 冶金層1 6之間的_向相互作用不會發生:唇或脊2 6也 對焊接塊的基部提供更高程度的保護3 it因此産生了一種 S; ra S -Ϊ* 3 IS :¾ ^W*S. U _·*'«- « -J - r 广 J-·、 ^ ^ 請参考麗15,介於各接獨墊12之間3¾焊钭狙塥13 及焊接塊下方冶金層1 6被移走,而保留波軟焊過的if f斗 塊2 4的基部;,即然介於焊接塊2 4及接镯墊1 2之間的 焊接塊下方冶金層1 6的頂層的銅已經波轉變為介於金屬 中間的夾層,便可以移走介於各(固接獨Μ ί 2之間的焊科 (锖先閱讀计面之注奇事項再填寫本頁) •策* ,訂…· 把濟郎中丸檔·;'ι^Μ工^^合作汴卬製 夂 A ' 今:5 r jq 3 ,.r 20041? A6 B6 經濟部屮央i?-f-ri3工消'(''合作认卬" 五、發明災明(丨/ ) 阻隔13及留下來的焊接塊下方冶金層16,而不會除去 介於金屬中間的夾層3 —種蝕刻液或數種蝕刻液被用來蝕 刻介於金屬間的夾層2 2及焊料阻隔1 8及焊接塊下方冶 金層1 6,蝕刻介於金屬間的夾層2 2的速度必須小於蝕 刻焊钭姐隔i 3及焊料塊下方冶金層1 6的速度。最好, 這些蝕刻液在移走焊料阻隔1 8及焊接塊下方冶金層1 6 的同時,不會蝕刻介於金靥中間的夾層2 2。 舉例而言,若以鉻來做成焊料阻隔18,氫氛酸基蝕 刻ί夜,諸如 T r a n s e n e C S E 4 7 3可作為一有效的蝕刻液,而 由多量氫攱證及少5過氣化氫(通常其濃度高於在銅蝕刻 液甲的過化物的濃度)所混成的混合物是有效的3多S 蝕刻液可被用來除去定相的鉻一銅層及底部的鉻層3這些 蝕刻液中没有任何一種能夠蝕刻銅/錫金屬間夾層,也沒 有任何一種能夠蝕刻焊接塊2 4至一種可脱離的程度。熟 於此技ϋ者將明白,在蝕刻銅的過程中,可以保持整®設 置在蝕刻液中一段時間,直到完全除去介於焊接塊2 4之 間的銅3熟於此技ϋ者也将明白,本發明tfc可以使用其他 的Η刻衮及其他的通程來除走不霈的部分 依上所論,本發明提供一種較為優良的焊接塊製造過 程。發生在厚膜光敏電阻$的攝影蝕刻過程中的瑕疵無法 降低對齊的程度。此外,在蝕刻焊接塊下方冶金層1 6的 過程中,本發明也降低或避免蝕刻焊接塊24的基部3所 以,本發明能保留焊接塊2 4基部的幾何形狀。事實上, -14- (請先閱讀计面之注意事頊再填寫本頁) .¾. •訂:· · 線 200417 A 6 B6 五、發明説明(/ i ) 本發明的製程更進一步在厍接塊的基部形成一唇2 3,以 保護焊接塊2 4 ,因此,強化了電子及機滅兩方面的可靠 度:.圖6是利周一掃瞄’電子顯微篾對液據本發明所産生的 一焊接塊2 4所抬的掃瞄電子頭激照片,圖6顯示焊接塊 2 4 , 1 2 6 及基 Η 1 0 : 熟於此技ϋ者将明白,本發明利用在除去介於接辑墊 1 2之間的焊接塊下方冶金層1 6之前軟焊焊料2 0 ,不 受不良對齊/扭曲爰形的影銮,而能夠對焊料塊2 4的基 部産生較少的侵註:舉例而言,在某些微電子基片的設計 中,設計者所設計出來的焊接塊的基部可能大於接镯墊, 因此,焊抖塊與接獨墊,2間的封齊就相對地不重要。焊接 塊與接觸對之間的不良對齊或扭曲變形可以被忍受, 本文將在以下説一種簡化的而又能容忍介於焊接塊及 接獨墊之間的不良對齊或杻曲愛形:,焊接塊下方冶金層可 .以包含與上述者相同的底部鉻層,定相的鉻/銅層及頂部 的銅層。然而,在上述的頂部銅層之上再設一第二鉻層: 如上述般來形成及畫出一焊钭累積層,例如厚摸光敏電阻 is , 3: a s , τ形或上;i右專嵙阻隔響_ 然後,移動第二鉻層至焊料累積層的穴中,再液上述 方式來電鍍焊料3移走焊钭累積1之後,軟焊這些焊料, 以形成一介於金屬中間的夾層並如上述般保護焊接塊的基 部3介於接镯墊之間的第二鉻層避免波軟焊的焊料跨越3 第二鉻層可能無法被精確地對齊到接觸墊,但由於基片的 -1 5 - ί請先聞讀背面之注意事邛再填寫本頁) •装· .訂:: 經濟部屮史|?平砀嵙工^';'合作;1卬" 艮吆:·\ ?、t ..七 3 1 ',!/〇丨:;' τ !卜-1 了十,
2〇〇4iV A6 B6 五、發明說明(ί $ ) 設計,這樣的不良對齊相對就不是很重要。由於除去介於 接觸墊之間的焊接塊下方冶金層之前軟焊這些焊料,蝕刻 焊接塊下方冶金層的過程中,焊接塊的基部仍然被保護。 上述說明及所附圖式掲示本發明的數種較佳實施例, 雖然本文使用了待定的名詞,這些名詞僅被用來描述而不 被用來限制本發明,本發明的範醻應由以下的申請專利範 圍來界定。 (請先閱讀背面之注意事項再填寫本頁) •51· .打:: 經濟部屮丸標';'1-局負工消';*合作;-1卬" -1 6 衣饫分又t T丨Π (D's)甲1規巧Π1 η X ?Q7公弩)
Claims (1)
- B7 C7 D7 20041? 六、申請專利範圍 (請先閱讀背面之注急事項再塡寫本頁) 1 . 一種在一基片上面的接觸墊上面形成焊接塊的方法, 這種方法包括一列步驟: 在該接觸墊上面,及在該基片上於該接觸墊之間,形 成一焊接塊下方冶金層;然後 在該焊接塊下方冶金層上面介於該接觸墊之間形成焊 钭阻隔,該焊料阻隔讓該焊接塊下方冶金層暴露在該接觸 墊之外;然後 在該焊料阻隔上面形成焊科累積區域,該焊料累積區 / V,!- 域讓焊接a下方冶金層暴露在該接觸墊之外;然後 在該接諝塾之上形成焊钭μ,該焊料墊是在該接鶚墊 上面的焊接塊下方冶金;1的工面,該焊料Μ被該焊料阻隔 及該焊料累積區域所暴露;然後 軟焊該焊料塾以形成焊料塊,每個焊料塊有一介於該 焊接塊下方冶金層及該接觸塾附近的該焊科之間的金屬間 夾層;然後 利用至少一種蝕刻液來蝕刻介於該接觸墊之間的該焊 料阻隔及該焊接塊下方冶金層,該蝕刻液蝕刻該金屬間夾 .5的速度小於蝕刻該焊料姐隔1該辱接塊下方冶金1的速 度,藉此降低對該接觸墊附近的該焊接塊基部的浸蝕。 經濟部中央標準局貝工消费合作杜印髮 2 .如申請專利範圍第1項所述的方法,其中該形成 一焊接塊下方冶金層的步驟是在該基片上形成一鈍化層, 介於該接觸塾之間。 3.如申請專利範圍第1項所述的方法,其中該形成 B7 C7 D7 2004^ 六、申請專利範圍 (諸先閲讀背面之注意事項再填寫本頁) 一焊接塊下方冶金層的步驟所形成的該焊接塊下方冶金層 包括:該基片及該接觸墊附近的一鉻層,在該鉻層上面的 一介於鉻/銅之間的定相的夾層及在該絡/,銅夾層上面的 一銅層。 4 .如申請專利範圍第1項所述的方法,其中該形成 焊料阻隔的步驟包括下列步驟: 在該基片上面形成一薄膜焊料阻隔層,部分介於該接 觸墊之間且部分在該接觸墊之上;及 移走該薄膜焊料阻隔層在該接觸塾上方的部分。 5. 如申請專利範圍第4項所述的方法,其中該移走 該薄膜焊料阻隔層的部分的步驟包括移走在該接辑塾上方 的該焊料阻隔層的步驟。 6. 如申諳專利範圍第1項所述的方法,其中該形成 焊料的步驟包括鍍焊料至該接觸之上,在該焊接塊下方冶 金層上面,該焊接,塊下方冶金層被該焊料阻隔及該焊料累 積區域所暴露。 7. 如申請專利範圍第1項所述的方法,其中該軟焊 的步驟包括熔(t該焊科墊的步驟。 I ®濟部中央揉準爲貝工消費合作社印* 8. 如申請專利範圔第4項所述的方法,其中該軟焊 的步驟更包括軟焊該焊料塾以在該金屬間夾層之中形成一 唇的步驟。 9. 如申請專利範圍第1項所述的方法,其中該焊料 包括鉛/錫焊料,其中該焊接塊下方冶金層包括銅,且其 本纸張尺度適用中國®家樣準(CNS) T 4说格(210 X 297公釐) 經濟部中央標準局S工消费合作社印K A: 200417 C7 D7 六、申請專利範園 中該軟焊步驟包括軟焊該焊料墊以形成具有一銅/錫間金 屬夾層的焊接塊的步驟。 10. 如申請專利範圍第1項所述的方法,其中該形 成焊料累積區域的步驟包括在該焊料阻隔上面形成厚膜焊 料累積區域,以便在該形成焊科阻隔的步驟中包含該焊料 墊,的步驟。 11. 一種在一基片上面的接觸墊上面形成焊接塊的 方法,這種方法包括一列步驟: 在該接觸墊上面,及在該基片上於該接觸墊之間,形 成一焊接塊下方冶金層;然後 在該接觸墊Z上的該焊接塊下方冶金層上面形成焊料 區,介於該接觸墊之間的該焊接塊下方冶金層不承接任何 焊料;然後 利用軟焊該焊料,使在該接觸墊之上的該焊接塊下方 冶金層的部分轉變成介於該焊科塊下方冶金層及該焊料二 者之間的夾層,的步驟;然後 在該接觸墊之上形成焊料M,該焊料Μ是在該接觸墊 上面的焊接塊下方冶金荖的上面,該焊钭該焊钭阻隔 及該焊料累積區域所暴露;然後 軟焊該焊料墊以形成焊科塊,毎値焊料塊有一介於該 焊接塊下方冶金層及該接觸墊附近的該焊料之間的金屬間 夾層;然後 移走介於該接觸墊之間的該焊料阻隔及該焊接塊下方 本纸張ϋϋ用中3®家揉準(CNS)甲4觇洛(2U1 X 297二兮) ------------------------裝-------tr-------線 (請先閲讀背面之注意事項再塡寫本頁) 經濟部t央揉準房典工消费合作社印K 20041? Z C7 __D7 六、申請專利範面 冶金層,而保留該焊接塊下方冶金層在該接觸墊之上的部 分,藉此降低對該接觸墊附近的該焊接塊基部的侵蝕。 12. 如申請專利範圍第1 1項所述的方法,其中該 形成一焊接塊下方冶金層的步铤是在該基片上形成一鈍化 層,介於該接觭墊之間D 13. 如申請專利範_第1 1項所述的方法,其中該 形成一焊接塊下方冶金層的步驟所形成的該焊接塊下方冶 金層包括:該基片及該接觸墊附近的一鉻層,在該鉻層上 面的一介於鉻/銅之間的定相的夾層及在該鉻/銅夾層上 面的一銅層。 14. 如甲請專利範圍第1 i項所述的方法,其中該 形成該焊料的步驟包括鍍焊料至該接觸墊上面的該焊接塊 下方冶金層上面。 1 5.如申請專利範圍第1 1項所述的方法,其中該 形成焊料的步驟包括在該接觴上面的該焊接塊下方冶金層 上面形成焊料,而\不在該接觸墊之間形成焊料。 16. 如申請專利範圍第1 1項所述的方法,其中該 軟焊的步驟包括熔化該焊料墊的步驟。 17. 如申請專利範臞第1 1項所述的方法,其中該 轉變步更包括在利用軟焊該焊料而該金羼間夾層形成一唇 的步驟。 18. 如申請專利範圍第11項所述的方法,其中該 焊料包括鉛/錫焊料,其中該焊接塊下方冶金層包括銅, 夂纸張尺適用中围同家橒準(CNS〉ψ 1規格(210 X 297公兮) --------------------------裝------,玎------線 (請先閱讀背面之:玉意事項再填寫本頁> 20041'V c: D7 六、申請專利範圍 (請先閲讀背面之注意事項再填寫本頁) 且其中該轉變步驟包括使在該接觸墊上方的該焊接塊下方 冶金層轉變成一銅/錫間金屬夾層的焊接塊的步驟。 19. 如申請專利範圍第15項所述的方法,其中該 形成焊料的步驟包括下列步驟: 在介於該接镯墊之間的該焊接塊下方冶金層上面形成 焊料累積區域,該焊料累積區域使該焊接塊下方冶金層暴 露在該接觸墊之外;然後 在該接觸墊的上方的該焊接塊下方冶金層上面形成焊 料,該焊料累積區域不存在於該接觸墊之間。 20. 如申請專利範圍第13項所述的方法,其中該 肜顷一焊接塊τ万冶金層的步驟更a括在該_層上面形成 一第二鉻層的步驟,且其中該形成焊料的步驟包括下列步 驟: 在介於該接獨Μ之間的該焊接塊下方冶金層上面形成 焊料累積區域,該焊料累積區域使該焊接塊下方冶金層暴 露在該接觸墊之外;然後 移走在該接觸墊上方的該第二鉻層;然後 在孩接想墊的上方的該焊接塊下方冶金歴上面形成焊 料,該焊料累積區域不存在於該接觸墊之間3 經濟部中央標準局Λ工消费合作社印* 2 1 . —種供一徹電子基Η所用的内部聯結条統,該 条統包括: 在該基片上的多痼接觸墊; 多値焊接塊,每一個焊接塊被安排在在一値對應的該. 本纸張尺度適用中as家樣準(CNS)甲4規格(210 X 297公釐) 〇 0041'^ Α7 Β7 C7 D7 六、申請專利範圍 娌濟部中央標準渴員工消费合作社印製 夾至 基且 基數 基墊與 該 應 唇上 基 間展 C 子塊 子展 子觸至 , 對 形墊 子 屬延墊電接 電延 電接展 統 痼 國觸 電 金外觸徹焊 撤外 微該延 糸 一 該接 微 的向接一錫 一向 一一外 結 在 ,的 一 間塊該供 I 供塊 供每向· 聯 排 辱結 供 之接護的鉛。的接 的在塊 部 安 形聯 的 墊焊保述是層述焊 述是接 内 披 圓塊 述 觸該此所塊夾所該 所塊焊 的 塊 的接 所 接從藉項接間項從. 項接該 用 接 有焊 項 該唇以 1 焊屬 1 唇 1 焊從 。所 焊 都形 5 的該 ,2 該金 2 該 2 該是方H.-該 部球 2 應,方第中錫第中 第中唇上基 墊画 基該 第 對唇上圍其 \ 圍其 圍其該的子 辑一 的與。圍 其 一的範 ,銅範 , 範·中墊電 接每 塊至墊範 塊括墊利統 一利统 利统其觸徹 傾 , 接展觸利 接包* 專条是專条 專条 且接一 多塊 及焊延接專 焊層接請結層請结 請结塊該供 的接;形外該請 該夾該申聯夾申聯 申聯接的種 上焊面球塊護申 •,値間的如部間如部 如部焊结一 片形上該接保如 面毎属塊.内JB.内 ·内形聯 ·:基球墊値焊此 . 上於金接 2 的金 3 的 4 的球塊 5 括該® 觸 一形藉 6 墊介該焊 2 用該 2 用 。2 用的接 2 包在多接每球以 2 觸 ·該 所中 所米 所面焊 統 該 該, 接 層與 片其 片{»片上該 条 的 從方 ------------------------裝------ΤΓ------線 {請先閲讀背面之注意^項再填寫本頁> 本紙張尺度適明伞闻两家堞翠(CNS)甲.1祁JM'210 X 297公牮) ,0041^ 申請專利範圍 A7 B7 C7 D7 錫 。基向 I 唇子塊 鉛形電接 形圓微焊 球的一形 是層供球 塊夾的該 接間述從 焊屬所唇 形金項形 球錫 5 圓 該 \ 2 該 中銅第中 其一圍其 , 是範 , 統唇利统 条 形專条 结圓請結 聯該申聯 。 部中如部米 内其 .内徹 的且 7 的數 用塊 2 用展 所接 所延 Η 焊 Η 外 ------------------------裝------#------線 (請先閱讀背面之注意事項再塡寫本頁) 缦濟部中央櫺準局員工消费合作社印製 本纸張尺Λ適用士 19¾家浮準(CNS)甲4规济(2U1 X 297 Α兮)
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TW200417B true TW200417B (zh) | 1993-02-21 |
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AT (1) | ATE156935T1 (zh) |
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DE (1) | DE69221627T2 (zh) |
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-
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- 1991-09-13 US US07/759,450 patent/US5162257A/en not_active Expired - Lifetime
-
1992
- 1992-08-07 US US07/927,069 patent/US5293006A/en not_active Expired - Lifetime
- 1992-09-11 DE DE69221627T patent/DE69221627T2/de not_active Expired - Fee Related
- 1992-09-11 WO PCT/US1992/007722 patent/WO1993006620A1/en active IP Right Grant
- 1992-09-11 KR KR1019940700820A patent/KR0186061B1/ko not_active IP Right Cessation
- 1992-09-11 ES ES92919808T patent/ES2106194T3/es not_active Expired - Lifetime
- 1992-09-11 JP JP5506136A patent/JP2842692B2/ja not_active Expired - Fee Related
- 1992-09-11 AT AT92919808T patent/ATE156935T1/de not_active IP Right Cessation
- 1992-09-11 EP EP92919808A patent/EP0603296B1/en not_active Expired - Lifetime
- 1992-09-11 CA CA002116766A patent/CA2116766C/en not_active Expired - Fee Related
- 1992-10-01 TW TW081107808A patent/TW200417B/zh active
Also Published As
Publication number | Publication date |
---|---|
JP2842692B2 (ja) | 1999-01-06 |
DE69221627T2 (de) | 1998-01-08 |
CA2116766C (en) | 1999-02-16 |
KR940702644A (ko) | 1994-08-20 |
KR0186061B1 (ko) | 1999-04-15 |
WO1993006620A1 (en) | 1993-04-01 |
JPH07502147A (ja) | 1995-03-02 |
DE69221627D1 (de) | 1997-09-18 |
CA2116766A1 (en) | 1993-04-01 |
EP0603296A1 (en) | 1994-06-29 |
EP0603296B1 (en) | 1997-08-13 |
ES2106194T3 (es) | 1997-11-01 |
US5162257A (en) | 1992-11-10 |
ATE156935T1 (de) | 1997-08-15 |
US5293006A (en) | 1994-03-08 |
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